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Product Specification
Port Description
| Name / opt. VHD Name | Direction | Pin | Bank Power | Description |
|---|
| ADBUS0 | in | G9 | 3V_D | FTDI TCK |
| ADBUS1 | in | F10 | 3V_D | FTDI TDI |
| ADBUS2 | out | E10 | 3V_D | FTDI TDO |
| ADBUS3 | in | D9 | 3V_D | FTDI TMS |
| AVDD_SHDN | inout | G10 | 3V_D | AVDD Shutdown / AVDD OV/UV |
| BCBUS0 | - | D12 | 3V_D | FTDI (JTAG/UART, U4) / currently_not_used |
| BCBUS1 | - | E13 | 3V_D | FTDI (JTAG/UART, U4) / currently_not_used |
| BCBUS2 | - | E12 | 3V_D | FTDI (JTAG/UART, U4) / currently_not_used |
| BCBUS3 | - | F13 | 3V_D |
BCBUS4 | - | F12 | 3V_D | BDBUS0 | FTDI (JTAG/UART, U4) / currently_not_used |
| BCBUS4 | - |
B11BDBUS1 | FTDI (JTAG/UART, U4) / currently_not_used |
| BDBUS0 / FTDI_RXD | - |
A12BDBUS2 | UART FTDI U4 |
| BDBUS1 / FTDI_TXD | - |
B12BDBUS3 C11BDBUS4 | FTDI (JTAG/UART, U4) / currently_not_used |
| BDBUS3 | - |
B13BDBUS5 | FTDI (JTAG/UART, U4) / currently_not_used |
| BDBUS4 | - |
C12BDBUS6 | FTDI (JTAG/UART, U4) / currently_not_used |
| BDBUS5 | - |
C13BDBUS7 | FTDI (JTAG/UART, U4) / currently_not_used |
| BDBUS6 | - |
D11CONF_DONE | FTDI (JTAG/UART, U4) / currently_not_used |
| BDBUS7 | - |
C5 | FTDI (JTAG/UART, U4) / currently_not_used |
| CONF_DONE |
DET_BPR H2| C5 | 3V_D | / currently_not_used |
| DET_BPR | - | H2 | 3V_D | / currently_not_used |
| DET_RIO | - | H3 | 3V_D | / currently_not_used |
| DONE | in | N3 | PS_1V8 | FPGA Done |
| EN_3V3 | out | C10 | 3V_D | 3.3V Power Enable |
| EN_DAC1 | out | E6 | 3V_D | DAC1 Power Enable |
| EN_DAC2 | out | E8 | 3V_D | DAC2 Power Enable |
| EN_DAC3 | out | B6 | 3V_D | DAC3 Power Enable |
| EN_DAC4 | out | A6 | 3V_D | DAC4 Power Enable |
| EN_DDR | out | G13 | 3V_D | DDR Power Enable |
| EN_FPD | out | L12 | 3V_D | FPD Power Enable |
| EN_LPD | out | J13 | 3V_D | LPD Power Enable |
| EN_PSGT | out | B9 | 3V_D | PSGT Power Enable |
| ERR_OUT | - | G5 | PS_1V8 | / currently_not_used |
| ERR_STATUS | - | H6 | PS_1V8 | / currently_not_used |
| F_TCK | out | N2 | PS_1V8 | FPGA TCK |
| F_TDI | out | M1 | PS_1V8 | FPGA TDI |
| F_TDO | in | K1 | PS_1V8 | FPGA TDO |
| F_TMS | out | J1 | PS_1V8 | FPGA TMS |
| F1PWM | out | H10 | 3V_D | FAN PWM Control |
| F1SENSE | in | J9 | 3V_D | FAN Sense |
| FTDI_RST | out | E9 | 3V_D | FTDI Reset |
| GA0 | - | F8 | 3V_D |
GA0_R | Backplane address / currently_not_used |
| GA0_R | - | F9 | 3V_D | Backplane address, pullup/down enable / currently_not_used |
| GA1 | - | A2 | 3V_D | Backplane address/ currently_not_used |
| GA1_R | - | B2 | 3V_D | Backplane address, pullup/down enable / currently_not_used |
| GA2 | - | A3 | 3V_D | Backplane address/ currently_not_used |
| GA2_R | - | B3 | 3V_D |
GA3 | | Backplane address, pullup/down enable / currently_not_used |
| GA3 | - | A4 | 3V_D | Backplane address/ currently_not_used |
| GA3_R | - | B4 | 3V_D | Backplane address, pullup/down enable / currently_not_used |
| IEEE_SW_NC | - | C9 | 3V_D | / currently_not_used |
| IEEE_SW_NO | - | A11 | 3V_D | / currently_not_used |
| INIT_B | in | L2 | PS_1V8 | FPGA Init |
| JTAGEN | - | E5 | 3V_D | JTAG Enable |
| LED_FP_4 | out | M4 | 3.3V | Front panel LED |
| LP_GOOD | in | H13 | 3V_D | LP Power Good |
| M10_RST | - | A7 | 3V_D | / currently_not_used |
| M10_RX | - | C2 | 3V_D | / currently_not_used |
| M10_TX | - | B1 | 3V_D | / currently_not_used |
| MAX_ |
IO1 | IO1 / IO1 | in | N8 | 3.3V | I²C SCL in, ZynqMP Pin G18 |
| MAX_IO10 | - | M10 | 3.3V | / currently_not_used |
| MAX_ |
IO2 | IO2 / IO2 | out | N7 | 3.3V | I²C SCL out, ZynqMP Pin G19 |
| MAX_ |
IO3 | IO3 / IO3 | in | M9 | 3.3V | I²C SDA in, ZynqMP Pin K18 |
| MAX_ |
IO4 | IO4 / IO4 | out | M8 | 3.3V | I²C SDA out, ZynqMP Pin H19 |
| MAX_ |
IO5 | IO5 / IO5 | in | M12 | 3.3V | User LED in, ZynqMP Pin J17 |
| MAX_IO6 | - | M13 | 3.3V | / currently_not_used |
| MAX_IO7 | - | N9 | 3.3V | / currently_not_used |
| MAX_IO8 | - | N10 | 3.3V | / currently_not_used |
| MAX_IO9 | - | M11 | 3.3V | / currently_not_used |
| MIO22 | out | M3 | PS_1V8 | UART out |
| MIO23 | in | M2 | PS_1V8 | UART in |
| MIO24 | - | L3 | PS_1V8 | / currently_not_used |
| MIO25 | - | H5 | PS_1V8 | / currently_not_used |
| MR | out | K10 | 3V_D | Supervisor Reset out |
| N.C. | - | J5 | 3.3V | / currently_not_used |
| N.C. | - | J6 | 3.3V | / currently_not_used |
| N.C. | - | J7 | 3.3V | / currently_not_used |
| N.C. | - | J8 | 3.3V | / currently_not_used |
| N.C. | - | K5 | 3.3V | / currently_not_used |
| N.C. | - | K6 | 3.3V | / currently_not_used |
| N.C. | - | K7 | 3.3V | / currently_not_used |
| N.C. | - | K8 | 3.3V |
N.| / currently_not_used |
| N.C. | - | L4 | 3.3V | / currently_not_used |
| N.C. | - | L5 | 3.3V | / currently_not_used |
| N.C. | - | M5 | 3.3V | / currently_not_used |
| N.C. | - | M7 | 3.3V | / currently_not_used |
| N.C. | - | N4 | 3.3V | / currently_not_used |
| N.C. | - | N5 | 3.3V | / currently_not_used |
| N.C. | - | N6 | 3.3V |
N.| / currently_not_used |
| N.C. | - | L10 | 3.3V | / currently_not_used |
| N.C. | - | L11 | 3.3V | / currently_not_used |
| N.C. | - | N12 | 3.3V | / currently_not_used |
| nCONF | - | E7 | 3V_D | / currently_not_used |
| nSTATUS | - | C4 | 3V_D | / currently_not_used |
| ON_GT_L | out | J12 | 3V_D | GT_L Power Enable |
| ON_GT_R | out | K12 | 3V_D | GT_R Power Enable |
| PG_DDR | in | H8 | 3V_D | DDR Power Good |
| PG_GT_L | in | H9 | 3V_D | GT_L Power Good |
| PG_GT_R | in | G12 | 3V_D | GT_R Power Good |
| PG_PL | in | L13 | 3V_D | PL Power Good |
| PG_PSGT | in | K11 | 3V_D | PSGT Power Good |
| PLL_RST | out | K2 | PS_1V8 | PLL Chip Reset |
| PROG_B | out | J2 | PS_1V8 | FPGA PROG_B |
| PSON | - | D6 | 3V_D | / currently_not_used |
| RP_SCL | - | E1 | 3V_D |
RP_| / currently_not_used |
| RP_SDI | - | G4 | 3V_D | / currently_not_used |
| RP_SDO | - | F4 | 3V_D | / currently_not_used |
| RP_SL | - | F1 | 3V_D | / currently_not_used |
| RST | - | B5 | 3V_D | / currently_not_used |
| RST_PRST | - | A8 | 3V_D | / currently_not_used |
| RST_PRST_R | - | B10 | 3V_D | / currently_not_used |
| RST_R | - | D8 | 3V_D |
SATA_SCL | / currently_not_used |
| SATA_SCL | - | G2 | 3V_D | / currently_not_used |
| SATA_SDI | - | F6 | 3V_D | / currently_not_used |
| SATA_SDO | - | F5 | 3V_D | / currently_not_used |
| SATA_SL | - | G1 | 3V_D | / currently_not_used |
| SMB_SCL | inout | E3 | 3V_D | I²C SCL |
| SMB_SCL_R | out | E4 | 3V_D | I²C SCL Pullup Enable |
| SMB_SDA | inout | C1 | 3V_D | I²C SDA |
| SMB_SDA_R | out | D1 | 3V_D | I²C SDA Pullup Enable |
| SRST_B | out | H4 | PS_1V8 | FPGA SRST_B |
| SW4 | in | A5 | 3V_D | Dip Switch |
| SYSEN | - | D7 | 3V_D | / currently_not_used |
| USR_BTN | in | J10 | 3V_D | Front panel button |
| WAKE | - | A9 | 3V_D | / currently_not_used |
| WAKE_R | - | A10 | 3V_D |
Functional Description
Functional Description
Power
System Controller provides control and status information for main power rails. By default all power rails are ON, the user can manipulate power using I²C interface, see Memory map table.
Reset
System controller generates a reset pulse to supervisor chip U69 when front panel button S3 is pressed.
JTAG
JTAG interface from FTDI controller passes through System Controller to FPGA.
SC to HD-IO Bank Interface
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using I²C interface, see Memory map table.
Reset
System controller generates a reset pulse to supervisor chip U69 when front panel button S3 is pressed.
JTAG
JTAG interface from FTDI controller passes through System Controller to FPGA.
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| Anchor |
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| i2c_interface |
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| i2c_interface |
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I²C Interface
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| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description |
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| Page info |
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| modified-date |
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| modified-date |
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| dateFormat | yyyy-MM-dd |
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| | Page info |
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| current-version |
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| current-version |
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| prefix | v. |
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| REV03 | REV02 | | Page info |
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| modified-user |
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| - initial release
- working in processREV02 finished
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| 2018-08-15 | v.3 | REV02 | REV02 | Antti Lukats | |
| All |
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| | Page info |
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| modified-users |
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| modified-users |
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