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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI



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titleMIOs pins

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MIO PinConnected toB2BNotes
MAX_IO1...20, 22U18 (Intel MAX 10) - Bank 8J2
MAX_IO23, 25, 26U18 (Intel MAX 10) - Bank 5
J2


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titleModule power rails.

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Power Rail Name

B2B Connector

J1 Pin

B2B Connector

J2 Pin

B2B Connector

J3 Pin

Voltage LevelDirectionNotes
VIN145, 147,149, 151, 153, 155, 157, 159--5 VInput
VCCIO2K53, 54--1.2 V, 1.25 V, 1.35 V, 1.5 V
,
or 1.8
V, 2.5 V or 3.0
VInput
VADJ140,142--adjustable between 1.8 V - 3.0 VOutputVoltages according to EP53A8HQI datasheet but restricted to allowed bank voltage
VCCIO2J-29,30-1.2 V, 1.25 V, 1.35 V, 1.5 V
,
or 1.8
V, 2.5
V
or 3.0 V
Input

3.3V

-149,150-3.3 VOutput
1.8_VIO--1391.8 VOutput


Bank Voltages

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titleSoC bank voltages.

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FPGAFPGA BankVoltage LevelNotes
Intel Cyclone 10 GXBank 1C0.95 V

Bank 1D

0.95 V
Bank 2A1.8 V1.8VIO
Bank 2J1.2 V, 1.25 V, 1.35 V, 1.5 V , or 1.8 V, 2.5 V or 3.0 VVCCIO2J
Bank 2K1.2 V, 1.25 V, 1.35 V, 1.5 V , or 1.8 V, 2.5 V or 3.0 VVCCIO2K
Bank 2Ladjustable between 1.8 V - 3.0 VVoltages according to EP53A8HQI datasheet
Bank 3A1.35 VVDD_DDR
Bank 3B1.35 VVDD_DDR
Intel Max 10Bank 1A3.3 V
Bank 1B3.3 V
Bank 21.8 V1.8VIO
Bank 31.8 V1.8VIO
Bank 53.3V
Bank 63.3V
Bank 83.3V


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DateRevisionContributorDescription

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dateFormatyyyy-MM-dd
typeFlat

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  • corrected Bank Voltages for Bank 2J (VCCIO2J) and Bank 2K (VCCIO2K)
2022-03-18v.85Vitali Tsiukala
  • Added Info about Gigabit Transceivers
2021-06-07

v.84

Martin Rohrmüller
  • corrected Physical Dimension figure
  • updated to REV03

2020-01-17

v.82Martin Rohrmüller
  • updated to REV02

2019-06-14

v.80Pedram Babakhani
  • Figures updated

  • Technical specifications updated

2019-05-29

v.69Pedram Babakhani
  • initial release

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