Page History
Template Revision 2.8 - on construction
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id | Comments |
Important General Note:
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Export PDF to download, if vivado revision is changed!
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
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Figure template (note: inner scroll ignore/only only with drawIO object):
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Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, use |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Table template:
- Layout macro can be use for landscape of large tables
- Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)
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Table of contents
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Overview
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Notes :
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Design example with Linux and MGT-CLK frequency monitoring over VIO.
Refer to http://trenz.org/teb0911-info for the current online version of this manual and other available documentation.
Key Features
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- add every update file on the download
- add design changes on description
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- bugfix usb3
- add nvme driver
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- script update
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- bugfix PL Design (all MGT buffer enabled)
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- 2019.2 update
- new assembly variants
- Vitis support
- FSBL SI programming procedure update
- petalinux device tree and u-boot update
- reduced DDR speed (see Xilinx Datasheet)
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- new assembly variant
- add init.sh
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Release Notes and Know Issues
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title | Known Issues |
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- initial release
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Launch
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Note:
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Programming
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
- Select Create and open delivery binary folder
Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated
QSPI
Optional for Boot.bin on QSPI Flash and image.ub on SD.
- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
Optional "TE::pr_program_flash_binfile -swapp hello_teb0911" possible - Copy image.ub and optional misc/sd/init.sh on SD-Card
- use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Insert SD-Card
SD
- Copy image.ub, Boot.bin and misc/sd/init.sh on SD-Card.
- use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Set Boot Mode to SD-Boot.
- Depends on CPLD Firmware, see SC0911 CPLD#BootMode
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section 70156312
- Connect UART USB (same as FPGA JTAG)
- Select SD Card as Boot Mode (or QSPI - depending on step 1)
- (Optional) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
- (Optional) Connect DisplayPort Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
- (Optional) Connect Network Cable
- Power On PCB
Note: 1. ZynqMP Boot ROM loads PMU Firmware and FSBL from SD into OCM, 2. FSBL loads ATF(bl31.elf) and U-boot from SD/QSPI into DDR, 3. U-boot load Linux from SD into DDR.
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:- User Name: root
- Password: root
- You can use Linux shell now.
- I2C 0 Bus type: i2cdetect -y -r 0
- ETH0 works with udhcpc
- USB type "lsusb" or connect USB device
- PCIe type "lspci"
Vivado HW Manager
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Note:
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Control:
- User LED Control (D16, D15)
Monitoring:
- MGT CLK Measurement:
- Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz
- Default B229_CLK1: 78,8MHz, B128_CLK1: 150MHz, B129_CLK1: 175MHz, B130_CLK1: 200MHz, B228_CLK1: 125MHz, B23ß_CLK1: 100MHz
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System Design - Vivado
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Block Design
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PS Interfaces
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- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see alsoTE Board Part Files
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- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
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- XSAis exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
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- "prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
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- Run on Vivado TCL: TE::sw_run_vitis -all
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
Note: TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis
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Constrains
Basic module constrains
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
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# GT Clocks
#B128-1
set_property PACKAGE_PIN N27 [get_ports {PL_MGT_CLK_clk_p[0]}]
#B129-1
set_property PACKAGE_PIN J27 [get_ports {PL_MGT_CLK_clk_p[1]}]
#B228-1
set_property PACKAGE_PIN J8 [get_ports {PL_MGT_CLK_clk_p[2]}]
#B130-1
set_property PACKAGE_PIN E27 [get_ports {PL_MGT_CLK_clk_p[3]}]
#B229-1
set_property PACKAGE_PIN E8 [get_ports {PL_MGT_CLK_clk_p[4]}]
#B230-1
set_property PACKAGE_PIN B10 [get_ports {PL_MGT_CLK_clk_p[5]}]
## DP
set_property PACKAGE_PIN AB1 [get_ports dp_aux_data_in]
set_property PACKAGE_PIN V9 [get_ports dp_hot_plug_detect]
set_property PACKAGE_PIN AA8 [get_ports dp_aux_data_out]
set_property PACKAGE_PIN AA3 [get_ports dp_aux_data_oe_n]
set_property IOSTANDARD LVCMOS18 [get_ports dp_*]
## LED
set_property PACKAGE_PIN K14 [get_ports {LED[0]}]
set_property PACKAGE_PIN K10 [get_ports {LED[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {LED*}]
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Software Design - Vitis
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Note:
optional for Zynq / ZynqMP only
- add basic PS configuration
Activated interfaces:
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Application
SDK template in ./sw_lib/sw_apps/ available.
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zynq_fsbl_flash
TE modified 2019.2 FSBL
General:
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TE modified 2019.2 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufw
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General Example:
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TE modified 2019.2 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufw
Xilinx default PMU firmware.
hello_teb0911
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u-boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
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Changes:
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Rootfs
Start with petalinux-config -c rootfs
Changes:
- i2c-tools
Applications
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No additional software is needed.
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- Design update (bugfix)
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- script update
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- Design update (bugfix)
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- new assembly variants
- Release 2019.2
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- some notes
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2018-11-26
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- new assembly variant
- documentation style update
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2018-07-20
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