Page History

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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware

Overview

testFirmware for PCB-Master CPLD with designator U17. First CPLD Device in Chain: LCMX02-1200HC

Feature Summary

• FMC VADJ Power
• JTAG / FMC JTAG / PJTAG
• RESET/Enable Management
• LED
• RGPIO
• SD
• CAN
• USB
• DisplayPort

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Functional Description

JTAG

JTAGENB set carrier board CPLD into the chain for firmware update. For Update set DIP S4-3 to ON.

FMC JTAG is connected to XMOD2 JTAG. Set DIP S4-3 to OFF for FMC access.

PJTAG (MIO29..26) is connected to JTAF Pinheader J30.

Power

FMC VADJ is 1.8V if S5-4 is ON else 1.2V.

Reset

Main Reset is send by Slave CPLD via X0, X1 Pins.

USB PHY hold ~0,6s after Main Reset or XMOD_G Reset or inv.RGPIO Bus Pin 0 (if active).

USB HUB hold ~0,25s after Main Reset or XMOD_G Reset or inv. RGPIO Bus Pin 0 (if active). Long delay is a BUGFIX: is currently need to start Linux before Reset is disabled.

I2C Reset is Main Reset  or inv. RGPIO Bus Pin 2 (if active).

ETH Reset is  Main Reset  or inv. RGPIO Bus Pin 3 (if active).

Enable

FMC VADJ Enable is set from Slave CPLD via Saity Check (X6, X7).

SFP1 and SFP2 are always enabled.

Oscillator U45 is enabled

USB

USB Hub Device Operation Mode (USBH_MODEx Pins) are set to internal ROM configuration. Can be controlled by RGPIO Bus Pin 4 and 5.

ETH

PHY Address is 1.

Display Port

SC10 is controlled by DP_RX when SC11 is zero else high impedance state. DP_TX controlled by SC10 and DP_DE controlled by SC11.SC12 is controlled by DP_HPD.

CAN

CAN_TX soured by SC18.

SC19 sourced by CAN_RX.

CAN_S sourced by S16.

SD

SD WP is forwarded to Slave CPLD.

RGPIO

LED

*Blinking: ~1,5Hz

Appx. A: Change History

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Revision Changes

CPLD REV05 to REV06

• BUGFIX: renamed SC19 to SC17
• Connect FMC JTAG to XMOD2 JTAG
• Connect PJTAG0 (MIO29..26) to JTAG Pin Header J30
• Connect CAN to PL
• RGPIO Pin changes

CPLD REV04 to REV05

• SD WP
• XMOD LED access over PL

Older Revision (PCB REV03) to CPLD REV04

• Fix USB HUB Mode default state over RGPIO
• Invert JLED2B over RGPIO

Older Revision (PCB REV02) to CPLD REV04

• Add all functionality from older Revision (PCB REV03)

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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Appx. B: Legal Notices

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