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Table of Contents

Table of Contents

Overview

The Trenz Electronic TE0xxx-xx ... is an industrial-grade ... module ... based on Xilinx ...CR00140-01 is a CRUVI motor driver module. It supports motors with up to 4 phases up to 40V.  

Refer to http://trenz.org/tec0850-info for the current online version of this manual and other available documentation.

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Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features'  must be split into 6 main groups for modues:

  • SoC/FPGA
    • Package:
    • Speed:
    • Temperature:
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension


Key Features'  must be split into 6 main groups for carrier:

  • Modules
    • TE0808, TE807, TE0803,...
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension


  • Modules/ SoC FPGA
    • TE0808, TE807, TE0803,...
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension

Block Diagram

    • MAX10 CPLD
    • 2 phase current measurement
    • DC_LINK voltage measurement
    • 4x LEDs (2 power indicator, 2 user)
    • 2x Pushbutton
    • EEPROM
  • Interface
    • 4 phase screw terminal motor connector
    • CRUVI for control
      • 1x high speed connector 
    • 6x1 pin header for single ended sensors
    • 5x2 pin header for differential sensors
  • Power
    • screw terminal for up to 40 V DC motor supply
  • Dimension
    • 131 mm x 68.35 mm


Block Diagram

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Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


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titleTExxxx CR00140 block diagram


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Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .
Note




Scroll Title
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titleTExxxx CR00140 main components


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  1. ...
  2. ...
  3. ...

Initial Delivery State

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Notes :

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

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anchorTable_OV_IDS
titleInitial delivery state of programmable devices on the module

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Storage device name

...

Content

...

Notes

...

Quad SPI Flash

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  1. Motor connector screw terminal, J8
  2. Power supply screw terminal, J7
  3. 5x2 pinheader, base for TEI0004 JTAG programmer, J10
  4. 5x2 pinheader for sensor selection, J3
  5. 6x1 pinheader for single ended sensors, J1
  6. 5x2 pinheader for differential sensors, J2
  7. User push buttons, S1, S2
  8. User LEDs, D1, D2
  9. LED DC_Link, D4
  10. LED Power Good, D3
  11. DCDC for 15V, U1
  12. DCDC for 5V, U2
  13. half bridge drivers, U8, U9, U10, U11
  14. MAX10 CPLD, U25
  15. CRUVI high speed connector
  16. ADCs, U3, U5, U7
  17. Shunt resistors, R22, R28

Initial Delivery State

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  • Overview of Boot Mode, Reset, Enables.
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titleBoot process.
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MODE Signal State

Boot Mode

Notes :

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty


Note
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titleReset process.Initial delivery state of programmable devices on the module

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Signal

Storage device name

B2BI/O

Content

Notes

MAX10 CPLDdefault firmware REV01See firmware documentation


Signals, Interfaces and Pins

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titleGeneral PL I/O to B2B connectors information

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FPGA CPLD BankB2B ConnectorI/O Signal CountVoltage LevelNotes

...

JTAG access to the TExxxx SoM through B2B connector JMX.

...

anchorTable_SIP_JTG
titleJTAG pins connection

...

JTAG Signal

...

B2B Connector

...

3J912 x LVDS / 24 I/OsVADJ6 x RX + 6 x TX
3J94 I/OsVADJ
8J94 I/Os3.3VConstant 3.3V
1BJ95 I/Os3.3VJTAG, JTAGEN, Constant 3.3V



JTAG Interface

JTAG access to the CPLD of CR00140 is possible via the CRUVI high speed connector J9 and the pinheader J10, which is a base for TEI004 JTAG programmer. The JTAGEN signal is pulled up and available on J9 only. If JTAGEN is pulled low, the four signals can be used as user I/Os.

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titleJTAG pins connection

MIO Pins

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

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MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI
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titleMIOs pins

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MIO PinConnected toB2BNotes

...

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs
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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

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anchorTable_OBP
titleOn board peripherals

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Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

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anchorTable_OBP_SPI
titleQuad SPI interface MIOs and pins

JTAG Signal

B2B Connector

Pin headerNotes
TMSJ9-55J10-5pull up
TDIJ9-51J10-9pull up
TDOJ9-53J10-3-
TCK

J9-59

J10-1pull down
JTAGEN J9-57-high for enable JTAG port of CPLD, low for user I/Os, pull up
UART_RX-J10-7CPLD Firmware dependent, see Firmware
UART_TX-J10-8CPLD Firmware dependent, see Firmware
RST-J10-6CPLD Firmware dependent, see Firmware
+3.3V_DJ9-4, J9-9J10-4-
DGNDseveral, see CRUVIJ10-2, J10-10-


Sensor Interface

The pin headers J1, J2 and J3 constitute the sensor interface. It can be e.g. used with Encoders or Hall sensors. J3 is the selector between differential sensor interface (J2) or single ended sensors (J1). Connecting sensors is only allowed to one of the two pinheaders (J1/J2), the other one has to stay unconnected. In the figure below the jumper configuration of J3 to enable one or the other type of sensor interface is depicted.

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titleCR00140 Jumpers


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The pinheaders for connection of the sensors are further described in the following table. For differential configuration 100 Ohm parallel termination is used.

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titleSensor pins connection

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titleI2C interface MIOs and pins

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MIO PinSchematicU? PinNotes
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titleI2C Address for RTC
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MIO PinI2C AddressDesignatorNotes

...

Signal

 J1 pin (singel ended) J2 pin (differential)
ISO_ENC_A_P36
ISO_ENC_A_N-5
ISO_ENC_B_P58
ISO_ENC_B_N-7
ISO_ENC_I_P210
ISO_ENC_I_N-9
DGND43
+5.0V_D1, 62


Motor Interface

CR00140 has a motor interface, where up to 4 phases can be driven.

Warning

Check carefully correct connection of the phases of the motor, according to the motor and the implemented driving algorithm.


Scroll Title
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titleI2C EEPROM interface MIOs and pinsMotor pins connection

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MIO PinSchematicU?? PinNotes
Scroll Title
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titleI2C address for EEPROM
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MIO PinI2C AddressDesignatorNotes

LEDs

Signal

 J8 pin lableNote
Motor_AACurrent measurement via R22 and ADC U3
Motor_BBCurrent measurement via R28 and ADC U5
Motor_CC-
Motor_DD-


CRUVI

For the connection to a control unit, the CRUVI interface is implemented. One high speed connector J9 is assembled. The connectors are further described in section B2B Connectors. The connection of the signals and the voltage levels is described in the CPLD section.

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titleOn-board LEDsCRUVI signals

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Designator

Signal

ColorConnected toActive LevelNote

DDR3 SDRAM

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Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

  • Part number: 
  • Supply voltage:
  • Speed: 
  • NOR Flash
  • Temperature: 

Ethernet

...

anchorTable_OBP_ETH
titleEthernet PHY to Zynq SoC connections

...

CAN Transceiver

...

anchorTable_OBP_CAN
titleCAN Tranciever interface MIOs

...

anchorTable_OBP_CLK
titleOsillators

...

Power and Power-On Sequence

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit
Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Power Supply

Power supply with minimum current capability of xx A for system startup is recommended.

Power Consumption

...

anchorTable_PWR_PC
titlePower Consumption

...

* TBD - To Be Determined

Power Distribution Dependencies

...

anchorFigure_PWR_PD
titlePower Distribution
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 Connector - Pin
DGND

J9-12, J9-18, J9-24, J9-30, J9-42, J9-48, J9-54, J9-13, J9-19, J9-25, J9-31, J9-37, J9-43, J9-49

+3.3V_D

J9-4, J9-9
+5.0V_DJ9-60
VADJJ9-36
A0_PJ9-14
A0_NJ9-16
A1_P

J9-20

A1_NJ9-22
A2_PJ9-26
A2_NJ9-28
A3_PJ9-32
A3_NJ9-34
A4_PJ9-38
A4_NJ9-40
A5_PJ9-44
A5_NJ9-46
B0_PJ9-15
B0_NJ9-17
B1_PJ9-21
B1_NJ9-23
B2_PJ9-27
B2_NJ9-29
B3_PJ9-33
B3_NJ9-35
B4_PJ9-39
B4_NJ9-41
B5_PJ9-45
B5_NJ9-47
HSIOJ9-2
HSOJ9-6
RESETJ9-8
HSIJ9-10

TDI

J9-51
TDOJ9-53
TMSJ9-55
JTAGENJ9-57
TCKJ9-59
SMB_ALERTJ9-3
SMB_SDAJ9-5
SMB_SCLJ9-7
REFCLKJ9-11


On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

CPLD

A Intel/Altera MAX10 FPGA 10M08SAU169C8G (U25) is used as system controller. Table below lists the SC CPLD I/O signals and pins.

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titleOn-board LEDs

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Signal nameSC CPLD PinCPLD BankConnected toFunctionNotes
A0_PJ83J9-14CPLD firmware dependentSee CPLD Firmware
A0_NK83J9-16CPLD firmware dependentSee CPLD Firmware
A1_PM133

J9-20

CPLD firmware dependentSee CPLD Firmware
A1_NM123J9-22CPLD firmware dependentSee CPLD Firmware
A2_PM93J9-26CPLD firmware dependentSee CPLD Firmware
A2_NM83J9-28CPLD firmware dependentSee CPLD Firmware
A3_PN83J9-32CPLD firmware dependentSee CPLD Firmware
A3_NN73J9-34CPLD firmware dependentSee CPLD Firmware
A4_PM73J9-38CPLD firmware dependentSee CPLD Firmware
A4_NN63J9-40CPLD firmware dependentSee CPLD Firmware
A5_PK53J9-44CPLD firmware dependentSee CPLD Firmware
A5_NJ53J9-46CPLD firmware dependentSee CPLD Firmware
B0_PN53J9-15CPLD firmware dependentSee CPLD Firmware
B0_NN43J9-17CPLD firmware dependentSee CPLD Firmware
B1_PJ73J9-21CPLD firmware dependentSee CPLD Firmware
B1_NK73J9-23CPLD firmware dependentSee CPLD Firmware
B2_PL113J9-27CPLD firmware dependentSee CPLD Firmware
B2_NM113J9-29CPLD firmware dependentSee CPLD Firmware
B3_PL103J9-33CPLD firmware dependentSee CPLD Firmware
B3_NM103J9-35CPLD firmware dependentSee CPLD Firmware
B4_PJ63J9-398CPLD firmware dependentSee CPLD Firmware
B4_NK63J9-41CPLD firmware dependentSee CPLD Firmware
B5_PL53J9-45CPLD firmware dependentSee CPLD Firmware
B5_NL43J9-47CPLD firmware dependentSee CPLD Firmware
HSION93J9-2CPLD firmware dependentSee CPLD Firmware
HSON103J9-6CPLD firmware dependentSee CPLD Firmware
RESETM53J9-8CPLD firmware dependentSee CPLD Firmware
HSIN123J9-10CPLD firmware dependentSee CPLD Firmware

TDI

F51BJ9-51, J10-9JTAG / user IO CPLD firmware dependentSee CPLD Firmware
TDOF61BJ9-53, J10-3JTAG / user IO CPLD firmware dependentSee CPLD Firmware
TMSG11BJ9-55, J10-5JTAG / user IO CPLD firmware dependentSee CPLD Firmware
JTAGENE51BJ9-57JTAG enable CPLD firmware dependentSee CPLD Firmware
TCKG21BJ9-59, J10-1JTAG / user IO CPLD firmware dependentSee CPLD Firmware
SMB_ALERTK22J9-3CPLD firmware dependentSee CPLD Firmware
SMB_SDAH52J9-5CPLD firmware dependentSee CPLD Firmware
SMB_SCLH42J9-7CPLD firmware dependentSee CPLD Firmware
REFCLKM22J9-11CPLD firmware dependentSee CPLD Firmware
BUTTON1C108S2CPLD firmware dependentactiv low, See CPLD Firmware 
BUTTON2B108S1CPLD firmware dependentactiv low, See CPLD Firmware 
ENC_AA108U13-13Sensor input channel A-
ENC_BA98U13-12Sensor input channel B-
ENC_IA118U13-14Sensor input channel I-
LED0D68D2CPLD firmware dependentSee CPLD Firmware
LED1B28D1CPLD firmware dependentSee CPLD Firmware
M_BEMF_B_DB58U15-13Back EMF signal phase B-
M_BEMF_C_DA58U15-12Back EMF signal phase C-
M_BEMF_A_DA48

U15-14

Back EMF signal phase A-
M_PWM_AHF11AU8-2Phase A half bridge high (DC_LINK) side driver signal-
M_PWM_ALE31AU8-3Phase A half bridge low (PGND) side driver signal-
M_PWM_BHE11AU9-2Phase B half bridge high (DC_LINK)side driver signal-
M_PWM_BLD11AU9-3Phase B half bridge low (PGND) side driver signal-
M_PWM_CHE41AU10-2Phase C half bridge high (DC_LINK)side driver signal-
M_PWM_CLC11AU10-3Phase C half bridge low (PGND) side driver signal-
M_PWM_DHC21AU11-2Phase D half bridge high (DC_LINK) side driver signal-
M_PWM_DLB11AU11-3Phase D half bridge low (PGND) side driver signal-
SD_IAE68U3-6Current measurement phase A33 Ohm series Resistor
SCLK_AB38U3-7, U5-7Clock for ADC for current measurement phase A and B(5-20 MHz)
SD_VB48U7-6Voltage measurement DC_LINK33 Ohm series Resistor
SD_IBA28U5-6Current measurement phase B33 Ohm series Resistor
SCLK_V_AA38U7-7Clock for ADC for voltage measurement DC_LINK(5-20 MHz)
M_DISABLE_D_DJ12U11-5Halfe bridge disable phase Ddisabled when high, pull up connected
M_DISABLE_A_DM12U8-5Halfe bridge disable phase Adisabled when high, pull up connected 
M_DISABLE_B_DL22U9-5Halfe bridge disable phase Bdisabled when high, pull up connected 
M_DISABLE_C_DK12U10-5Halfe bridge disable phase Cdisabled when high, pull up connected 
REFCLKM22J9-11CPLD firmware dependent-
RSTM32J10-6CPLD firmware dependent-
UART_RXN22J10-7CPLD firmware dependent-
UART_TXN32J10-8CPLD firmware dependent-
CLK_25MHZH62U26-3Clock input for accurate 25 Mhz clk.-


CPLD Bank Voltages

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titleCPLD bank voltages.

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Bank          

Schematic Name

Voltage

Notes
1A+3.3V_D3.3VProvided via CRUVI
1B

+3.3V_D

3.3VProvided via CRUVI
2+3.3V_D3.3VProvided via CRUVI
3VADJ1.8V, 2.5V, 3.3VProvided via CRUVI, supported voltage levels are determined by the CPLD Firmware, and the connected base/controller.
8+3.3V_D3.3V

Provided via CRUVI


LEDs

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titleOn-board LEDs

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DesignatorColorConnected toSignal nameActive LevelNote
D1greenU25-B2LED1highUser LED, CPLD Firmware dependent, see Firmware description.
D2greenU25-D6LED0highUser LED, CPLD Firmware dependent, see Firmware description.
D3greenU1-A3, U2-B1PGOODhighON when +15.0V_M and +5.0V_M regulator indicated power good. Connected via transistor T1.
D4greenDC_LINK-lowON when DC_LINK above 11.7V. Connected via comparator U14D to DC_LINK


Buttons

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titleOn-board LEDs

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DesignatorConnected toSignal nameActive LevelNote
S1U25-B10BUTTON2lowUser button, CPLD Firmware dependent, see Firmware description.
S2U25-C10BUTTON1lowUser button, CPLD Firmware dependent, see Firmware description.


ADCs

There are three isolating AD7403-8 ADCs for continous measurement oft phase A current (U3), phase B current (U5) and the DC_LINK voltage (U7) on board. The currents are measured through the shunt resistors R22, R28 for phase A and B respectively. The ADC clock is routed to the CPLD. For Currents the clock has the signal lable SCLK_A and for the voltage SCLK_V_A. The data signals are also routed to the CPLD. See CPLD Firmware for further description.

BEMF

Back EMF zero crossing signals for sensor-less motor control are implemented for Phase A, B and C. They are routed via a triple channel Digital isolator (U15) to the CPLD. See CPLD Firmware for further description.

Half bridge drivers

Four ADuM7223 isolated half bridge drivers (U8, U9, U10, U11) are used for driving the four phases.

DCDCs

On the Motor side are two DCDCs on board. LTM8053 (U1) is utilized for the generation of the 15V transistor control voltage from VIN and can be measured on Testpoint TP1. A LTM8074 DCDC (U2) generates 5V from VIN for miscellaneous signals on the motor side of the PCB and can be measured on TP2.

Two isolated DCDCs ADUM5028 (U4, U6) are used for the generation two seperate clean 5V for the supply of the current measurement ADCs U3 and U5.

Power and Power-On Sequence

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


EEPROM

The 2K Microchip 24AA02E48 EEPROM with pre-programmed unique 48bit address is connected to the CRUVI HS (Signals: SMB_SDA, SMB_SCL) connector and can e.g. be used for identifiction purposes.

Power Supply

The motor driving stage is supplied via connector J7 with maximum of 40V DC. Polarity of the powersupply is noted on the PCB.  

Warning

Check powersupply for correct polarity. Inversion of polarity will damage the module. At least Transistor T11 may be harmed. Furthermore make sure that under any circumstances the absolute maximum voltage does not exceed 42V.

Power Consumption

The power consumption on the motor stage side (J7) is dominated by the connected motor and the corresponding driving algorithm. The idle consumption is given below.

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Power Input PinTypical CurrentNote
VIN~ 47mA@24V (J7), no motor connected, no PWM signal driven.


Power Distribution Dependencies

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titlePower Distribution


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Power-On Sequence

There is no power on sequence which has to be maintained.

Power Rails

Power-On Sequence

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anchorFigure_PWR_PS
titlePower Sequency
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Voltage Monitor Circuit

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anchorFigure_PWR_VMC
titleVoltage Monitor Circuit
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Power Rails

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anchorTable_PWR_PR
titleModule power rails.

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B2B Connector

JM1 Pin

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B2B Connector

JM2 Pin

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B2B Connector

JM3 Pin

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Bank Voltages


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titleZynq SoC bank voltagesModule power rails.

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Bank          

Schematic Name

Voltage

Notes
Power Rail Name

B2B Connectors


DirectionNotes

+3.3V_D

 J9-4, J9-9In-
+5.0V_DJ9-60In-
VADJJ9-36In-
VINJ7Inisolated


Board to Board Connectors

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  • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors

    Include Page
    PD:6 x 6 SoM LSHM B2B ConnectorsPD:
    6 x 6 SoM LSHM B2B Connectors

? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.

3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)

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CRUVI B2B Connectors
CRUVI B2B Connectors

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Technical Specifications

Absolute Maximum Ratings

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titlePS absolute maximum ratings

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V
SymbolsDescriptionMinMaxUnit
VINMotor supply voltage042V

+3.3V_D

digital part 3.3V supply voltage-0.33.9V
+5.0V_Ddigital part 5V supply voltage-0.36.0V
VVADJVIO Bank Voltage-0.33.9VV


Recommended Operating Conditions

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anchorTable_TS_ROC
titleRecommended operating conditions.

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ParameterMinMaxUnitsReference Document
VIN
VSee ???? datasheets.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.°CSee Xilinx ???? datasheet.
2240VLTM8053 datasheet

+3.3V_D

3.1353.465VMAX10 datasheet
+5.0V_D4.755.25VSN65LBC173AD datasheet

VADJ (3.3V operation)

VADJ (2.5V operation)

VADJ (1.8V operation)

3.135

2.375

1.71

3.465

2.625

1.89

VMAX10 datasheet
T-40105°CAD7403-8 (junction)
T (ambient)-4085°CSN65LBC173AD datasheet
°CSee Xilinx ???? datasheet.