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- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM"
Template Change history: Date | Version | Changes | Author |
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2024-08-07 | 4.3 | - add article name encoding table link to "Currently offert Variants" chapter
- removed empty lines
| JH/ED |
| 4.2.1 | Error correction in tables "Power Rails" and "Configuration and System Control Signals" | KJ |
| 4.2 | | ED |
| 4.1 | | ED |
| 4.0 | - Rework for smaller TRM which can be generated faster
- Reduce Signal Interfaces Pin
- Reduce On Board Periphery
- Reduce Power
- Move Configuration Signals from Overview to own section
| JH |
| 3.12 | - Version History
- changed from list to table
- all
- changed title-alignment for tables from left to center
| ma |
| 3.11 | - update "Recommended Operating Conditions" section
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| 3.1 | - New general notes for temperature range to "Recommended Operating Conditions"
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| 3.02 | - add again fix table of content with workaround to use it for pdf and wiki
- Export Link for key features examples
- Notes for different Types (with and without Main FPGA)
- Export Link for Signals, Interfaces and Pins examples
- Notes for different Types (Modul, Modul Hybrid, Evalboard, Carrier)
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| 3.01 | - remove fix table of content and page layout ( split page layout make trouble with pdf export)
- changed and add note to signal and interfaces, to on board periphery section
- ...(not finished)
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| 3.00 | - → separation of Carrier/Module and evaluation kit TRM
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| 2.15 | - add excerpt macro to key features
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| 2.14 | - add fix table of content
- add table size as macro
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Important General Note:
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----------------------------------------------------------------------- |
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Note for Download Link of the Scroll ignore macro: |
OverviewOverview
The Trenz Electronic TE0820 is an industrial/extended 4 x 5 SoM integrating an AMD Zynq UltraScale+ MPSoC, DDR4 SDRAM, eMMC memory, flash memory for configuration and data storage, as well as powerful switching power supplies for all required voltages. The module is equipped with a Lattice Mach XO2 CPLD for system controlling. Three high-speed connectors provide a large number of inputs and outputs. Additionally, the module provides Gigabit Ethernet and USB 2.0 transceivers.
The highly integrated modules are smaller than a credit card and are offered in several variants at an affordable price-performance ratio. Modules with a 4 x 5 cm form factor are completely mechanically and largely electrically compatible with each other.
All components cover at least the industrial temperature range. The temperature range in which the module can be used depends on the customer design and the selected cooling. Please contact us for special solutions.
Refer to http://trenz.org/te0820-info for the current online version of this manual and other available documentation.
Key Features
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- SoC
- Device: ZU1 / ZU2 / ZU3 / ZU4 / ZU5 1)
- Engine: CG / EG / EV 1)
- Speedgrade: -1 / -1L / -2 / -2L / 3 1)
- Temperature Range: Extended / Industrial 1)
- Package: SFVC784
- RAM/Storage
- 2 GByte DDR4 SDRAM 2)
- 2 x 64 MByte Serial Flash 3)
- 8 GByte eMMC 3)
- EEPROM with MAC address
- On Board
- Lattice MachXO2 CPLD
- Programmable Clock Generator
- Hi-speed USB2 ULPI Transceiver
- 10/100/1000 Mbps Ethernet Transceiver
- 4x LEDS
- Interface
- 3 x B2B Connector (LSHM)
- up to 132 PL HP IO
- up to PS 14 MIO
- 4 PS GTR
- ETH (MDI) or SGMII
- USB
- SDIO
- CFG, JTAG
- Power
- 3.3 V power supply via B2B Connector needed 4).
- Dimension
- Notes
1) Please, take care of the possible assembly options. Furthermore, check whether the power supply is powerful enough for your FPGA design. 2) Up to 4 GByte are possible with a maximum bandwidth of 2400 MBit/s. 3) Please, take care of the possible assembly options. 4) Higher input voltage may be possible.
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Block Diagram
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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.
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Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name. Example: TE0812 Block Diagram |
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All created DrawIOs should be named according to the Module name: Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD |
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title | TE0820 -03 block diagram |
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![](/download/attachments/33492224/TE0820%20BD%20Block%20Diagram.png?version=4&modificationDate=1723008700868&api=v2)
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Main Components
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Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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anchor | Figure_OV_MC |
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title-alignment | center |
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title | TE0820 main components |
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![](/download/attachments/33492224/TE0820%20MC%20main%20components%20.png?version=3&modificationDate=1723006075674&api=v2)
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- AMD Zynq UltraScale+ MPSoC, U1
- QSPI flash memory, U7, U17
- DDR4 SDRAM, U2, U3
- eMMC memory, U6
- EEPROM, U25
- Ethernet transceiver, U8
- USB 2.0 ULPItransceiver, U18
- B2B Connector, JM1, JM2, JM3
- Lattice Semiconductor MachXO2 System Controller CPLD, U21
- Clock generator, U10
- Oscillator, U11, U14, U32
- Done LED, D1
- User LED, D2
- Error Out LED, D3
- Error Status LED, D4
Initial Delivery State
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Note |
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Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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title-alignment | center |
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title | Initial delivery state of programmable devices on the module |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Storage device name | Content | Notes |
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Quad SPI Flash | not programmed |
| eMMC | not programmed |
| DDR4 SDRAM | not programmed |
| Programmable Clock Generator | not programmed |
| EEPROM | not programmed besides factory programmed MAC address |
| System Controller CPLD | programmed | TE0820 CPLD |
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Signals, Interfaces and Pins
Connectors
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anchor | Table_SIP_C |
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title-alignment | center |
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title | Board Connectors |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Connector Type | Designator | Interface | IO CNT | Notes |
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B2B | JM1 | ETH - MDI | ETH |
| B2B | JM1 | HP | 48 SE / 24 DIFF |
| B2B | JM1 | MIO | 8 x GPIO |
| B2B | JM1 | SDIO | SDIO or 6 x MIO |
| B2B | JM2 | HP | 68 SE / 33 DIFF |
| B2B | JM2 | CFG | JTAG |
| B2B | JM3 | ETH | SGMII |
| B2B | JM3 | MGT PS | 4 x MGT (RX/TX) |
| B2B | JM3 | MGT PS | MGT CLK |
| B2B | JM3 | CLK | DIFF CLK |
| B2B | JM3 | HP | 16 SE / 8 DIFF |
| B2B | JM3 | USB | USB |
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Test Points
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delete the Test Point section. Example: Test Point | Signal | Notes1) |
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TP1 | PWR_PL_OK |
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1) Direction: - IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
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anchor | Table_SIP_TPs |
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title-alignment | center |
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title | Test Points Information |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Test Point | Signal | Notes1) |
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TP1 | PS_LP0V85 |
| TP2 | DDR_2V5 |
| TP3 | PS_AVCC |
| TP4 | DDR_1V2 |
| TP5 | PS_AVTT |
| TP6 | VTT |
| TP7 | PS_FP0V85 |
| TP8 | VREFA |
| TP9 | DDR4-TEN | pulled-down to GND | TP10 | PS_PLL |
| TP11 | PL_VCCINT |
| TP12 | PG_ALL | pulled-up to 3.3VIN | TP15 | PL_VCCINT_IO |
| TP16 | PL_VCU |
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1) Direction: - IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
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On-board Peripherals
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection Example: Chip/Interface | Designator | Connected To | Notes |
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ETH PHY | U10 | | Gigabit ETH PHY |
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title-alignment | center |
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title | On board peripherals |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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cellHighlighting | true |
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Chip/Interface | Designator | Connected To | Notes |
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QSPI Flash | U7, U17 | SoC - PS |
| EEPROM | U25 | SoC - PS |
| DDR4 SDRAM | U2, U3 | SoC - PS |
| GigaBit Ethernet | U8 | SoC - PS, B2B |
| USB2.0 Transceiver | U18 | SoC - PS, B2B |
| eMMC Memory | U6 | SoC - PS |
| Oscillator | U32 | SoC - PS |
| Oscillator | U14 | USB PHY |
| Oscillator | U11 | Clock Generator, ETH PHY |
| Programmable Clock Generator | U10 | SoC - PS, B2B |
| CPLD | U21 | SoC - PS, B2B |
| LED | D1 | SoC - PS | Red, Done LED (see U+ Zynq TRM) | LED | D2 | CPLD | Green, Status LED (see TE0820 CPLD) | LED | D3 | SoC - PS | Red, PS Error LED (see U+ Zynq TRM) | LED | D4 | SoC - PS | Green, PS Error Status LED (see U+ Zynq TRM) |
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Configuration and System Control Signals
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- Overview all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
- In case it's connected to CPLD always link to CPLD description and add not from the current implementation here(in case it's available)
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anchor | Table_OV_CNTRL |
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title-alignment | center |
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title | Controller signal. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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1) Direction: - IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
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Power and Power-On Sequence
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Enter the default value for power supply and startup of the module here. - Order of power provided Voltages and Reset/Enable signals
Link to Schematics, for power images or more details |
Power Rails
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List of all power rails which are accessible by the customer - Main Power Rails and Variable Bank Power
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anchor | Table_PWR_PR |
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title-alignment | center |
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title | Module power rails. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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Power Rail Name/ Schematic Name | Connector.Pin | Direction1) | Notes |
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VIN | JM1.1 / JM1.3 / JM1.5 / JM2.2 / JM2.4 / JM2.6 / JM2.8 | IN | Supply voltage from carrier board | 3.3VIN | JM1.13 / JM1.15 | IN | Supply voltage from carrier board | 3.3VIN | JM2.91 | OUT | JTAG reference voltage | +3.3V | JM2.10 / JM2.12 | OUT | Internal +3.3 V voltage level | +1.8V | JM1.39 | OUT | Internal +1.8V voltage level | VCCO_64 | JM2.7 / JM2.9 | IN | HP Bank voltage (max. +1.9 V) | VCCO_65 | JM2.5 | IN | HP Bank voltage (max. +1.9 V) | VCCO_66 | JM1.9 / JM1.11 | IN | HP Bank voltage (max. +1.9 V) | PSBATT | JM1.79 | IN | PS battery supply voltage |
1) Direction: - IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
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Recommended Power up Sequencing
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List baseboard design hints for final baseboard development. |
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anchor | Table_BB_DH |
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title-alignment | center |
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title | Baseboard Design Hints |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Sequence | Net name | Recommended Voltage Range | Pull-up/down | Description | Notes |
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0 | - | - | - | Configuration signal setup. | See Configuration and System Control Signals. | 1 1) | 3.3VIN | 3.3 V (± 5 %) | - | Management and SoC power supply. | Main module power supply for management and SoC. 1 A recommended. Power consumption depends mainly on design and cooling solution. | 2 1) | VIN | 3.3 V (± 5 %) 2) OR 5.0 V (± 5 %) 2) | - | Main module power supply. | Main module power supply for management and SoC. 3 A to 7 A recommended. Power consumption depends mainly on design and cooling solution. | 3 | 1.8V | - | - | 1.8 V on-module power supply. |
| 4 | 3.3V | - | - | 3.3 V on-module power supply. |
| 5 | VCCO_64 / VCCO_65 / VCCO_66 | 2) | - | Module bank voltages. | Enable bank voltages after 1.8 V and/or 3.3 V are available on carrier. |
1) In cases where VIN = 3.3VIN = 3.3 V, both voltages can be enabled together. 2) A higher or lower input voltage may be possible. 2) See DS925 for additional information. |
Board to Board Connectors
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- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
Include Page |
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| 6 x 6 SoM LSHM B2B Connectors |
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| 6 x 6 SoM LSHM B2B Connectors |
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Include Page |
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| 4 x 5 SoM LSHM B2B Connectors |
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| 4 x 5 SoM LSHM B2B Connectors |
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Technical Specifications
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List of all power rails which are accessible by the customer - Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)
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Absolute Maximum Ratings *)
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anchor | Table_TS_AMR |
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title-alignment | center |
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title | Absolute maximum ratings |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Rail Name/ Schematic Name | Description | Min | Max | Unit |
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VIN | Supply voltage | -0.3 | 7 | V | 3.3VIN | Supply voltage | -0.3 | 3.75 | V | VCCO_64 | I/O bank voltage | -0.5 | 2.0 | V | VCCO_65 | I/O bank voltage | -0.5 | 2.0 | V | VCCO_66 | I/O bank voltage | -0.5 | 2.0 | V | PSBATT | RTC / BBRAM | -0.5 | 2.0 | V |
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*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
or any other conditions beyond those indicated under Recommended Operating ConditionConditions. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
This TRM is generic for all variants. Temperature range can be differ depending on the assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
- Variants of modules are described here: Article Number Information
- Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
- Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
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anchor | Table_TS_ROC |
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title-alignment | center |
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title | Recommended operating conditions. |
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repeatTableHeaders | default |
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cellHighlighting | true |
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Parameter | Min | Max | Units | Reference Document |
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VIN 1) | 3.135 OR 4.75 | 3.465 OR 5.25 | V
V |
| 3.3VIN | 3.135 | 3.465 | V |
| VCCO_64 | 0.950 | 1.900 | V | See FPGA datasheet. | VCCO_65 | 0.950 | 1.900 | V | See FPGA datasheet. | VCCO_66 | 0.950 | 1.900 | V | See FPGA datasheet. | PSBATT | 1.200 | 1.500 | V | See FPGA datasheet. |
1) Higher values may possible. For more information consult schematic and according datasheets. |
Physical Dimensions
PCB thickness: 1.66 mm (± 10 %).
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anchor | Figure_TS_PD |
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title-alignment | center |
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title | Physical Dimension |
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diagramName | TE0820_TS_PD PD |
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diagramWidth | 641 |
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revision | 3 |
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scroll-html | true |
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| ![](/download/attachments/33492224/%20TE0820_TS_PD%20PD.png?version=3&modificationDate=1723006802037&api=v2)
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Currently Offered Variants
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anchor | Table_VCP_SO |
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title-alignment | center |
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title | Trenz Electronic Shop Overview |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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*) Module article name encoding table: Zynq Ultrascale+ based modules (MPSoC, RFSoC) |
Revision History
Hardware Revision History
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anchor | Figure_6 |
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title-alignment | center |
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title | Figure 6: Module hardware revision number |
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diagramName | TE0820_HV_HRH HRH |
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simpleViewer | false |
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tbstyle | top |
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diagramWidth | 260 |
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revision | 2 |
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| ![](/download/attachments/33492224/TE0820_HV_HRH%20HRH.png?version=2&modificationDate=1723007050451&api=v2)
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anchor | Table_RH_HRH |
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title-alignment | center |
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title | Hardware Revision History |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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cellHighlighting | true |
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Date | Revision | Changes | Documentation Link |
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2022-06-22 | 05 | - Changed EOL ferrite beads L1..5,L7,L9..12.
- Changed EOL DCDC U5 (EN6363QI -> MPM3860GQW-Z).
- Changed EOL load switch U28 (TPS27082LDDCR -> MP5077GG-Z ).
- Added additional decoupling capacitors and changed caps 4.7uF to 10uF (AMD doc UG583 v1.23).
- Added pull-down and testpoint to TEN DDR4 signal.
- Changed EOL transistor T1 (AO7800 -> BSD840NH6327XTSA1).
- Added voltage detector U30 (BD39040MUF-CE2).
- Changed EOL eMMC U6 (MTFC4GACAJCN-4M -> SDINBDG4-8G-XI2).
- Changed EOL MEMS U14 (SiT8008AI-73-XXS-52.000000E -> SiT8008BI-73-XXS-52.000000E).
- Added signal PG_ALL (U30) to CPLD (pin5).
- Added option (depends assembly variants, for all assembly variants R128 set as populated, instead special inquiry) signal POR_B through R128, T2 to CPLD (pin27).
- Added option (depends assembly variants, for all assembly variants R95 set as DNP, instead special inquiry) signal EN1 through R95 to DCDC U5.
- Added option (depends assembly variants, for all assembly variants U29 and R129 set as populated, instead special inquiry) signal PHY_LED1 through level translator U29 to FPGA (U1.K7).
- Added resistors R130 & R131 (select Power-on delay override, for all assembly variants R130 set as DNP -> Standard PL Power-on delay time).
- Added diode D5.
- Added Power Diagram sheet.
- LIB components update.
| TE0820-05 | 2020-08-14 | 04 | - Fixed DDR4 connection (BG1), support B-die DDR4 Industrial grade chips.
- Added R93, changed value C62, change obsolete U28.
- Added R89 (10R).
- Added additional caps 4.7uF to PS_AVTT/PS_AVCC (AMD doc UG583).
- Changed R51 20k ->10K (PS_AVCC = 0.85V, AMD doc DS925 v1.17).
- Fixed DDR4 connection (Alert).
- Added 3.3V signal to CPLD.
- Added testpoints.
- LIB components update.
| TE0820-04 | 2019-01-02 | 03 | - Fixed VCU connection: add additional DCDC (0.9V).
- LIB components update.
- Change package 1K resistors (0402 -> 0201).
- Added LEDs (1x user LED, 1x LED for ERR_STATUS, 1xLED for ERR_OUT).
- Change obsolete 2xSPI Flash (256MBit) -> 2xSPI Flash (512MBit).
- Added additional DCDCs (PL_VCCINT_IO, PS_FP0V85).
- Changed DCDC (U5) 6A (optional 4A).
| TE0820-03 | 2017-08-17 | 02 | - Added MAC EEPROM (slave address).
- LIB components update.
- Fixed SD Card connection.
- Fixed sense connection from DCDC.
- Made correct power connection for VCU (removed DCDC, added resistors and caps like as AMD recommended).
- Added resistors for variants (ZU+ with/without VCU).
- Added termination resistors (240R) to VRP pins fro all HP-banks.
| TE0820-02 | 2016-12-23 | 01 | Prototype | TE0820-01 |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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dateFormat | yyyy-MM-dd |
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| - Updated to new TRM style
- Updated for REV05
| | | | | 2021-12-17 | v.99 | Vadim Yunitski | - Corrected 'Bank voltages' table
| 2021-07-14 | v.98 | John Hartfiel | | 2021-07-05 | v.97 | John Hartfiel | | 2020-09-18 | v.95 | Pedram Babakhani | - Update to REV04
- Update the TRM format
- Technical Information update
| 2020-03-16 | v.87 | John Hartfiel | - Corrected PLL section
- Corrected Designators USB, ETH PHY, CLK section
| 2020-02-03 | v.85 | Martin Rohrmüller | - Corrected #MIOs for QSPI and USB in block diagram
| 2019-11-28 | v.81 | Martin Rohrmüller | - typo and designator in section USB interface corrected
| 2019-10-30 | v.80 | John Hartfiel | | 2019-09-17 | v79 | Martin Rohrmüller | - Updated according to PCN-20190110: eMMC, QSPI-Flash
| | v.78 | Martin Rohrmüller | - Corrected PJTAG Mio Pin29 in table 8
| 2019-05-08 | v.77 | John Hartfiel | - Corrected EEPROM I2C Address
- Correction USB PHY connection
| | v.74 | John Hartfiel | | | v.73 | John Hartfiel | - typo correction
- update CPLD section
- add LEDs to component list
- add 3D picture of REV03 instead of REV01 picture
| | v.69 | Ali Naseri | | | v.61 | John Hartfiel | - Rework chapter currently available products
- add PJTAG note to MIOtable
| 2018-03-12 | v.54 |
| - Correction Power Rail Section
| 2017-11-20 | v.51 | John Hartfiel | - Correction Default MIO Configuration Table
| 2017-11-10 | v.50 | John Hartfiel | - Replace B2B connector section
| 2017-10-18 | v.49 | John Hartfiel | | 2017-09-25 | v.48 | John Hartfiel | - Correction in the "Board to Board (B2B) I/Os" section
- Update in the "Variants Currently In Production" section
| 2017-09-18 | v.47 | John Hartfiel | | 2017-08-30 | v.46 | Jan Kumann | | | | John Hartfiel | - Correction in the "Key Features" section.
| 2017-08-21 | v.34 | John Hartfiel | - "Initial delivery state" section updated.
| 2017-08-21 | v.33 | Jan Kumann | - HW revision 02 block diagram added.
- Power distribution and power-on sequence diagram added.
- System Controller CPLD and DDR4 SDRAM sections added.
- TRM update to the template revision 1.6
- Weight section removed.
- Few minor corrections.
| | | John Hartfiel | - Style changes
- Updated "Boot Mode", "HW Revision History", "Variants Currently In Production" sections
- Correction of MIO SD Pin-out, System Controller chapter
- Update and new sub-sections on "On Board Peripherals and Interfaces" sections
| 2017-08-07 | v.5 | Jan Kumann | | -- | all | Page info |
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Disclaimer
Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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