Page History

Custom_table_size_100

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Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM"

Template Change history:

Date	Version	Changes	Author
2024-08-07	4.3	add article name encoding table link to "Currently offert Variants" chapter removed empty lines	JH/ED
	4.2.1	Error correction in tables "Power Rails" and "Configuration and System Control Signals"	KJ
	4.2	Changes Xilinx to AMD	ED
	4.1	Minor changes Notes Tables	ED
	4.0	Rework for smaller TRM which can be generated faster Reduce Signal Interfaces Pin Reduce On Board Periphery Reduce Power Move Configuration Signals from Overview to own section	JH
	3.12	Version History changed from list to table all changed title-alignment for tables from left to center	ma
	3.11	update "Recommended Operating Conditions" section
	3.1	New general notes for temperature range to "Recommended Operating Conditions"
	3.02	add again fix table of content with workaround to use it for pdf and wiki Export Link for key features examples Notes for different Types (with and without Main FPGA) Export Link for Signals, Interfaces and Pins examples Notes for different Types (Modul, Modul Hybrid, Evalboard, Carrier)
	3.01	remove fix table of content and page layout ( split page layout make trouble with pdf export) changed and add note to signal and interfaces, to on board periphery section ...(not finished)
	3.00	→ separation of Carrier/Module and evaluation kit TRM
	2.15	add excerpt macro to key features
	2.14	add fix table of content add table size as macro

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Important General Note:

If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template:

Scroll Title

anchor	Figure_anchorname
title-alignment	center
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Table template:
- Layout macro can be use for landscape of large tables

Scroll Title

anchor	Table_tablename
title-alignment	center
title	Text

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Example	Comment
1	2

The anchors of the Scroll Title should be named consistent across TRMs. A incomplete list of examples is given below
- <type>_<main section>_<name>
  - type: Figure, Table
  - main section:
    - "OV" for Overview
    - "SIP" for Signal Interfaces and Pins,
    - "OBP" for On board Peripherals,
    - "PWR" for Power and Power-On Sequence,
    - "B2B" for Board to Board Connector,
    - "TS" for Technical Specification
    - "VCP" for Variants Currently in Production
    - "RH" for Revision History
  - name: custom, some fix names, see below
- Fix names:
  - "Figure_OV_BD" for Block Diagram
  - "Figure_OV_MC" for Main Components
  - "Table_OV_IDS" for Initial Delivery State
  - "Table_PWR_PC" for Power Consumption
  - "Figure_PWR_PD" for Power Distribution
  - "Figure_PWR_PS" for Power Sequence
  - "Figure_PWR_PM" for Power Monitoring
  - "Table_PWR_PR" for Power Rails
  - "Table_PWR_BV" for Bank Voltages
  - "Table_TS_AMR" for Absolute_Maximum_Ratings
  - "Table_TS_ROC" for Recommended_Operating_Conditions
  - "Figure_TS_PD" for Physical_Dimensions
  - "Table_VCP_SO" for TE_Shop_Overview
  - "Table_RH_HRH" for Hardware_Revision_History
  - "Figure_RH_HRN" for Hardware_Revision_Number
  - "Table_RH_DCH" for Document_Change_History
Use Anchor in the document: add link macro and add "#<anchorname>
Refer to Anchor from external : <page url>#<pagename without space characters>-<anchorname>

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-----------------------------------------------------------------------

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Note for Download Link of the Scroll ignore macro:

Link to the base folder of the module (remove de/ or en/ from the URL):
Example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5_Carriers/TE0728/

Scroll Ignore
Download PDF version of this document.

OverviewOverview

The Trenz Electronic TE0820 is an industrial/extended 4 x 5 SoM integrating an AMD Zynq UltraScale+ MPSoC, DDR4 SDRAM, eMMC memory, flash memory for configuration and data storage, as well as powerful switching power supplies for all required voltages. The module is equipped with a Lattice Mach XO2 CPLD for system controlling. Three high-speed connectors provide a large number of inputs and outputs. Additionally, the module provides Gigabit Ethernet and USB 2.0 transceivers.

The highly integrated modules are smaller than a credit card and are offered in several variants at an affordable price-performance ratio. Modules with a 4 x 5 cm form factor are completely mechanically and largely electrically compatible with each other.

All components cover at least the industrial temperature range. The temperature range in which the module can be used depends on the customer design and the selected cooling. Please contact us for special solutions.

Refer to http://trenz.org/te0820-info for the current online version of this manual and other available documentation.

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Notes :

short description of the PCB
Short Link of the wiki resources reference:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0728-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Key Features

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Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

→ See examples for different types <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-KeyFeatures

Excerpt

SoC
- Device: ZU1 / ZU2 / ZU3 / ZU4 / ZU5 ¹⁾
- Engine: CG / EG / EV ¹⁾
- Speedgrade: -1 / -1L / -2 / -2L / 3 ¹⁾
- Temperature Range: Extended / Industrial ¹⁾
- Package: SFVC784
RAM/Storage
- 2 GByte DDR4 SDRAM ²⁾
- 2 x 64 MByte Serial Flash ³⁾
- 8 GByte eMMC ³⁾
- EEPROM with MAC address
On Board
- Lattice MachXO2 CPLD
- Programmable Clock Generator
- Hi-speed USB2 ULPI Transceiver
- 10/100/1000 Mbps Ethernet Transceiver
- 4x LEDS
Interface
- 3 x B2B Connector (LSHM)
  - up to 132 PL HP IO
  - up to PS 14 MIO
  - 4 PS GTR
  - ETH (MDI) or SGMII
  - USB
  - SDIO
  - CFG, JTAG
Power
- 3.3 V power supply via B2B Connector needed ⁴⁾.
Dimension
- 40 mm x 50 mm
Notes
¹⁾ Please, take care of the possible assembly options. Furthermore, check whether the power supply is powerful enough for your FPGA design.
²⁾ Up to 4 GByte are possible with a maximum bandwidth of 2400 MBit/s.
³⁾ Please, take care of the possible assembly options.
⁴⁾ Higher input voltage may be possible.

Block Diagram

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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.

Note
For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .

Note

Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name.

Example: TE0812 Block Diagram

Note

All created DrawIOs should be named according to the Module name:

Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD

Scroll Title

anchor	Figure_OV_BD
title-alignment	center
title	TE0820 -03 block diagram

Scroll Ignore

draw.io Diagram

border	false

diagramName	TE0820 BD Block Diagram
simpleViewer	false
width
links	auto
tbstyle	hidden
diagramDisplayName
lbox	true
diagramWidth	641
revision	34

Scroll Only

Main Components

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Notes :

Picture of the PCB (top and bottom side) with labels of important components
Add List below

Note
For more information regarding how to add board photos, Please refer to "Diagram Drawing Guidline" .

Scroll Title

anchor	Figure_OV_MC
title-alignment	center
title	TE0820 main components

Scroll Ignore

draw.io Diagram

border	false

diagramName	TE0820 MC main components
simpleViewer	false
width
links	auto
tbstyle	hidden
diagramDisplayName
lbox	true
diagramWidth	641
revision	3

Scroll Only

AMD Zynq UltraScale+ MPSoC, U1
QSPI flash memory, U7, U17
DDR4 SDRAM, U2, U3
eMMC memory, U6
EEPROM, U25
Ethernet transceiver, U8
USB 2.0 ULPItransceiver, U18
B2B Connector, JM1, JM2, JM3
Lattice Semiconductor MachXO2 System Controller CPLD, U21
Clock generator, U10
Oscillator, U11, U14, U32
Done LED, D1
User LED, D2
Error Out LED, D3
Error Status LED, D4

Initial Delivery State

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Note

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

Scroll Title

anchor	Table_OV_IDS
title-alignment	center
title	Initial delivery state of programmable devices on the module

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Storage device name	Content	Notes
Quad SPI Flash	not programmed
eMMC	not programmed
DDR4 SDRAM	not programmed
Programmable Clock Generator	not programmed
EEPROM	not programmed besides factory programmed MAC address
System Controller CPLD	programmed	TE0820 CPLD

Signals, Interfaces and Pins

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For subsection examples see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-Signals,InterfacesandPins

Note
Table with all connectors and Designator List of different interfaces per connector IO CNT (for FPGA IOs where functionality can be changed by customer)

Connectors

Scroll Title

anchor	Table_SIP_C
title-alignment	center
title	Board Connectors

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Connector Type	Designator	Interface	IO CNT
B2B	JM1	ETH - MDI	ETH
B2B	JM1	HP	48 SE / 24 DIFF
B2B	JM1	MIO	8 x GPIO
B2B	JM1	SDIO	SDIO or 6 x MIO
B2B	JM2	HP	68 SE / 33 DIFF
B2B	JM2	CFG	JTAG
B2B	JM3	ETH	SGMII
B2B	JM3	MGT PS	4 x MGT (RX/TX)
B2B	JM3	MGT PS	MGT CLK
B2B	JM3	CLK	DIFF CLK
B2B	JM3	HP	16 SE / 8 DIFF
B2B	JM3	USB	USB

Test Points

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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delete the Test Point section.

Example:

Test Point	Signal	Notes¹⁾
TP1	PWR_PL_OK

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Scroll Title

anchor	Table_SIP_TPs
title-alignment	center
title	Test Points Information

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Test Point	Signal	Notes¹⁾
TP1	PS_LP0V85
TP2	DDR_2V5
TP3	PS_AVCC
TP4	DDR_1V2
TP5	PS_AVTT
TP6	VTT
TP7	PS_FP0V85
TP8	VREFA
TP9	DDR4-TEN	pulled-down to GND
TP10	PS_PLL
TP11	PL_VCCINT
TP12	PG_ALL	pulled-up to 3.3VIN
TP15	PL_VCCINT_IO
TP16	PL_VCU

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

On-board Peripherals

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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

Example:

Chip/Interface	Designator	Connected To	Notes
ETH PHY	U10	B2B connector J1 SoC MIO	Gigabit ETH PHY

Scroll Title

anchor	Table_OBP
title-alignment	center
title	On board peripherals

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Chip/Interface	Designator	Connected To	Notes
QSPI Flash	U7, U17	SoC - PS
EEPROM	U25	SoC - PS
DDR4 SDRAM	U2, U3	SoC - PS
GigaBit Ethernet	U8	SoC - PS, B2B
USB2.0 Transceiver	U18	SoC - PS, B2B
eMMC Memory	U6	SoC - PS
Oscillator	U32	SoC - PS
Oscillator	U14	USB PHY
Oscillator	U11	Clock Generator, ETH PHY
Programmable Clock Generator	U10	SoC - PS, B2B
CPLD	U21	SoC - PS, B2B
LED	D1	SoC - PS	Red, Done LED (see U+ Zynq TRM)
LED	D2	CPLD	Green, Status LED (see TE0820 CPLD)
LED	D3	SoC - PS	Red, PS Error LED (see U+ Zynq TRM)
LED	D4	SoC - PS	Green, PS Error Status LED (see U+ Zynq TRM)

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For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

Configuration and System Control Signals

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Overview all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
In case it's connected to CPLD always link to CPLD description and add not from the current implementation here(in case it's available)

Scroll Title

anchor	Table_OV_CNTRL
title-alignment	center
title	Controller signal.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Connector+Pin	Signal Name	Direction¹⁾	Description
JM1-7	NOSEQ	IN/OUT	See 4 x 5 SoM Integration Guide and TE0820 CPLD.
JM1-28	EN1	IN	See 4 x 5 SoM Integration Guide and TE0820 CPLD.
JM1-30	PGOOD	IN/OUT	See 4 x 5 SoM Integration Guide and TE0820 CPLD.
JM1-32	MODE	IN	See 4 x 5 SoM Integration Guide and TE0820 CPLD.
JM1-89	JTAGEN	IN	See 4 x 5 SoM Integration Guide and TE0820 CPLD.
JM2-18	RESIN	IN	Reset signal, see 4 x 5 SoM Integration Guide.
JM2-93 / JM2-95 / JM2-97 / JM2-99	TMS / TDI / TDO / TCK	Signal-dependent	JTAG configuration and debugging interface. JTAG reference voltage: 3.3VIN

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Power and Power-On Sequence

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Enter the default value for power supply and startup of the module here.

Order of power provided Voltages and Reset/Enable signals

Link to Schematics, for power images or more details

Power Rails

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id	Comments

List of all power rails which are accessible by the customer

Main Power Rails and Variable Bank Power

Scroll Title

anchor	Table_PWR_PR
title-alignment	center
title	Module power rails.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Power Rail Name/ Schematic Name	Connector.Pin	Direction¹⁾	Notes
VIN	JM1.1 / JM1.3 / JM1.5 / JM2.2 / JM2.4 / JM2.6 / JM2.8	IN	Supply voltage from carrier board
3.3VIN	JM1.13 / JM1.15	IN	Supply voltage from carrier board
3.3VIN	JM2.91	OUT	JTAG reference voltage
+3.3V	JM2.10 / JM2.12	OUT	Internal +3.3 V voltage level
+1.8V	JM1.39	OUT	Internal +1.8V voltage level
VCCO_64	JM2.7 / JM2.9	IN	HP Bank voltage (max. +1.9 V)
VCCO_65	JM2.5	IN	HP Bank voltage (max. +1.9 V)
VCCO_66	JM1.9 / JM1.11	IN	HP Bank voltage (max. +1.9 V)
PSBATT	JM1.79	IN	PS battery supply voltage

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Recommended Power up Sequencing

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id	Comments

List baseboard design hints for final baseboard development.

Scroll Title

anchor	Table_BB_DH
title-alignment	center
title	Baseboard Design Hints

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Sequence	Net name	Recommended Voltage Range	Pull-up/down	Description	Notes
0	-	-	-	Configuration signal setup.	See Configuration and System Control Signals.
1 ¹⁾	3.3VIN	3.3 V (± 5 %)	-	Management and SoC power supply.	Main module power supply for management and SoC. 1 A recommended. Power consumption depends mainly on design and cooling solution.
2 ¹⁾	VIN	3.3 V (± 5 %) ²⁾ OR 5.0 V (± 5 %) ²⁾	-	Main module power supply.	Main module power supply for management and SoC. 3 A to 7 A recommended. Power consumption depends mainly on design and cooling solution.
3	1.8V	-	-	1.8 V on-module power supply.
4	3.3V	-	-	3.3 V on-module power supply.
5	VCCO_64 / VCCO_65 / VCCO_66	²⁾	-	Module bank voltages.	Enable bank voltages after 1.8 V and/or 3.3 V are available on carrier.

¹⁾ In cases where VIN = 3.3VIN = 3.3 V, both voltages can be enabled together.

²⁾ A higher or lower input voltage may be possible.

²⁾ See DS925 for additional information.

Board to Board Connectors

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This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series,
For example: 6 x 6 SoM LSHM B2B Connectors
Include Page
6 x 6 SoM LSHM B2B Connectors
6 x 6 SoM LSHM B2B Connectors

Include Page

	4 x 5 SoM LSHM B2B Connectors
	4 x 5 SoM LSHM B2B Connectors

Technical Specifications

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List of all power rails which are accessible by the customer

Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)

Absolute Maximum Ratings ^*)

Scroll Title

anchor	Table_TS_AMR
title-alignment	center
title	Absolute maximum ratings

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Power Rail Name/ Schematic Name	Description	Min	Max	Unit
VIN	Supply voltage	-0.3	7	V
3.3VIN	Supply voltage	-0.3	3.75	V
VCCO_64	I/O bank voltage	-0.5	2.0	V
VCCO_65	I/O bank voltage	-0.5	2.0	V
VCCO_66	I/O bank voltage	-0.5	2.0	V
PSBATT	RTC / BBRAM	-0.5	2.0	V

^*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
or any other conditions beyond those indicated under Recommended Operating ConditionConditions. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

This TRM is generic for all variants. Temperature range can be differ depending on the assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Variants of modules are described here: Article Number Information
Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C

Scroll Title

anchor	Table_TS_ROC
title-alignment	center
title	Recommended operating conditions.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Parameter	Min	Max	Units	Reference Document
VIN¹⁾	3.135 OR 4.75	3.465 OR 5.25	V V
3.3VIN	3.135	3.465	V
VCCO_64	0.950	1.900	V	See FPGA datasheet.
VCCO_65	0.950	1.900	V	See FPGA datasheet.
VCCO_66	0.950	1.900	V	See FPGA datasheet.
PSBATT	1.200	1.500	V	See FPGA datasheet.

¹⁾ Higher values may possible. For more information consult schematic and according datasheets.

Physical Dimensions

Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm.

PCB thickness: 1.66 mm (± 10 %).

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id	Comments

In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guideline" .

Scroll Title

anchor	Figure_TS_PD
title-alignment	center
title	Physical Dimension

Scroll Ignore

draw.io Diagram

border	false

diagramName	TE0820_TS_PD PD
simpleViewer	false
width
links	auto
tbstyle	hidden
diagramDisplayName
lbox	true
diagramWidth	641
revision	3

Scroll Only

scroll-pdf	true
scroll-office	true
scroll-chm	true
scroll-docbook	true
scroll-eclipsehelp	true
scroll-epub	true
scroll-html	true

Currently Offered Variants

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id	Comments

Set correct link to the shop page overview table of the product on English and German.

Example for TE0706:

ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706

Set correct Link for Name encoding table

Scroll Title

anchor	Table_VCP_SO
title-alignment	center
title	Trenz Electronic Shop Overview

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Trenz shop TE0820 overview page*
English page	German page

*) Module article name encoding table: Zynq Ultrascale+ based modules (MPSoC, RFSoC)

Revision History

Hardware Revision History

Page properties

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id	Comments

Set correct links to download Carrier, e.g. TE0706 REV02:

TE0706-02 -> https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

Date format: YYYY-MM-DD
Example:
Date Revision Changes Documentation Link
2020-11-25 REV02
Resistors R14 and R15 was replaced by 953R (was 5K1)
Resistor R5 was replaced by 5K1, R8 by 953R (was 9K09 and 1K69 respectively)
REV02

Scroll Title

anchor	Figure_6
title-alignment	center
title	Figure 6: Module hardware revision number

Scroll Ignore

scroll-pdf	true
scroll-office	true
scroll-chm	true
scroll-docbook	true
scroll-eclipsehelp	true
scroll-epub	true
scroll-html	true

draw.io Diagram

border	true

diagramName	TE0820_HV_HRH HRH
simpleViewer	false
width
links	auto
tbstyle	top
lbox	true
diagramWidth	260
revision	2

Scroll Only

scroll-pdf	true
scroll-office	true
scroll-chm	true
scroll-docbook	true
scroll-eclipsehelp	true
scroll-epub	true
scroll-html	true

Scroll Title

anchor	Table_RH_HRH
title-alignment	center
title	Hardware Revision History

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Date	Revision	Changes	Documentation Link
2022-06-22	05	Changed EOL ferrite beads L1..5,L7,L9..12. Changed EOL DCDC U5 (EN6363QI -> MPM3860GQW-Z). Changed EOL load switch U28 (TPS27082LDDCR -> MP5077GG-Z ). Added additional decoupling capacitors and changed caps 4.7uF to 10uF (AMD doc UG583 v1.23). Added pull-down and testpoint to TEN DDR4 signal. Changed EOL transistor T1 (AO7800 -> BSD840NH6327XTSA1). Added voltage detector U30 (BD39040MUF-CE2). Changed EOL eMMC U6 (MTFC4GACAJCN-4M -> SDINBDG4-8G-XI2). Changed EOL MEMS U14 (SiT8008AI-73-XXS-52.000000E -> SiT8008BI-73-XXS-52.000000E). Added signal PG_ALL (U30) to CPLD (pin5). Added option (depends assembly variants, for all assembly variants R128 set as populated, instead special inquiry) signal POR_B through R128, T2 to CPLD (pin27). Added option (depends assembly variants, for all assembly variants R95 set as DNP, instead special inquiry) signal EN1 through R95 to DCDC U5. Added option (depends assembly variants, for all assembly variants U29 and R129 set as populated, instead special inquiry) signal PHY_LED1 through level translator U29 to FPGA (U1.K7). Added resistors R130 & R131 (select Power-on delay override, for all assembly variants R130 set as DNP -> Standard PL Power-on delay time). Added diode D5. Added Power Diagram sheet. LIB components update.	TE0820-05
2020-08-14	04	Fixed DDR4 connection (BG1), support B-die DDR4 Industrial grade chips. Added R93, changed value C62, change obsolete U28. Added R89 (10R). Added additional caps 4.7uF to PS_AVTT/PS_AVCC (AMD doc UG583). Changed R51 20k ->10K (PS_AVCC = 0.85V, AMD doc DS925 v1.17). Fixed DDR4 connection (Alert). Added 3.3V signal to CPLD. Added testpoints. LIB components update.	TE0820-04
2019-01-02	03	Fixed VCU connection: add additional DCDC (0.9V). LIB components update. Change package 1K resistors (0402 -> 0201). Added LEDs (1x user LED, 1x LED for ERR_STATUS, 1xLED for ERR_OUT). Change obsolete 2xSPI Flash (256MBit) -> 2xSPI Flash (512MBit). Added additional DCDCs (PL_VCCINT_IO, PS_FP0V85). Changed DCDC (U5) 6A (optional 4A).	TE0820-03
2017-08-17	02	Added MAC EEPROM (slave address). LIB components update. Fixed SD Card connection. Fixed sense connection from DCDC. Made correct power connection for VCU (removed DCDC, added resistors and caps like as AMD recommended). Added resistors for variants (ZU+ with/without VCU). Added termination resistors (240R) to VRP pins fro all HP-banks.	TE0820-02
2016-12-23	01	Prototype	TE0820-01

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

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Description

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Updated to new TRM style
Updated for REV05

2022-11-02

v.100

John Hartfiel

Corrected Key features

2021-12-17

v.99

Vadim Yunitski

Corrected 'Bank voltages' table

2021-07-14

v.98

John Hartfiel

bugfix boot mode

2021-07-05

v.97

John Hartfiel

published
style changes

2020-09-18

v.95

Pedram Babakhani

Update to REV04
Update the TRM format
Technical Information update

2020-03-16

v.87

John Hartfiel

Corrected PLL section
Corrected Designators USB, ETH PHY, CLK section

2020-02-03

v.85

Martin Rohrmüller

Corrected #MIOs for QSPI and USB in block diagram

2019-11-28

v.81

Martin Rohrmüller

typo and designator in section USB interface corrected

2019-10-30

v.80

John Hartfiel

typo correction

2019-09-17

v79

Martin Rohrmüller

Updated according to PCN-20190110: eMMC, QSPI-Flash

2019-07-17

v.78

Martin Rohrmüller

Corrected PJTAG Mio Pin29 in table 8

2019-05-08

v.77

John Hartfiel

Corrected EEPROM I2C Address
Correction USB PHY connection

2018-11-12

v.74

John Hartfiel

update boot section

2018-08-30

v.73

John Hartfiel

typo correction
update CPLD section
add LEDs to component list
add 3D picture of REV03 instead of REV01 picture

2018-07-12

v.69

Ali Naseri

Update PCB Rev03

2018-06-11

v.61

John Hartfiel

Rework chapter currently available products
add PJTAG note to MIOtable

2018-03-12

v.54

Correction Power Rail Section

2017-11-20

v.51

John Hartfiel

Correction Default MIO Configuration Table

2017-11-10

v.50

John Hartfiel

Replace B2B connector section

2017-10-18

v.49

John Hartfiel

add eMMC section

2017-09-25

v.48

John Hartfiel

Correction in the "Board to Board (B2B) I/Os" section
Update in the "Variants Currently In Production" section

2017-09-18

v.47

John Hartfiel

Update PS MIO table

2017-08-30

v.46

Jan Kumann

MGT lanes section added.

2017-08-24

v.36

John Hartfiel

Correction in the "Key Features" section.

2017-08-21

v.34

John Hartfiel

"Initial delivery state" section updated.

2017-08-21

v.33

Jan Kumann

HW revision 02 block diagram added.
Power distribution and power-on sequence diagram added.
System Controller CPLD and DDR4 SDRAM sections added.
TRM update to the template revision 1.6
Weight section removed.
Few minor corrections.

2017-08-18

v.7

John Hartfiel

Style changes
Updated "Boot Mode", "HW Revision History", "Variants Currently In Production" sections
Correction of MIO SD Pin-out, System Controller chapter
Update and new sub-sections on "On Board Peripherals and Interfaces" sections

2017-08-07

v.5

Jan Kumann

Initial version

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Trenz Electronic Documentation

Versions Compared

Old Version 101

New Version Current

Key

OverviewOverview

Key Features

Block Diagram

Main Components

Initial Delivery State

Signals, Interfaces and Pins

Connectors

Test Points

On-board Peripherals

QSPI Flash

EEPROM

DDR4 SDRAM

GigaBit Ethernet

USB2.0 Transceiver

eMMC Memory

Oscillator

Programmable Clock Generator

CPLD

LED

Configuration and System Control Signals

Power and Power-On Sequence

Power Rails

Recommended Power up Sequencing

Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings ^*)

Recommended Operating Conditions

Physical Dimensions

Currently Offered Variants

Revision History

Hardware Revision History

Document Change History

Disclaimer

Table of contents

Trenz Electronic Documentation

Page History

Versions Compared

Old Version 101

New Version Current

Key

OverviewOverview

Key Features

Block Diagram

Main Components

Initial Delivery State

Signals, Interfaces and Pins

Connectors

Test Points

On-board Peripherals

QSPI Flash

EEPROM

DDR4 SDRAM

GigaBit Ethernet

USB2.0 Transceiver

eMMC Memory

Oscillator

Programmable Clock Generator

CPLD

LED

Configuration and System Control Signals

Power and Power-On Sequence

Power Rails

Recommended Power up Sequencing

Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings *)

Recommended Operating Conditions

Physical Dimensions

Currently Offered Variants

Revision History

Hardware Revision History

Document Change History

Disclaimer

Table of contents

Absolute Maximum Ratings ^*)