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The Trenz Electronic TEM0005-02 is a low-cost , small FPGA module with Microsemi SmartFusion2 FPGA SoC and 32 MByte flash memory for configuration and operation. SmartFusion2 combines a 166 MHz Cortex-M3 MCU with 256 KByte Flash and 80 KByte SRAM as well as 12 kLUT FPGA Core Logic.
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- SoC/FPGA
- Package: VFG400
- Device: M2S005, M2S010, M2S025, M2S050 ,M2S060 *
- Engine: VFG166Mhz 32Bit ARM Cortex-M3
- Speed: -1, Standard*, **
- Temperature: C, I,*, **
- RAM/Storage
- Low Power DDR3
- Data width: 8/ 16bit
- Size: def. 2Gb*
- Speed: 20ns***
- SPI Flash
QSPI- Data width: 8 bit
- size: 256 M bit * bit
- 2Kb EEPROM
- On Board
- Crypto Authentication IC
- Voltage monitor IC
- 10/100 Mbps PHY Ethernet
- Interface
- Power
- 5V 3.3V supplied from carrier
- Dimension
- Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used FPGA and DDR3 combination
Block Diagram
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| Scroll Title |
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| anchor | Figure_OV_BD |
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| title | TEM0005 block diagram |
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| Scroll Ignore |
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| scroll-pdf | true |
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| scroll-office | true |
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| scroll-chm | true |
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| scroll-docbook | true |
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| scroll-eclipsehelp | true |
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| scroll-epub | true |
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| scroll-html | true |
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| | draw.io Diagram |
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| border | false |
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| diagramName | TEM0005_OV_BD |
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| simpleViewer | false |
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| width | 639 |
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| links | auto |
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| tbstyle | hidden |
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| diagramDisplayName | |
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| lbox | true |
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| diagramWidth | 641 |
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| revision | 912 |
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Main Components
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| Scroll Title |
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| anchor | Figure_OV_MC |
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| title | TEM0005 main components |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| diagramName | TEM0005_OV_MC |
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| simpleViewer | false |
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| width | 600 |
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| links | auto |
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| tbstyle | hidden |
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| diagramDisplayName | |
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| lbox | true |
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| diagramWidth | 641 |
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| revision | 20 |
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- Microsemi SmartFusionSmartFusion2 SoC, U2
- RegDual DCDC Regulator, U7
- EEPROM, U4
- 10/100 Mb Ethernet, U1
- QSPI Flash, U3
- Authentication IC, U6
- DDR3 Memory, U5
- B2B Connector, J1
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| Scroll Title |
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| anchor | Table_OV_IDS |
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| title | Initial delivery state of programmable devices on the module |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Storage device name | Content | Notes |
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Quad SPI Flash | Not Programmed |
| | EEPROM | Not Programmed |
| | DDR3 SDRAMCryptoAuthentication | Not Programmed |
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Configuration Signals
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FPGA bank number and number of I/O signals connected to the B2B connector:, J1.
| Scroll Title |
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| anchor | Table_SIP_B2B |
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| title | General PL I/O to B2B connectors information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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B2B Connector| Interface | I/O Signal Count | Voltage Level | Notes |
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JTAG access to the TEM0005 SoM through B2B connector J1.
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| anchor | Table_SIP_JTG |
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| title | JTAG pins connection |
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| Bank 1 | GPIO | 8x Single Ended | 3.3V |
| | UART | 4x Single Ended | 3.3V |
| | I2C | 2x Single Ended | 3.3V |
| | GOLDEN | 1x Single Ended | 3.3V |
| | Bank 2 | ULPI/I/O | 12x Single Ended | 3.3V |
| | I2C | 2x Single Ended | 3.3V |
| | GPIO | 10x Single Ended | 3.3V |
| | SC SPI | 4x Single Ended | 3.3V |
| | SPI1 | 7x Single Ended | 3.3V |
| | Bank 3 | JTAG | 5x Single Ended | 3.3V |
| | Reset | 1x Single Ended | 3.3V |
| | Bank 4 | I/O | 24x Single Ended/12 LVDS pairs | 3.3V |
| | Bank 6 | I/O | 28x Single Ended/14 LVDS pairs | VDDI6 | max 2.5V | | Bank 7 | I/O | 4x Single Ended | 3.3V |
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JTAG Interface
JTAG access to the TEM0005 SoM through B2B connector J1.
| Scroll Title |
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| anchor | Table_SIP_JTG |
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| title | JTAG pins connection |
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JTAG Signal
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B2B Connector
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J1-12
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Test Points
| Page properties |
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.
Example:
| Test Point | Signal | B2B | Notes |
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10 | PWR_PL_OK | J2-120 | | Scroll Title |
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| anchor | Table_SIP_TPs |
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| title | Test Points Information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Test Point | Signal | Connected to | Notes |
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TP1 | CLKOUT | Regulator, U7 |
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JTAG Signal | B2B Connector |
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| TMS | J1-14 | | TDI | J1-8 | | TDO | J1-10 | | TCK | J1-12 | | TRST | J1-7 |
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Test Points
| Page properties |
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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| Page properties |
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example: | Test Point | Signal | B2B | Notes |
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| 10 | PWR_PL_OK | J2-120 |
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| Scroll Title |
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| anchor | Table_SIP_TPs |
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| title | Test Points Information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection |
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| Scroll Title |
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| anchor | Table_OBP |
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| title | On board peripherals |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Test Point | Signal | Connected to |
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Chip/Interface | DesignatorQSPIU3 | DDR3 SDRAM | U5 | EEPROM | U4 | Authentication IC | U6 | Ethernet | U1 | |
Quad SPI Flash Memory
On-board Peripherals
| Page properties |
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
| Scroll Title |
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| anchor | Table_OBP_SPI |
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| title | Quad SPI interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Schematic | U?? Pin | Notes |
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...
- add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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| Page properties |
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
| Scroll Title |
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| anchor | Table_OBP_EEP |
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| title | I2C EEPROM interface MIOs and pinsOn board peripherals |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Schematic | U?? Pin | Notes |
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| Scroll Title |
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| anchor | Table_OBP_I2C_EEPROM |
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| title | I2C address for EEPROM |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | I2C Address | Designator | Notes |
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DDR3 SDRAM
(Quad) SPI Flash Memory
| Page properties |
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Notes : Minimum and Maximum density of DDR3 SDRAM quad SPI flash must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.
- Part number:
- Supply voltage:
- Speed:
- NOR Flash
- Temperature:
Ethernet
The TEM0005 is equipped with a (Q)SPI flash memory, U3 provided in order to store data and configuration.
| Scroll Title |
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| anchor | Table_OBP_SPI |
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| title | Quad SPI interface MIOs and pins |
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| Scroll Title |
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| anchor | Table_OBP_ETH |
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| title | Ethernet PHY to Zynq SoC connections |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| U?? Pin | Signal NameSignal Description | Note | |
...
| Notes |
|---|
| SPI0_SS0 | nCE | FPGA Bank 2 |
| | SPI0_CLK | SCK | FPGA Bank 2 |
| | SPI0_SDO | SI/IO0 | FPGA Bank 2 |
| | SPI0_SDI | SO/IO0 | FPGA Bank 2 |
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EEPROM
The TEM0005 is equipped with an EEPROM IC, U4. The I2C signals are connected to authentication IC as well.
| Scroll Title |
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| Scroll Title |
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| anchor | Table_OBP_CLKEEP |
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| title | OsillatorsI2C EEPROM interface MIOs and pins |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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DesignatorDescriptionFrequencyNote| Y3 | Crystal Oscillator | 25 MHz | |
Power and Power-On Sequence
...
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
- Power on-sequence
- Power distribution
- Voltage monitoring circuit
| Note |
|---|
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" . |
| Scroll Title |
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| anchor | Table_OBP_I2C_EEPROM |
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| title | I2C address for EEPROM |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Pin | I2C Address | Designator | Notes |
|---|
| SCL/SDA | 0x70 | U4 |
|
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Authentication IC
There is an Authentication IC ATECC608A provided on TEM0005, The IC is connected to I2C0 bus.
Power Supply
Power supply with minimum current capability of 1.5 A for system startup is recommended.
Power Consumption
| Scroll Title |
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| anchor | Table_PWROBP_PCAuth |
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| title | Power ConsumptionAuthentication IC information |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Power Input Pin | Typical Current |
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| VIN | TBD* |
* TBD - To Be Determined
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| Pin | Schematic | Notes |
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| SCL | I2C0_SCL | Serial Clock | | SDA | I2C1_SCL | Serial Data |
|
| Scroll Title |
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| anchor | FigureTable_OBP_PWRI2C_PDAuthentication IC |
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| title | Power DistributionI2C address for Authentication IC |
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|
| ignoredrawioborderfalse |
| diagramName | TEM0005_PWR_PD |
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| simpleViewer | false |
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| width | 639 |
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| links | auto |
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| tbstyle | hidden |
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diagramDisplayName | | lbox | true |
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| diagramWidth | 641 |
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| revision | 3 |
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| Scroll Only |
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 Image Removed
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Power-On Sequence
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| anchor | Figure_PWR_PS |
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| title | Power Sequency |
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| ASC | | repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Pin | I2C Address | Designator | Notes |
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| SCL/SDA | 0xC0 | U6 | This is the default value, which can be changed, see device datasheet. |
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DDR3L SDRAM
| Page properties |
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TEM0005 SoM has 2 Gb volatile DDR3L SDRAM IC for storing user application code and data.
- Part number: IS43TR16128CL-125KBLI
- Supply voltage: 1.5 V
- Temperature: -40 to 95 °C
Ethernet Transceiver
On board 10/100 Mbps Ethernet Transceiver U1 is provided on the module TEM0005.
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| Scroll Only |
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| Scroll Title |
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| anchor | FigureTable_PWROBP_VMCETH |
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| title | Voltage Monitor CircuitEthernet PHY to Zynq SoC connections |
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| ignore |
Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
| Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
Power Rails
| tablelayout |
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| orientation | portrait |
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| sortDirection |
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| Scroll Title |
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| anchor | Table_PWR_PR |
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| title | Module power rails. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Power Rail B2B Connector JM1 Pin | Direction | Notes | 3.3V | 1, 2, 3, 4 | Output | VDDI6 | 22 | Input | |
Bank Voltages
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| anchor | Table_PWR_BV |
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| title | Zynq SoC bank voltages. |
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VDDI1
...
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use "include page" macro and link to the general B2B connector page of the module series,
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Technical Specifications
Absolute Maximum Ratings
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| anchor | Table_TS_AMR |
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| title | PS absolute maximum ratings |
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Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
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| anchor | Table_TS_ROC |
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| title | Recommended operating conditions. |
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Physical Dimensions
Module size: 56 mm × 31 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 4 mm.
PCB thickness: 1.6 mm.
...
In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.
For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:
https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF
| Note |
|---|
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" . |
| Connected to | Note |
|---|
| RXM/RXP | ETH1_RX | B2B, J1 |
| | TXM/TXP | ETH1_TX | B2B, J1 |
| | LED0/NWAYEN | ETH1_LED0 | B2B, J1 |
| | LED1/SPEED | ETH1_LED1 | B2B, J1 |
| | MDIO | ETH1_MDIO | FPGA Bank 7, U2 |
| | MDC | ETH1_MDC | FPGA Bank 7, U2 |
| | REXT | - | GND |
| | INTRP | ETH1_INTRP | FPGA Bank 7, U2 |
| | XO/XI | - | Crystal Oscillator, Y3 |
| | nRST | ETH1_RST | FPGA Bank 7, U2 |
| | CONFIG0...2 | ETH1_COL/CRC/RXDV | FPGA Bank 7, U2 |
| | TXC | ETH1_TXC | FPGA Bank 7, U2 |
| | TXEN | ETH1_TXEN | FPGA Bank 7, U2 |
| | TXD0...3 | ETH1_TXD0...3 | FPGA Bank 7, U2 |
| | RXD0...3 | ETH1_RXD0...3 | FPGA Bank 7, U2 |
| | RXC | ETH1_RXC | FPGA Bank 7, U2 |
| | RXCER | ETH1_RXCER | FPGA Bank 7, U2 |
|
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Clock Sources
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| anchor | Figure_TS_PD |
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| title | Physical Dimension |
|---|
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| Scroll Only |
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| scroll-pdf | true |
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| scroll-office | true |
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| scroll-chm | true |
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| scroll-docbook | true |
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| scroll-eclipsehelp | true |
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| scroll-epub | true |
|---|
| scroll-html | true |
|---|
|
 Image Removed
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Currently Offered Variants
| Page properties |
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Set correct link to the shop page overview table of the product on English and German. Example for TE0706: ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706 DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706 |
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| anchor | Table_VCP_SO |
|---|
| title | Trenz Electronic Shop Overview |
|---|
...
Revision History
Hardware Revision History
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| anchor | Table_RH_HRH |
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| title | Hardware Revision History |
|---|
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- Support M2S050 -> added R29,R30, C24..C26,C31
- Added resistor R32
- Full upd LIB
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
...
| anchor | Figure_RV_HRN |
|---|
| title | Board hardware revision number. |
|---|
...
| Scroll Only |
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 Image Removed
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Document Change History
| Page properties |
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|
- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
|
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| anchor | Table_RH_DCH |
|---|
| title | Document change history. |
|---|
...
| Page info |
|---|
| infoType | Modified date |
|---|
| dateFormat | yyyy-MM-dd |
|---|
| type | Flat |
|---|
|
...
| Page info |
|---|
| infoType | Current version |
|---|
| prefix | v. |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
|
...
| Page info |
|---|
| infoType | Modified by |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
|
...
...
--
...
all
...
| Page info |
|---|
| infoType | Modified users |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
|
...
Disclaimer
...
| Page properties |
|---|
|
Template Revision 2.12
- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM" - Carrier: TRM Name usually "TEB Series Name" +TRM
Example: "TEB0728 TRM"
|
| HTML |
|---|
<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
<style>
.wrapped{
width: 100% !important;
max-width: 1200px !important;
}
</style> |
...
Important General Note:
...
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
...
Figure template:
...
| anchor | Figure_anchorname |
|---|
| title | Text |
|---|
| Scroll Ignore |
|---|
Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
| Scroll Only |
|---|
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
...
Table template:
- Layout macro can be use for landscape of large tables
...
| anchor | Table_tablename |
|---|
| title | Text |
|---|
...
The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below
<type>_<main section>_<name>
- type: Figure, Table
- main section:
- "OV" for Overview
- "SIP" for Signal Interfaces and Pins,
- "OBP" for On board Peripherals,
- "PWR" for Power and Power-On Sequence,
- "B2B" for Board to Board Connector,
- "TS" for Technical Specification
- "VCP" for Variants Currently in Production
- "RH" for Revision History
- name: custom, some fix names, see below
- Fix names:
"Figure_OV_BD" for Block Diagram
"Figure_OV_MC" for Main Components
"Table_OV_IDS" for Initial Delivery State
"Table_PWR_PC" for Power Consumption
- "Figure_PWR_PD" for Power Distribution
- "Figure_PWR_PS" for Power Sequence
- "Figure_PWR_PM" for Power Monitoring
- "Table_PWR_PR" for Power Rails
- "Table_PWR_BV" for Bank Voltages
"Table_TS_AMR" for Absolute_Maximum_Ratings
"Table_TS_ROC" for Recommended_Operating_Conditions
- "Figure_TS_PD" for Physical_Dimensions
- "Table_VCP_SO" for TE_Shop_Overview
"Table_RH_HRH" for Hardware_Revision_History
- "Figure_RH_HRN" for Hardware_Revision_Number
- "Table_RH_DCH" for Document_Change_History
...
| Page properties |
|---|
|
----------------------------------------------------------------------- |
| Page properties |
|---|
|
Note for Download Link of the Scroll ignore macro: |
| Scroll pdf ignore |
|---|
Table of Contents |
Overview
The Trenz Electronic TE0xxx-xx ... is an industrial-grade ... module ... based on Xilinx ...
Refer to http://trenz.org/tem0005-info for the current online version of this manual and other available documentation.
Key Features
...
Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options
Key Features' must be split into 6 main groups for modules and mainboards:
- SoC/FPGA
- Package: SFVC784
- Device: ZU2...ZU5*
- Engine: CG, EG, EV*
- Speed: -1LI, -2LE,*, **
- Temperature: I, E,*, **
- RAM/Storage
- Low Power DDR4 on PS
- Data width: 32bit
- Size: def. 2GB*
- Speed:***
- eMMC
- Data width: 8Bit
- size: def. 8GB *
- QSPI boot Flash in dual parallel mode (size depends on assembly version)
- Data width: 8bit
- size: def. 128MB *
- HyperRAM/Flash (optional, default not assembled)
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
- On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
- Interface
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, Sata, PCIe, DP)
- MIO for UART
- MIO for SD
- MIO for PJTAG
- JTAG
- Ctrl
- Power
- 3.3V-5V Main Input
- 3.3V Controller Input
- Variable Bank IO Power Input
- Dimension
- Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
Key Features' must be split into 6 main groups for carrier:
- Modules
- TE0808, TE807, TE0803,...
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
- <Replace for module use "SoC/FPGA" for Carrier "Modules">
- RAM/Storage
- On Board
- Interface
- Power
- Dimension
- Notes
Block Diagram
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add drawIO object here.
| Note |
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For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" . |
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| anchor | Figure_OV_BD |
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| title | TEM0005 block diagram |
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| Scroll Only |
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Image Removed |
Main Components
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Notes :
- Picture of the PCB (top and bottom side) with labels of important components
- Add List below
| Note |
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For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" . |
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| anchor | Figure_OV_MC |
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| title | TEM0005 main components |
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| Scroll Only |
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Image Removed |
- ...
- ...
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Initial Delivery State
| Page properties |
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Notes : Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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| anchor | Table_OV_IDS |
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| title | Initial delivery state of programmable devices on the module |
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Storage device name
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Content
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Notes
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Quad SPI Flash
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Configuration Signals
| Page properties |
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- Overview of Boot Mode, Reset, Enables.
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| anchor | Table_OV_BP |
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| title | Boot process. |
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MODE Signal State
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| anchor | Table_OV_RST |
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| title | Reset process. |
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Signal
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Signals, Interfaces and Pins
| Page properties |
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Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
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| anchor | Table_SIP_B2B |
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| title | General PL I/O to B2B connectors information |
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JTAG access to the TExxxx SoM through B2B connector JMX.
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| anchor | Table_SIP_JTG |
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| title | JTAG pins connection |
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JTAG Signal
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B2B Connector
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MIO Pins
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.
Example:
...
SPI_CS , SPI_DQ0... SPI_DQ3
SPI_SCK
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| anchor | Table_SIP_MIOs |
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| title | MIOs pins |
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Test Points
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.
Example:
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| anchor | Table_SIP_TPs |
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| title | Test Points Information |
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On-board Peripherals
| Page properties |
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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| Page properties |
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
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| anchor | Table_OBP |
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| title | On board peripherals |
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Quad SPI Flash Memory
| Page properties |
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
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| anchor | Table_OBP_SPI |
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| title | Quad SPI interface MIOs and pins |
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| anchor | Table_OBP_RTC |
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| title | I2C interface MIOs and pins |
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| anchor | Table_OBP_I2C_RTC |
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| title | I2C Address for RTC |
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| anchor | Table_OBP_EEP |
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| title | I2C EEPROM interface MIOs and pins |
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| anchor | Table_OBP_I2C_EEPROM |
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| title | I2C address for EEPROM |
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LEDs
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| anchor | Table_OBP_LED |
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| title | On-board LEDs |
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DDR3 SDRAM
| Page properties |
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.
- Part number:
- Supply voltage:
- Speed:
- NOR Flash
- Temperature:
Ethernet
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| anchor | Table_OBP_ETH |
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| title | Ethernet PHY to Zynq SoC connections |
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CAN Transceiver
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| anchor | Table_OBP_CAN |
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| title | CAN Tranciever interface MIOs |
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| anchor | Table_OBP_CLK |
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| title | Osillators |
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Programmable Clock Generator
There is a programmable clock generator on-board (U??) provided in order to generate variable clocks for the module. Programming can be done using I2C via PIN header J??. The I2C Address is 0x??.
| Scroll Title |
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| anchor | Table_OBP_PCLKCLK |
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| title | Programmable Clock Generator Inputs and OutputsOsillators |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Description | Frequency | Note |
|---|
| Y3 | Crystal Oscillator | 25 MHz | Connected to ETH PHY |
U?? Pin
| Signal | Connected to | Direction | Note |
|---|
IN0 | IN1 | IN2 | IN3 | XAXB | SCLK | SDA | OUT0 | OUT1 | OUT2 | OUT3 | OUT4 | OUT5 | OUT6 | OUT7 | OUT8/OUT9
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Power and Power-On Sequence
| Page properties |
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
Power supply with minimum current capability of xx 1.5 A for system startup is recommended.
Power Consumption
| Scroll Title |
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| anchor | Table_PWR_PC |
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| title | Power Consumption |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Power Input Pin | Typical Current |
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| VIN | TBD* |
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* TBD - To Be Determined
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Power Distribution Dependencies
| Scroll Title |
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| anchor | Figure_PWR_PD |
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| title | Power Distribution |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| |
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| diagramName | TEM0005_PWR_PD |
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| simpleViewer | false |
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| width | 639 |
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| links | auto |
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| tbstyle | hidden |
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| diagramDisplayName | |
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| lbox | true |
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| diagramWidth | 640 |
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| revision | 5 |
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| Scroll Only |
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Image Added |
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Power-On Sequence
| Scroll Title |
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| anchor | Figure_PWR_PDPS |
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| title | Power DistributionSequency |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| diagramName | TEM0005_PWR_PDPS |
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| simpleViewer | false |
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| width | 639 |
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| links | auto |
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| tbstyle | hidden |
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| diagramDisplayName | |
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| lbox | true |
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| diagramWidth | 641 |
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| revision | 3 |
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| Scroll Only |
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Image Removed |
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Image Added |
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Voltage Monitor Circuit
The TEM0005 is equipped with a voltage monitoring IC, U8. Reset Logic Output (nRST) asserts low when any of the V1, V2, or ADJ inputs are below their reset thresholds.
| Scroll Title |
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| anchor | Figure_PWR_PSVMC |
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| title | Power SequencyVoltage Monitor Circuit |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| diagramName | TEM0005_PWR_PSVMC |
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| simpleViewer | false |
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| width | 639 |
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| links | auto |
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| tbstyle | hidden |
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diagramDisplayName | | lbox | true |
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| diagramWidth | 641 |
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| revision | 1 |
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| Scroll Only |
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Image Removed |
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Voltage Monitor Circuit
| | tbstyle | hidden |
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| diagramDisplayName | |
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| lbox | true |
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| diagramWidth | 642 |
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| revision | 4 |
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| Scroll Only |
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 Image Added
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| Scroll Title |
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| anchor | Figure_PWR_VMC |
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| title | Voltage Monitor Circuit |
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| Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
| Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Power Rails
| Scroll Title |
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| anchor | Table_PWR_PR |
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| title | Module power rails. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Power Rail Name | B2B Connector |
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JM1 Pin J1 Pin | Direction | Notes |
|---|
| 3.3V | 1, 2, 3, 4 | Input |
| | VDDI6 | 22 | Input |
B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes
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Bank Voltages
| Scroll Title |
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| anchor | Table_PWR_BV |
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| title | Zynq SoC bank voltages. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic Name | | Notes |
|---|
| Bank0 | 1.5V | 1.5V |
| | Bank1 | 3.3V | 3.3V |
| | Bank2 | 3.3V | 3.3V |
| | Bank3 | 3.3V | 3.3V |
| | Bank4 | 3.3V | 3.3V |
| | Bank5 | 3.3V | 3.3V |
| | Bank6 | VDDI6 | max. 2.5V | supplied by carrier | | Bank7 | 3.3V | 3.3V | | Schematic Name | | Notes |
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Board to Board Connectors
| Page properties |
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- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
| Include Page |
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| PD:6 x 6 SoM LSHM B2B ConnectorsPD: |
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| 6 x 6 SoM LSHM B2B Connectors |
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| Include Page |
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| DRAFT:3.1 x 5.6 SoM ST5/SS5 B2B Connectors |
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| DRAFT:3.1 x 5.6 SoM ST5/SS5 B2B Connectors |
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Technical Specifications
Absolute Maximum Ratings
| Scroll Title |
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| anchor | Table_TS_AMR |
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| title | PS absolute maximum ratings |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Symbols | Description | Min | Max | Unit |
|---|
| VIN | Input Supply Voltage | -0.3 | 3.63 | V | V | V | V | | STG_T | Storage Temperature | -45 | 125 | °C | V | V | V | V |
|
Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
| Scroll Title |
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| anchor | Table_TS_ROC |
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| title | Recommended operating conditions. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Parameter | Min | Max | Units | Reference Document | | Reference Document |
|---|
| VIN | 3.15 | 3.45 | V | See the carrier datasheets. | | OPT_T | 0 /-40 | 85 | °C | See Microsemi Smartfusion2 datasheet. Depends on assembly version. | V | See ???? datasheets. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | °C | See Xilinx ???? datasheet. | °C | See Xilinx ???? datasheet. |
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Physical Dimensions
Module size: 56 mm × 31 31 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 4 mm.
PCB thickness: 1.6 mm.
| Page properties |
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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM. For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below: https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF
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| Scroll Title |
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| anchor | Figure_TS_PD |
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| title | Physical Dimension |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| |
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| diagramName | TEM0005_TS_PD |
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| simpleViewer | false |
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| width | 639 |
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| links | auto |
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| tbstyle | hidden |
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| diagramDisplayName | |
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| lbox | true |
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| diagramWidth | 641 |
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| revision | 3 |
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| Scroll Only |
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| scroll-pdf | true |
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| scroll-office | true |
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| scroll-chm | true |
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| scroll-docbook | true |
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| scroll-eclipsehelp | true |
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| scroll-epub | true |
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| scroll-html | true |
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Currently Offered Variants
| Page properties |
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Set correct link to the shop page overview table of the product on English and German. Example for TE0706: ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706 DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706 |
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| Scroll Title |
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| anchor | Table_VCP_SO |
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| title | Trenz Electronic Shop Overview |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Revision History
Hardware Revision History
...
| Scroll Title |
|---|
| anchor | Table_RH_HRH |
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| title | Hardware Revision History |
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| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
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| style | |
|---|
| widths | |
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| sortByColumn | 1 |
|---|
| sortEnabled | false |
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| cellHighlighting | true |
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| Date | Revision | Changes | Documentation Link |
|---|
| 2019-10-01 | REV01 | | REV01 | | 2020-05-20 | REV02 | |
> added - >added R29,R30, C24..C26,C31
- Added resistor R32
- Full upd LIB
| REV02 |
|
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
| Scroll Title |
|---|
| anchor | Figure_RV_HRN |
|---|
| title | Board hardware revision number. |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| |
|---|
| diagramName | TEM0005_RV_HRN |
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| simpleViewer | false |
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| width | 200 |
|---|
| links | auto |
|---|
| tbstyle | hidden |
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| diagramDisplayName | |
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| lbox | true |
|---|
| diagramWidth | 175 |
|---|
| revision | 6 |
|---|
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| Scroll Only |
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Document Change History
| Page properties |
|---|
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
|
...
| Scroll Title |
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| anchor | Table_RH_DCH |
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| title | Document change history. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
|---|
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| Date | Revision | Contributor | Description |
|---|
| Page info |
|---|
| infoType | Modified date |
|---|
| dateFormat | yyyy-MM-dd |
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| type | Flat |
|---|
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| | Page info |
|---|
| infoType | Current version |
|---|
| prefix | v. |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
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| | Page info |
|---|
| infoType | Modified by |
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| type | Flat |
|---|
| showVersions | false |
|---|
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| | -- | all | | Page info |
|---|
| infoType | Modified users |
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| type | Flat |
|---|
| showVersions | false |
|---|
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| |
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Disclaimer
| Include Page |
|---|
| IN:Legal Notices |
|---|
| IN:Legal Notices |
|---|
|
...