Versions Compared

Old Version 12

changes.mady.by.user Oleksandr Kiyenko

Saved on

compared with

New Version Current

changes.mady.by.user Oleksandr Kiyenko

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

Product Specification

Port Description

Name / opt. VHD NameDirectionPinBank PowerDescription
ADBUS0        inG93V_DFTDI TCK
ADBUS1        inF103V_DFTDI TDI
ADBUS2        outE103V_DFTDI TDO
ADBUS3        inD93V_DFTDI TMS
AVDD_SHDN     inoutG103V_DAVDD Shutdown / AVDD OV/UV
BCBUS0        -D123V_DFTDI (JTAG/UART, U4) / currently_not_used
BCBUS1        -E133V_D
BCBUS2        E123V_DBCBUS3        F13
FTDI (JTAG/UART, U4) / currently_not_used
BCBUS2        -E123V_D
BCBUS4        F12
FTDI (JTAG/UART, U4) / currently_not_used
BCBUS3        -F133V_D
BDBUS0        
FTDI (JTAG/UART, U4) / currently_not_used
BCBUS4        -F12
B11
3V_D
BDBUS1        A123V_D
FTDI (JTAG/UART, U4) / currently_not_used
BDBUS0 / FTDI_RXD-B11
BDBUS2        B12
3V_D
BDBUS3        C113V_DBDBUS4        B13
UART FTDI U4
BDBUS1 / FTDI_TXD   -A123V_D
BDBUS5        
UART FTDI U4
C12
BDBUS2        
3V_D
-
BDBUS6        
B12
C13
3V_D
BDBUS7        D113V_DCONF_DONE     
FTDI (JTAG/UART, U4) / currently_not_used
BDBUS3        -C11
C5
3V_D
DET_BPR       H23V_DDET_RIO       H33V_DDONE          N3PS_1V8EN_3V3        C103V_DEN_DAC1       E63V_DEN_DAC2       E83V_DEN_DAC3       B63V_DEN_DAC4       A63V_DEN_DDR        G133V_DEN_FPD        L123V_DEN_LPD        J133V_DEN_PSGT       B93V_DERR_OUT       G5PS_1V8ERR_STATUS    H6PS_1V8F_TCK         N2PS_1V8F_TDI         M1PS_1V8F_TDO         K1PS_1V8F_TMS         J1PS_1V8F1PWM         H103V_DF1SENSE       J93V_DFTDI_RST      E93V_DGA0           F83V_DGA0_R         F93V_DGA1           A23V_DGA1_R         B23V_DGA2           A33V_DGA2_R         B33V_DGA3           A43V_DGA3_R         B43V_DIEEE_SW_NC    C93V_DIEEE_SW_NO    A113V_DINIT_B        L2PS_1V8JTAGEN        E53V_DLED_FP_4      M43.3VLP_GOOD       H133V_DM10_RST       A73V_DM10_RX        C23V_DM10_TX        B13V_DMAX_IO1       N83.3VMAX_IO10      M103.3VMAX_IO2       N73.3VMAX_IO3       M93.3VMAX_IO4       M83.3VMAX_IO5       M123.3VMAX_IO6       M133.3VMAX_IO7       N93.3VMAX_IO8       N103.3VMAX_IO9       M113.3VMIO22         M3PS_1V8MIO23         M2PS_1V8MIO24         L3PS_1V8MIO25         H5PS_1V8MR            K103V_DN.C.J53.3VN.C.J63.3VN.C.J73.3VN.C.J83.3VN.C.K53.3VN.C.K63.3VN.C.K73.3VN.C.K83.3VN.C.L43.3VN.C.L53.3VN.C.M53.3VN.C.M73.3VN.C.N43.3VN.C.N53.3VN.C.N63.3VN.C.L103.3VN.C.L113.3VN.C.N123.3VnCONF         E73V_DnSTATUS       C43V_DON_GT_L       J123V_DON_GT_R       K123V_DPG_DDR        H83V_DPG_GT_L       H93V_DPG_GT_R       G123V_DPG_PL         L133V_DPG_PSGT       K113V_DPLL_RST       K2PS_1V8PROG_B        J2PS_1V8PSON          D63V_DRP_SCL        E13V_DRP_SDI        G43V_DRP_SDO        F43V_DRP_SL         F13V_DRST           B53V_DRST_PRST      A83V_DRST_PRST_R    B103V_DRST_R         D83V_DSATA_SCL      G23V_DSATA_SDI      F63V_DSATA_SDO      F53V_DSATA_SL       G13V_DSMB_SCL       E33V_DSMB_SCL_R     E43V_DSMB_SDA       C13V_DSMB_SDA_R     D13V_DSRST_B        H4PS_1V8SW4           A53V_DSYSEN         D73V_DUSR_BTN       J103V_DWAKE          A93V_DWAKE_R        A103V_DName / opt. VHD NameDirectionPinBank PowerDescriptionFTDI_RXDinUART receive data from FTDIFTDI_TXDoutUART transmit data to FTDIMIO22outUART receive data to FPGAMIO23inUART receive data from FPGAZYNQ_TDOinFPGA JTAG TDOZYNQ_TCKoutFPGA JTAG TCKZYNQ_TDIoutFPGA JTAG TDIZYNQ_TMSoutFPGA JTAG TMSADBUS0inFTDI JTAG TCKADBUS1inFTDI JTAG TDIADBUS2outFTDI JTAG TDOADBUS3inFTDI JTAG TMSUSB_BTNinFront panel buttonLED4outFront panel LED4MRoutSupervisor Reset outputSRST_BoutFPGA SRST_BFTDI_RSToutFPGA RST_BPLL_RSToutClock chip ResetEN_DAC1outDAC1 Power EnableEN_DAC2outDAC2 Power EnableEN_DAC3outDAC3 Power EnableEN_DAC4outDAC4 Power EnableEN_FPDoutFPD Power EnableEN_LPDoutLPD Power EnableEN_DDRoutDDR Power EnableEN_PSGToutPSGT Power EnableON_GT_LoutGT_L Power EnableON_GT_RoutGT_R Power EnablePG_PSGTinPSGT Power GoodLP_GOODinLP Power GoodPG_GT_LinGT_L Power GoodPG_GT_RinGT_R Power GoodPG_PLinPL Power GoodPG_DDRinDDR Power GoodF1PWMoutFAN PWM ControlF1SENSEinFAN SenseDONEinFPGA DONEIO1inFPGA I2C SCL_tIO2outFPGA I2C SCL_iIO3inFPGA I2C SDA_tIO4outFPGA I2C SDA_iIO5inFPGA User LED controlSCL_RoutSCL Strong Pull-Up EnableSDA_RoutSDA Strong Pull-Up EnableSCLinoutI2C SCLSDAinoutI2C SDA

Functional Description

Power

System Controller provides control and status information for main power rails. By default all power rails are ON, the user can manipulate power using I²C interface, see  Memory map table.

Reset

System controller generate a reset pulse to supervisor chip U69 when front panel button S3 is pressed.

JTAG

JTAG interface from FTDI controller passes through System Controller to FPGA.

SC to HD-IO Bank Interface

...

FTDI (JTAG/UART, U4) / currently_not_used
BDBUS4        -B133V_DFTDI (JTAG/UART, U4) / currently_not_used
BDBUS5        -C123V_DFTDI (JTAG/UART, U4) / currently_not_used
BDBUS6        -C133V_DFTDI (JTAG/UART, U4) / currently_not_used
BDBUS7        -D113V_DFTDI (JTAG/UART, U4) / currently_not_used
CONF_DONE     -C53V_D/ currently_not_used
DET_BPR       -H23V_D/ currently_not_used
DET_RIO       -H33V_D/ currently_not_used
DONE          inN3PS_1V8FPGA Done
EN_3V3        outC103V_D3.3V Power Enable
EN_DAC1       outE63V_DDAC1 Power Enable
EN_DAC2       outE83V_DDAC2 Power Enable
EN_DAC3       outB63V_DDAC3 Power Enable
EN_DAC4       outA63V_DDAC4 Power Enable
EN_DDR        outG133V_DDDR Power Enable
EN_FPD        outL123V_DFPD Power Enable
EN_LPD        outJ133V_DLPD Power Enable
EN_PSGT       outB93V_DPSGT Power Enable
ERR_OUT       -G5PS_1V8/ currently_not_used
ERR_STATUS    -H6PS_1V8/ currently_not_used
F_TCK         outN2PS_1V8FPGA TCK
F_TDI         outM1PS_1V8FPGA TDI
F_TDO         inK1PS_1V8FPGA TDO
F_TMS         outJ1PS_1V8FPGA TMS
F1PWM         outH103V_DFAN PWM Control
F1SENSE       inJ93V_DFAN Sense
FTDI_RST      outE93V_DFTDI Reset
GA0           -F83V_DBackplane address / currently_not_used
GA0_R         -F93V_DBackplane address, pullup/down enable / currently_not_used
GA1           -A23V_DBackplane address/ currently_not_used
GA1_R         -B23V_DBackplane address, pullup/down enable / currently_not_used
GA2           -A33V_DBackplane address/ currently_not_used
GA2_R         -B33V_DBackplane address, pullup/down enable / currently_not_used
GA3           -A43V_DBackplane address/ currently_not_used
GA3_R         -B43V_DBackplane address, pullup/down enable / currently_not_used
IEEE_SW_NC    -C93V_D/ currently_not_used
IEEE_SW_NO    -A113V_D/ currently_not_used
INIT_B        inL2PS_1V8FPGA Init
JTAGEN        -E53V_DJTAG Enable
LED_FP_4      outM43.3VFront panel LED
LP_GOOD       inH133V_DLP Power Good
M10_RST       -A73V_D/ currently_not_used
M10_RX        -C23V_D/ currently_not_used
M10_TX        -B13V_D/ currently_not_used
MAX_IO1 / IO1    inN83.3VI²C SCL in, ZynqMP Pin G18
MAX_IO10      -M103.3V/ currently_not_used
MAX_IO2 / IO2 outN73.3VI²C SCL out, ZynqMP Pin G19
MAX_IO3 / IO3 inM93.3VI²C SDA in, ZynqMP Pin K18
MAX_IO4 / IO4 outM83.3VI²C SDA out, ZynqMP Pin H19
MAX_IO5 / IO5 inM123.3VUser LED in, ZynqMP Pin J17
MAX_IO6       -M133.3V/ currently_not_used
MAX_IO7       -N93.3V/ currently_not_used
MAX_IO8       -N103.3V/ currently_not_used
MAX_IO9       -M113.3V/ currently_not_used
MIO22         outM3PS_1V8UART out
MIO23         inM2PS_1V8UART in
MIO24         -L3PS_1V8/ currently_not_used
MIO25         -H5PS_1V8/ currently_not_used
MR            outK103V_DSupervisor Reset out
N.C.-J53.3V/ currently_not_used
N.C.-J63.3V/ currently_not_used
N.C.-J73.3V/ currently_not_used
N.C.-J83.3V/ currently_not_used
N.C.-K53.3V/ currently_not_used
N.C.-K63.3V/ currently_not_used
N.C.-K73.3V/ currently_not_used
N.C.-K83.3V/ currently_not_used
N.C.-L43.3V/ currently_not_used
N.C.-L53.3V/ currently_not_used
N.C.-M53.3V/ currently_not_used
N.C.-M73.3V/ currently_not_used
N.C.-N43.3V/ currently_not_used
N.C.-N53.3V/ currently_not_used
N.C.-N63.3V/ currently_not_used
N.C.-L103.3V/ currently_not_used
N.C.-L113.3V/ currently_not_used
N.C.-N123.3V/ currently_not_used
nCONF         -E73V_D/ currently_not_used
nSTATUS       -C43V_D/ currently_not_used
ON_GT_L       outJ123V_DGT_L Power Enable
ON_GT_R       outK123V_DGT_R Power Enable
PG_DDR        inH83V_DDDR Power Good
PG_GT_L       inH93V_DGT_L Power Good
PG_GT_R       inG123V_DGT_R Power Good
PG_PL         inL133V_DPL Power Good
PG_PSGT       inK113V_DPSGT Power Good
PLL_RST       outK2PS_1V8PLL Chip Reset
PROG_B        outJ2PS_1V8FPGA PROG_B
PSON          -D63V_D/ currently_not_used
RP_SCL        -E13V_D/ currently_not_used
RP_SDI        -G43V_D/ currently_not_used
RP_SDO        -F43V_D/ currently_not_used
RP_SL         -F13V_D/ currently_not_used
RST           -B53V_D/ currently_not_used
RST_PRST      -A83V_D/ currently_not_used
RST_PRST_R    -B103V_D/ currently_not_used
RST_R         -D83V_D/ currently_not_used
SATA_SCL      -G23V_D/ currently_not_used
SATA_SDI      -F63V_D/ currently_not_used
SATA_SDO      -F53V_D/ currently_not_used
SATA_SL       -G13V_D/ currently_not_used
SMB_SCL       inoutE33V_DI²C SCL
SMB_SCL_R     outE43V_DI²C SCL Pullup Enable
SMB_SDA       inoutC13V_DI²C SDA
SMB_SDA_R     outD13V_DI²C SDA Pullup Enable
SRST_B        outH4PS_1V8FPGA SRST_B
SW4           inA53V_DDip Switch
SYSEN         -D73V_D/ currently_not_used
USR_BTN       inJ103V_DFront panel button
WAKE          -A93V_D/ currently_not_used
WAKE_R        -A103V_D/ currently_not_used

Functional Description

Power

System Controller provides control and status information for main power rails. By default all power rails are ON, the user can manipulate power using I²C interface, see  Memory map table.

Reset

System controller generates a reset pulse to supervisor chip U69 when front panel button S3 is pressed.

JTAG

JTAG interface from FTDI controller passes through System Controller to FPGA.

...

Anchor
i2c_interface
i2c_interface
I²C Interface

...

AddressRegisterDescription
0Input Port 0

Power status register:

Bit 0 - LP_PGOOD

Bit 1 - PG_PL

Bit 2 - PG_PSGT

Bit 3 - PG_GT_L

Bit 4 - PG_GT_R

Bit 5 - PG_DDR

Bit 6 - Not Used "0"AVDD OV/UV

Bit 7 - Not Used "0"

1Input Port 1

FAN Status register

Bits 7:0 - FAN RPM/1000

(Nominal Sepa HFB44B-12A speed is 8000 RPM)

2Output Port 0

Control register 0

Bits 1:0 - LED Control (Default "01")

Bit 2 - SMB Strong Pull-Up Enable (Default "1")

Bit 3 - Enable DAC1 Power (Default "1")

Bit 4 - Enable DAC2 Power (Default "1")

Bit 5 - Enable DAC3 Power (Default "1")

Bit 6 - Enable DAC4 Power (Default "1")

Bit 7 - Enable FPD Power (Default "1")

3Output Port 1

Control register 1

Bit 0 - Enable LPD Power (Default "1")

Bit 1 - Enable DDR Power (Default "1")

Bit 2 - Enable PSGT Power (Default "1")

Bit 3 - Enable GT_L Power (Default "1")

Bit 4 - Enable GT_R Power (Default "1")

Bit 5 - Enable FAN Power (Default "1") (Works only if 4-wire FAN is used)

Bit 6 - Not usedEnable AVDD Power (Default "1")

Bit 7 - System reset (Default "0", Reset by rising edge)Bit 7 - Not used

LED Control

Bits [1:0]Mode
"00"LED4 is OFF
"01"LED4 is Power indicator
"10"LED4 is User LED (connected to IO5)
"11"LED4 is ON

...

The System Controller control D4 LED (front panel green rightmost LED). By default, it act like power status indicator see "Power Indicator" table in "I²C interfaceI²C interface" section.


Appx. A: Change History and Legal Notices

...

  • Add I²C GPIO core
  • FAN Control/FAN Status
  • Power control

RE03 to REV04

  • BUGFIX Reset

Document Change History

To get content of older revision got to "Change History"  of this page and select older document revision number.

...

DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
current-version
current-version
prefixv.

REV03REV04REV02

Page info
modified-user
modified-user

  • REV04 finished
  • initial release
    • working in process
  • Firmware release on 2018-10-24
2018-10-10v.20REV03REV02Oleksandr Kiyenko
  • REV03 finished
  • Firmware release on 2018-10-10
2018-08-15v.3REV02REV02Antti Lukats
  • initial release

All

Page info
modified-users
modified-users


...