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Xilinx Spartan-3 generation FPGAs have a dedicated four-wire IEEE 1149.1/1532 JTAG port that is always available any time the FPGA is powered and regardless of the mode pin settings. However, when the FPGA mode pins are set for JTAG mode (M[2:0] = <1:0:1>), the FPGA waits to be configured via the JTAG port after a power-on event or after PROG_B is pulsed Low. Selecting the JTAG mode simply disables the other configuration modes. No other pins are required as part of the configuration interface.
| Info |
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| M0-M2 have Pull |
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| up resistors in FPGA. |
- If S1B and S1C are off, then signals from B2B should be left float.
- If S1B and S1C are on, then mode can be set from B2B.
| Warning | ||
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Never set Mx M2 and M1 from B2B directly to a Power Supply or to a "logical" '1' (aka a digital port with output '1'). Without an interposing resistor, a shortcircuit between Power Supply and GND is possible. Without an interposing resistor, a shortcircuit between the output of a digital port set to High ("1") and GND is possible. This could damage (or at least force the use of the overcurrent protection of) the digital port used. |
The table below shows some options about setting mode pin M2 high or low.
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