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- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM"
Template Change history: Date | Version | Changes | Author |
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| 4.1 | | ED |
| 4.0 | - Rework for smaller TRM which can be generated faster
- Reduce Signal Interfaces Pin
- Reduce On Board Perihery
- Reduce Power
- Move Configuration Signals from Overview to own section
| JH |
| 3.12 | - Version History
- changed from list to table
- all
- changed title-alignment for tables from left to center
| ma |
| 3.11 | - update "Recommended Operating Conditions" section
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| 3.1 | - New general notes for temperature range to "Recommended Operating Conditions"
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| 3.02 | - add again fix table of content with workaround to use it for pdf and wiki
- Export Link for key features examples
- Notes for different Types (with and without Main FPGA)
- Export Link for Signals, Interfaces and Pins examples
- Notes for different Types (Modul, Modul Hypride, Evalboard, Carrier)
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| 3.01 | - remove fix table of content and page layout ( split page layout make trouble with pdf export)
- changed and add note to signal and interfaces, to on board periphery section
- ...(not finished)
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| 3.00 | - → separation of Carrier/Module and evaluation kit TRM
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| 2.15 | - add excerpt macro to key features
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| 2.14 | - add fix table of content
- add table size as macro
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Important General Note:
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----------------------------------------------------------------------- |
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Note for Download Link of the Scroll ignore macro: |
Overview
The Trenz Electronic TE0818 is an industrial grade MPSoC SOM integrating a Xilinx an AMD Zynq UltraScale+ MPSoC, DDR4 SDRAM with 64-Bit width data bus connection, SPI Boot Flash memory for configuration and operation, transceivers and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking connections in a compact 5.2 cm x 7.6 cm form factor.
Refer to http://trenz.org/te0818-info for the current online version of this manual and other available documentation.
Key Features
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- SoC
- Device: ZU6 / ZU9 / ZU15 1)
- Engine: CG / EG 1)
- Speedgrade: -1 / -2 1)
- Temperature Range: Extended / Industrial 1)
- Package: FFVC900
- RAM/Storage
- 4 GByte DDR4 SDRAM 2)
- 2 x 64 MByte Serial Flash 3)
- EEPROM with MAC address
- On Board
- Interface
- 4 x B2B Connector (ADM6)
up to 204 PL IO up to 65 PS MIO - 4 GTR
- 16 GTH
- I2C, JTAG, CONFIG
- Power
- 3.3 V power supply via B2B Connector needed 4).
- Dimension
- Notes
1) Please, take care of the possible assembly options. Furthermore, check whether the power supply is powerful enough for your FPGA design. 2) Up to 32 GByte are possible with a maximum bandwidth of 2400 MBit/s. 3) Please, take care of the possible assembly options. 4) Dependant Dependent on the assembly option a higher input voltage may be possible
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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.
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Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name. Example: TE0812 Block Diagram |
Note |
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All created DrawIOs should be named according to the Module name: Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD |
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anchor | Figure_OV_BD |
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title-alignment | center |
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title | TExxxx TE0818 block diagram |
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Scroll Ignore |
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draw.io Diagram |
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border | true |
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diagramName | TE0818_OV_BD |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | top |
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lbox | true |
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diagramWidth | 641 |
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revision | 35 |
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Scroll Only |
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Main Components
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Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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Scroll Title |
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anchor | Figure_OV_MC |
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title-alignment | center |
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title | TExxxx main components |
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Scroll Ignore |
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draw.io Diagram |
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border | true |
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diagramName | Figure_OV_MC |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | top |
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lbox | true |
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diagramWidth | 752751 |
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revision | 34 |
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Scroll Only |
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- SoC, U1
- DDR4, U2, U3, U9, U12
- Quad SPI Flash, U7, U17
- Connector, J1, J2, J3, J4
- EEPROM, U4
- Clock Generator, U5
- Oscillator, U25, U32
Initial Delivery State
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Note |
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Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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Scroll Title |
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anchor | Table_OV_IDS |
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title-alignment | center |
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title | Initial delivery state of programmable devices on the module |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Storage device name | Content | Notes |
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DDR4 SDRAM | not programmed |
| Quad SPI Flash | not programmed |
| EEPROM | not programmed besides factory programmed MAC address |
| Programmable Clock Generator | not programmed |
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Signals, Interfaces and Pins
Connectors
Scroll Title |
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anchor | Table_SIP_C |
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title-alignment | center |
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title | Board Connectors |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Connector Type | Designator | Interface | IO CNT | Notes |
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B2B | JM1J1 | MGT PL | 12 x MGT (RX/TX) |
| B2B | JM1J1 | HP | 52 SE / 24 DIFF |
| B2B | JM2J2 | MGT PS | 2 x MGT CLK |
| B2B | JM2J2 | CLK | DIFF CLK |
| B2B | JM2J2 | MGT PL | 4 x MGT (RX/TX) |
| B2B | JM2J2 | MGT PS | 4 x MGT (RX/TX) |
| B2B | JM2J2 | CFG | JTAG |
| B2B | JM2J2 | CFG | MODE |
| B2B | JM3J3 | HD | 48 SE / 24 DIFF |
| B2B | JM3J3 | MGT PL | 3 x MGT CLK |
| B2B | JM3J3 | CLK | DIFF CLK |
| B2B | JM3J3 | MIO | 65 GPIO |
| B2B | JM4J4 | HP | 104 SE / 48 DIFF |
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Test Points
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example: Test Point | Signal | Notes1) |
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TP1 | PWR_PL_OK |
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1) Direction: - IN (C2M): Carrier to Module, means it's an input from the point of view of this board
- OUT (M2C): Module to Carrier, means it's output from the point of view of this board
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Scroll Title |
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anchor | Table_SIP_TPs |
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title-alignment | center |
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title | Test Points Information |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Test Point | Signal | Notes | Revision Notes |
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TP1 | PLL_SCL | pulled-up to PS_1V8 |
| TP2 | PLL_SDA | pulled-up to PS_1V8 |
| TP3 | LP_DCDC |
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| TP4 | DCDCIN |
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| TP5 | GND |
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| TP6 | TCK |
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| TP7 | PL_DCIN |
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| TP8 | GND |
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| TP9 | GT_DCDC |
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| TP10 | GND |
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| TP11 | TDI |
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| TP12 | TDO |
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| TP13 | TMS |
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| TP14 | PS_1V8 |
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| TP15 | No Net Name1V25_REF | REF3312AIDCKT (U33) ouput voltage | No Net Name for REV01. | TP16 | FP_0V85 |
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| TP17 | DDR_2V5 |
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| TP18 | DDR_PLL |
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| TP19 | PL_VCCINT |
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| TP20 | AUX_R |
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| TP21 | AVTT_R |
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| TP22 | AUX_L |
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| TP23 | DDR4-TEN |
| Only REV02. | TP24 | AVCC_R |
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| TP25 | PLL_SDA | pulled-up to PS_1V8 | Only REV02. | TP26 | AVTT_L | TP28AVCCTP30 | LSCL | pulled-up to PS_1V8 | Only REV02. | TP28 | AVCC_L |
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| TP29 | LP_DCDC |
| Only REV02. | TP30 |
PS_PLL |
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| TP31 | PS_AVTT |
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| TP32 | LP_0V85 |
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| TP33 | PS_AUX |
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| TP34 | PS_AVCC |
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| TP35 | DCDCIN |
| Only REV02. | TP36 | POR_B |
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On-board Peripherals
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Notes :
In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection
Example:
Chip/Interface | Designator | Connected To | Notes |
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ETH PHY | U10 | | Gigabit ETH PHY |
Scroll Title |
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anchor | Table_OBP |
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title-alignment | center |
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title | On board peripherals |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Chip/Interface | Designator | Connected To | Notes |
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DDR4 SDRAM | U2, U3, U9, U12 | SoC - PS | Quad SPI Flash | U7, U17 | SoC - PS | Booting. |
EEPROM | U4 | B2B - J2 | Clock Generator | U5 | SoC, B2B | Oscillator | U25 | Clock Generator | 25 MHz |
Oscillator | U32 | SoC | 33.333333 MHz |
Configuration and System Control Signals
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- Overview all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
- In case it's connected to CPLD always link to CPLD description and add not from the current implementation here(in case it's available)
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Scroll Title |
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anchor | Table_OV_CNTRL |
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title-alignment | center |
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title | Controller signal. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Connector+Pin | Signal Name | Direction1) | Description |
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JM1.A45 | POR_OVERRIDE | IN | Override power-on reset delay 2). |
JM2.A30 | PG_PLL_1V8 | OUT | SI_PLL_1V8 power rail powered-up. |
JM2.A31 | ERR_OUT | OUT | PS error indication 2). |
JM2.A34 | ERR_STATUS | OUT | PS error status 2). |
JM2.A35 | LP_GOOD | OUT | Low-power domain powered-up. Pulled up to 3.3VIN. |
JM2.A36 | PLL_SCL | IN | I2C clock. Pulled up to PS_1V8. |
JM2.A37 | PLL_SDA | IN/OUT | I2C data. Pulled up to PS_1V8. |
JM2.A40 | PG_GT_L | OUT | Left GTH Transceivers powered-up. |
JM2.A41 | EN_PSGT | IN | Enable GTR transceiver power-up. |
JM2.A44 / JM2.A45 / JM2.A46 / JM2.A47 | TCK / TDI / TDO / TMS | Signal-dependent | JTAG configuration and debugging interface. JTAG reference voltage: PS_1V8 |
JM2.B29 | PG_PSGT | OUT | GTR transceivers powered-up. |
JM2.B30 | PROG_B | IN/OUT | Power-on reset 2). Pulled-up to PS_1V8. |
JM2.B33 | SRST_B | IN | System reset 2). Pulled-up to PS_1V8. |
JM2.B34 | INIT_B | IN/OUT | Initialization completion indicator after POR 2). Pulled-up to PS_1V8. |
JM2.B37 | PG_PL | OUT | Programmable logic powered-up. |
JM2.B38 | EN_FPD | IN | Enable full-power domain power-up. |
JM2.B41 | PG_FPD | OUT | Full-power domain powered-up. |
JM2.B42 | EN_LPD | IN | Enable low-power domain power-up. |
JM2.B45 | PG_DDR | OUT | DDR power supply powered-up. |
JM2.B46 | DONE | OUT | PS done signal 2). Pulled-up to PS_1V8. |
JM2.B47 | EN_DDR | IN | Enable DDR power-up. |
JM2.C30 | EN_GT_L | IN | Enable left GTH transceiver power-up. |
JM2.C31 | MR | IN | Manual reset. |
JM2.C32 | PLL_SEL0 | IN | PLL clock selection. |
JM2.C33 | PLL_RST | IN | PLL reset. Pulled-up to PS_1V8. |
JM2.C35 | EN_PL | IN | Enable programable logic power-up. |
JM2.C36 | EN_GT_R | IN | Enable right GTH transceiver power-up. |
JM2.C37 | PLL_FDEC | IN | PLL Frequency decrementation. |
JM2.C44 / JM2.C45 / JM2.C46 / JM2.C47 | MODE3..0 | IN | Boot mode selection 2):
- JTAG
- QUAD-SPI (32 Bit)
- SD1 (2.0)
- eMMC (1.8 V)
- SD1 LS (3.0)
Supported Modes depends also on used Carrier. |
JM2.D29 | EN_PLL_PWR | IN | Enable PLL power supply. |
JM2.D30 | PLL_FINC | IN | PLL Frequency incrementation. |
JM2.D31 | PLL_LOLn | OUT | Loss of lock status. |
JM2.D32 | PLL_SEL1 | IN | PLL clock selection. |
JM2.D33 | PG_GT_R | OUT | Right GTH Transceivers powered-up. |
JM2.D37 | PSBATT | IN | PS RTC Battery supply voltage 2) 3). |
JM2.D38 | PUDC_B | IN | Configuration pull-ups setting 2). Pulled-up to PL_1V8. |
JM2.D45 / JM2.D46 | DX_P / DX_N | - | SoC temperatur sensing diode pins 2). |
1) Direction:
- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
2) See UG1085 for additional information.
3) See Recommended Operating Conditions.
Power and Power-On Sequence
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Enter the default value for power supply and startup of the module here. - Order of power provided Voltages and Reset/Enable signals
Link to Schematics, for power images or more details |
Power Rails
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List of all Powerrails which are accessible by the customer
- Main Power Rails and Variable Bank Power
Scroll Title |
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anchor | Table_PWR_PR |
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title-alignment | center |
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title | Module power rails. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Rail Name/ Schematic Name | Connector + Pin | Direction1) | Notes |
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| TP37 | PL_DCIN |
| Only REV02. | TP38 | GT_DCDC |
| Only REV02. | TP39 | PS_1V8 |
| Only REV02. | TP40 | 1V25_REF |
| Only REV02. | TP41 | FP_0V85 |
| Only REV02. | TP42 | DDR_2V5 |
| Only REV02. | TP43 | DDR_PLL |
| Only REV02. | TP44 | PL_VCCINT |
| Only REV02. | TP45 | AUX_R |
| Only REV02. | TP46 | AVTT_R |
| Only REV02. | TP47 | AUX_L |
| Only REV02. | TP48 | AVCC_R |
| Only REV02. | TP49 | AVTT_L |
| Only REV02. | TP50 | AVCC_L |
| Only REV02. | TP51 | PS_PLL |
| Only REV02. | TP52 | PS_AVTT |
| Only REV02. | TP53 | LP_0V85 |
| Only REV02. | TP54 | PS_AUX |
| Only REV02. | TP55 | PS_AVCC |
| Only REV02. | TP56 | DDR_1V2 |
| Only REV02. | TP57 | DDR_1V2 |
| Only REV02. | TP58 | SI_PLL_1V8 |
| Only REV02. | TP59 | SI_PLL_1V8 |
| Only REV02. | TP60 | PL_GT2_1V35 |
| Only REV02. | TP61 | PL_GT2_1V35 |
| Only REV02. | TP62 | PL_GT2_1V05 |
| Only REV02. | TP63 | PL_GT2_1V05 |
| Only REV02. | TP64 | PL_GT_1V35 |
| Only REV02. | TP65 | PL_GT_1V35 |
| Only REV02. | TP66 | PL_GT_1V05 |
| Only REV02. | TP67 | PL_GT_1V05 |
| Only REV02. | TP68 | 3.3VIN |
| Only REV02. | TP69 | 3.3VIN |
| Only REV02. | TP70 | DCDC_2V0 |
| Only REV02. | TP71 | DCDC_2V0 |
| Only REV02. | TP72 | PS_GT_1V0 |
| Only REV02. | TP73 | PS_GT_1V0 |
| Only REV02. | TP74 | PL_1V8 |
| Only REV02. | TP75 | PL_1V8 |
| Only REV02. | TP76 | VREFA |
| Only REV02. | TP77 | VREFA |
| Only REV02. | TP78 | VTT |
| Only REV02. | TP79 | VTT |
| Only REV02. |
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On-board Peripherals
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection Example: Chip/Interface | Designator | Connected To | Notes |
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ETH PHY | U10 | | Gigabit ETH PHY |
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Scroll Title |
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anchor | Table_OBP |
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title-alignment | center |
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title | On board peripherals |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Chip/Interface | Designator | Connected To | Notes |
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DDR4 SDRAM | U2, U3, U9, U12 | SoC - PS |
| Quad SPI Flash | U7, U17 | SoC - PS | Booting. | EEPROM | U4 | B2B - J2 |
| Clock Generator | U5 | SoC, B2B |
| Oscillator | U25 | Clock Generator | 25 MHz | Oscillator | U32 | SoC | 33.333333 MHz |
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Configuration and System Control Signals
Page properties |
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|
- Overview all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
- In case it's connected to CPLD always link to CPLD description and add not from the current implementation here(in case it's available)
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Scroll Title |
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anchor | Table_OV_CNTRL |
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title-alignment | center |
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title | Controller signal. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Connector+Pin | Signal Name | Direction1) | Description |
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J1.A45 | POR_OVERRIDE | IN | Override power-on reset delay 2). | J2.A30 | PG_PLL_1V8 | OUT | SI_PLL_1V8 power rail powered-up. | J2.A31 | ERR_OUT | OUT | PS error indication 2). | J2.A34 | ERR_STATUS | OUT | PS error status 2). | J2.A35 | LP_GOOD | OUT | Low-power domain powered-up. Pulled up to 3.3VIN. | J2.A36 | PLL_SCL | IN | I2C clock. Pulled up to PS_1V8. | J2.A37 | PLL_SDA | IN/OUT | I2C data. Pulled up to PS_1V8. | J2.A40 | PG_GT_L | OUT | Left GTH Transceivers powered-up. | J2.A41 | EN_PSGT | IN | Enable GTR transceiver power-up. | J2.A44 / J2.A45 / J2.A46 / J2.A47 | TCK / TDI / TDO / TMS | Signal-dependent | JTAG configuration and debugging interface. JTAG reference voltage: PS_1V8 | J2.B29 | PG_PSGT | OUT | GTR transceivers powered-up. | J2.B30 | PROG_B | IN/OUT | Power-on reset 2). Pulled-up to PS_1V8. | J2.B33 | SRST_B | IN | System reset 2). Pulled-up to PS_1V8. | J2.B34 | INIT_B | IN/OUT | Initialization completion indicator after POR 2). Pulled-up to PS_1V8. | J2.B37 | PG_PL | OUT | Programmable logic powered-up. | J2.B38 | EN_FPD | IN | Enable full-power domain power-up. | J2.B41 | PG_FPD | OUT | Full-power domain powered-up. | J2.B42 | EN_LPD | IN | Enable low-power domain power-up. | J2.B45 | PG_DDR | OUT | DDR power supply powered-up. | J2.B46 | DONE | OUT | PS done signal 2). Pulled-up to PS_1V8. | J2.B47 | EN_DDR | IN | Enable DDR power-up. | J2.C30 | EN_GT_L | IN | Enable left GTH transceiver power-up. | J2.C31 | MR | IN | Manual reset. | J2.C32 | PLL_SEL0 | IN | PLL clock selection. | J2.C33 | PLL_RST | IN | PLL reset. Pulled-up to PS_1V8. | J2.C35 | EN_PL | IN | Enable programable logic power-up. | J2.C36 | EN_GT_R | IN | Enable right GTH transceiver power-up. | J2.C37 | PLL_FDEC | IN | PLL Frequency decrementation. | J2.C44 / J2.C45 / J2.C46 / J2.C47 | MODE3..0 | IN | Boot mode selection 2):
- JTAG
- QUAD-SPI (32 Bit)
- SD1 (2.0)
- eMMC (1.8 V)
- SD1 LS (3.0)
Supported Modes depends also on used Carrier. | J2.D29 | EN_PLL_PWR | IN | Enable PLL power supply. | J2.D30 | PLL_FINC | IN | PLL Frequency incrementation. | J2.D31 | PLL_LOLn | OUT | Loss of lock status. | J2.D32 | PLL_SEL1 | IN | PLL clock selection. | J2.D33 | PG_GT_R | OUT | Right GTH Transceivers powered-up. | J2.D37 | PSBATT | IN | PS RTC Battery supply voltage 2) 3). | J2.D38 | PUDC_B | IN | Configuration pull-ups setting 2). Pulled-up to PL_1V8. | J2.D45 / J2.D46 | DX_P / DX_N | - | SoC temperatur sensing diode pins 2). |
1) Direction: - IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
2) See UG1085 for additional information. 3) See Recommended Operating Conditions.
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Power and Power-On Sequence
Page properties |
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Enter the default value for power supply and startup of the module here. - Order of power provided Voltages and Reset/Enable signals
Link to Schematics, for power images or more details |
Power Rails
Page properties |
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|
List of all Powerrails which are accessible by the customer - Main Power Rails and Variable Bank Power
|
Scroll Title |
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anchor | Table_PWR_PR |
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title-alignment | center |
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title | Module power rails. |
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|
Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Rail Name/ Schematic Name | Connector + Pin | Direction1) | Notes |
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VCCO_66 | J1.A32 / J1.A33 | IN |
| VREF_66 | J1.A41 | IN |
| 3.3VIN | J1.A54 / J1.A55 / J1.B55 / J1.B56 | IN |
| PL_1V8 | J1.C32 / J1.C33 / J1.D33 / J1.D34 | OUT |
| PL_DCIN | J1.C56 / J1.C57 / J1.C58 / J1.C59 / J1.C60 / J1.D56 / J1.D57 / J1.D58 / J1.D59 / J1.D60 | IN |
| LP_DCDC | J2.A50 / J2.A51 / J2.A52 / J2.B50 / J2.B51 / J2.B52 / J2.C50 / J2.C51 / J2.C52 / J2.D50 / J2.D51 / J2.D52 | IN |
| DCDCIN | J2.A57 / J2.A58 / J2.A59 / J2.A60 / J2.B57 / J2.B58 / J2.B59 / J2.B60 / J2.C57 / J2.C58 / J2.C59 / J2.C60 / J2.D57 / J2.D58 / J2.D59 / J2.D60 / | IN |
| PS_BATT | J2.D37 | IN |
| DDR_1V2 | J2.D47 | OUT |
| PS_1V8 | J2.C34 / J2.D34 / J3.A56 / J3.B56 / J3.C56 / J3.D56 | OUT |
| PLL_3V3 | J3.A55 | IN |
| GT_DCDC | J3.A59 / J3.A60 / J3.B59 / J3.B60 / J3.C59 / J3.C60 / J3.D59 / J3.D60 / | IN |
| VCCO_48 | J3.C7 / J3.C8 / J3.D8 / J3.D9 | IN |
| VCCO_47 | J3.C19 / J3.C20 / J3.D20 / J3.D21 | IN |
| VCCO_64 | J4.B21 / J4.B39 | IN |
| VREF_64 | J4.B30 | IN |
| VCCO_65 | J4.C21 / J4.C39 | IN |
| VREF_65 | J4.C30 | IN |
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1) Direction: - IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
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Recommended Power up Sequencing
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List baseboard design hints for final baseboard development. |
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title-alignment | center |
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title | Baseboard Design Hints |
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The power up sequencing highly depends on the use case. In general, it should be possible to enable/disable the processing system (PS) / programmable logic (PL) independently. Furthermore, within the processing logic it should be possible to enable/disable only low-power domain and/or low-power and full-power domain. Additionally, usage of GTR for PS side and GTH for PL side should be possible. GTH transceivers on left and right side are usable independently. Because of this flexibility the needed parts of the following table needs to be selected individually. For detailed information take a look into schematics. Sequence | Net name | Recommended Voltage Range | Pull-up/down | Description | Notes |
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0 | - | - | - | Configuration signal setup. | See Configuration and System Control Signals. | 1 1) | PSBATT | 1.2 V ... 1.5 V | - | Battery connection. | Battery Power Domain usage. When not used, tie to GND. | 1 | 3.3VIN | 3.3 V (± 5 %) | - | Management power supply. | Management module power supply. 0.5 A recommended. | GTH / GTR Transceiver clocking (Only necessary in cases where the PLL clock is used for GTH / GTR.): | 1 1) | GT_DCDC | 3.3 V (± 5 %) 2) |
| GTH transceiver power supply. | Main module power supply for GTH / GTY transceiver. 5 A recommended. Power consumption depends mainly on design and cooling solution. | 1 1) | EN_PLL_PWR | - | PU 3), 3.3VIN | PLL power enable. |
| 1 1) | PG_PLL_1V8 |
|
VCCO_66 | JM1.A32 / JM1.A33 | IN | VREF_66 | JM1.A41 | IN | 3.3VIN | JM1.A54 / JM1.A55 / JM1.B55 / JM1.B56 | IN | PL_1V8 | JM1.C32 / JM1.C33 / JM1.D33 / JM1.D34 | OUT | PL_DCIN | JM1.C56 / JM1.C57 / JM1.C58 / JM1.C59 / JM1.C60 / JM1.D56 / JM1.D57 / JM1.D58 / JM1.D59 / JM1.D60 | IN | LP_DCDC | JM2.A50 / JM2.A51 / JM2.A52 / JM2.B50 / JM2.B51 / JM2.B52 / JM2.C50 / JM2.C51 / JM2.C52 / JM2.D50 / JM2.D51 / JM2.D52 | IN | DCDCIN | JM2.A57 / JM2.A58 / JM2.A59 / JM2.A60 / JM2.B57 / JM2.B58 / JM2.B59 / JM2.B60 / JM2.C57 / JM2.C58 / JM2.C59 / JM2.C60 / JM2.D57 / JM2.D58 / JM2.D59 / JM2.D60 / | IN | PS_BATT | JM2.D37 | IN | DDR_1V2 | JM2.D47 | OUT | PS_1V8 | JM2.C34 / JM2.D34 / JM3.A56 / JM3.B56 / JM3.C56 / JM3.D56 | OUT | PLL_3V3 | JM3.A55 | IN | GT_DCDC | JM3.A59 / JM3.A60 / JM3.B59 / JM3.B60 / JM3.C59 / JM3.C60 / JM3.D59 / JM3.D60 / | IN | VCCO_48 | JM3.C7 / JM3.C8 / JM3.D8 / JM3.D9 | IN | VCCO_47 | JM3.C19 / JM3.C20 / JM3.D20 / JM3.D21 | IN | VCCO_64 | JM4.B21 / JM4.B39 | IN | VREF_64 | JM4.B30 | IN | VCCO_65 | JM4.C21 / JM4.C39 | IN | VREF_65 | JM4.C30 | IN | 1) Direction:
- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
Recommended Power up Sequencing
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List baseboard design hints for final baseboard development. |
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title | Baseboard Design Hints |
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orientation | portrait |
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repeatTableHeaders | default |
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cellHighlighting | true |
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The power up sequencing highly depends on the use case. In general, it should be possible to enable/disable the processing system (PS) / programmable logic (PL) independently. Furthermore, within the processing logic it should be possible to enable/disable only low-power domain and/or low-power and full-power domain. Additionally, usage of GTR for PS side and GTH for PL side should be possible. GTH transceivers on left and right side are usable independently. Because of this flexibility the needed parts of the following table needs to be selected individually. For detailed information take a look into schematics.
Sequence | Net name | Recommended Voltage Range | Pull-up/down | Description | Notes |
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0 | - | - | - | Configuration signal setup. | See Configuration and System Control Signals. |
1 1) | PSBATT | 1.2 V ... 1.5 V | - | Battery connection. | Battery Power Domain usage. When not used, tie to GND. |
1 | 3.3VIN | 3.3 V (± 5 %) | - | Management power supply. | Management module power supply. 0.5 A recommended. |
GTH / GTR Transceiver clocking (Only necessary in cases where the PLL clock is used for GTH / GTH.): |
1 1) | GT_DCDC | 3.3 V (± 5 %) 2) | GTH transceiver power supply. | Main module power supply for GTH / GTY transceiver. 5 A recommended. Power consumption depends mainly on design and cooling solution. | 1 1) | EN_PLL_PWR | - | PU 3), 3.3VIN | PLL power enable. | 1 1) | PG_PLL_1V8 | - | PU 3), 3.3VIN | PLL power good status. | 2 | Processing System (PS):
Procedure for PS starting. | 2.1 | Low-power domain: | Bring-up for low-power domain PS. | 2.1.1 | LP_DCDC | 3.3 V (± 5 %) 2) | - | Low-power domain power supply. | Main module power supply for low-power domain. 5.5 A recommended. Power consumption depends mainly on design and cooling solution. |
2.1.2 | EN_LPD | - | PU 3), 3.3VIN | Low-power domain power enable. | 2.1.3 | LP_GOOD | - | PU 3), 3.3VIN | Low-power domain power good status. | Module power-on sequencing for low-power domain finished. |
2.2 | Full-power domain: | Bring-up for full-power domain PS. | Full-power PS domain needs powered low-power PS domain. |
2.2.1 | DCDCIN | 3.3 V (± 5 %) 2) | Full-power domain and GTR transceiver power supply. | Main module power supply for full-power domain. 7 A recommended. Power consumption depends mainly on design and cooling solution. | 2.2.2 | EN_FPD | 3.3 V | - | Full-power domain power enable. | 2.2.3 | PG_FPD | - | PU 3), 3.3VIN | Full-power domain power good status. | Module power-on sequencing for full-power domain finished. |
2.2.4 | EN_DDR | 3.3 V | - | DDR memory power enable. | 2.2.5 | PG_DDR | PU 3), 3.3VIN | DDR memory power good status. | Module power-on sequencing for DDR memory finished. | 2.3 | GTR Transceiver | Procedure for GTR transceiver starting. | PS transceiver usage needs powered PS (low- and full-power domain). |
2.3.1 | EN_PSGT | 3.3 V | - | GTR transceiver power enable. | 2.3.2 | PG_PSGT | - | PU 3), 3.3VIN | GTR transceiver PLL power good status. | Module power-on sequencing for GTR transceiver finished. |
|
1 1) | PLL_3V3 | 3.3 V (± 5 %) |
| PLL power supply |
|
2 | Processing System (PS):
| Procedure for PS starting. |
|
2.1 | Low-power domain: | Bring-up for low-power domain PS | 2 | Programmable Logic (PL) | Procedure for PL starting. | PS and PL can be started independently. |
|
2.1.1 | PLLP_DCINDCDC | 3.3 V (± 5 %) 2) | - | Programmable logic Low-power domain power supply. | Main module power supply for programmable logic. 12 low-power domain. 5.5 A recommended. Power consumption depends mainly on design and cooling solution. |
2.1.2 | EN_PLLPD | - | PU 3), 3.3VIN | Programmable logic Low-power domain power enable. |
|
2.1.3 | PGLP_PLGOOD | - | PU 3), 3.3VIN | Programmable logic Low-power domain power good status. | Module power-on sequencing for programmable logic finished. Periphery and variable bank voltages can be enabled on carrier. |
2.4 | VCCO_47 / VCCO_48 / VCCO_64 / VCCO_65 / VCCO_66 | 4) | - | Module bank voltages. | Enable bank voltages after PG_PL deassertion. |
low-power domain finished. |
2.2 | Full-power domain: | Bring-up for full-power domain PS. | Full-power PS domain needs powered | 3 | GTH / GTY Transceiver | Procedure for GTH / GTY transceiver starting. | PL transceiver usage needs powered PL and low-power PS domain. |
32.2.1 | GT_DCDCDCDCIN | 3.3 V (± 5 %) 2) | - |
| GTH Full-power domain and GTR transceiver power supply. | Main module power supply for GTH transceiver. 5 full-power domain. 7 A recommended. Power consumption depends mainly on design and cooling solution. |
32.2.2 | EN_GT_L / EN_GT_RFPD | 3.3 V | - | GTH / GTY left / right transceiver Full-power domain power enable. | Transceivers on left / right side can be used independently. |
|
32.2.3 | PG_GT_L / PG_GT_RFPD | - | PU 3), 3.3VIN | GTH / GTY transceiver Full-power domain power good status. |
1) (optional)
2) Dependent on the assembly option a higher input voltage may be possible.
3) (on module)
4) See DS925 for additional information.
Board to Board Connectors
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This section is optional and only for modules.Module power-on sequencing for full-power domain finished. | 2.2.4 | EN_DDR | 3.3 V | - | DDR memory power enable. |
| 2.2.5 | PG_DDR |
| PU 3), 3.3VIN | DDR memory power good status. | Module power-on sequencing for DDR memory finished. | 2.3 | GTR Transceiver | Procedure for GTR transceiver starting. | PS transceiver usage needs powered PS (low- and full-power domain). | 2.3.1 | EN_PSGT | 3.3 V | - | GTR transceiver power enable. |
| 2.3.2 | PG_PSGT | - | PU 3), 3.3VIN | GTR transceiver power good status. | Module power-on sequencing for GTR transceiver finished. | 2 | Programmable Logic (PL) | Procedure for PL starting. | PS and PL can be started independently. | 2.1 | PL_DCIN | 3.3 V (± 5 %) 2) | - | Programmable logic power supply. | Main module power supply for programmable logic. 12 A recommended. Power consumption depends mainly on design and cooling solution. | 2.2 | EN_PL | - | PU 3), 3.3VIN | Programmable logic power enable. |
| 2.3 | PG_PL | - | PU 3), 3.3VIN | Programmable logic power good status. | Module power-on sequencing for programmable logic finished. Periphery and variable bank voltages can be enabled on carrier. | 2.4 | VCCO_47 / VCCO_48 / VCCO_64 / VCCO_65 / VCCO_66 | 4) | - | Module bank voltages. | Enable bank voltages after PG_PL deassertion. | 3 | GTH / GTY Transceiver | Procedure for GTH / GTY transceiver starting. | PL transceiver usage needs powered PL and low-power PS domain. | 3.1 | GT_DCDC | 3.3 V (± 5 %) 2) | - | GTH transceiver power supply. | Main module power supply for GTH transceiver. 5 A recommended. Power consumption depends mainly on design and cooling solution. | 3.2 | EN_GT_L / EN_GT_R | 3.3 V | - | GTH / GTY left / right transceiver power enable. | Transceivers on left / right side can be used independently. | 3.3 | PG_GT_L / PG_GT_R | - | PU 3), 3.3VIN | GTH / GTY transceiver power good status. |
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1) (optional) 2) Dependent on the assembly option a higher input voltage may be possible. 3) (on module) 4) See DS925 for additional information. |
Board to Board Connectors
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- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
Include Page |
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| 6 x 6 SoM LSHM B2B Connectors |
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| 6 x 6 SoM LSHM B2B Connectors |
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Include Page |
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| 5.2 x 7.6 UltraSoM+ ADF6 and ADM6 B2B Connectors |
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| 5.2 x 7.6 UltraSoM+ ADF6 and ADM6 B2B Connectors |
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Technical Specifications
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List of all Powerrails which are accessible by the customer - Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)
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Absolute Maximum Ratings *)
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title | Module absolute maximum ratings |
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Power Rail Name/ Schematic Name | Description | Min | Max | Unit |
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LP_DCDC | Micromodule Power | -0.300 | 6.0 | V | DCDCIN | Micromodule Power | -0.300 | 7.0 | V | GT_DCDC | Micromodule Power | -0.300 | 6.0 | V | PL_DCIN | Micromodule Power | -0.300 | 7.0 | V | 3.3VIN | Micromodule Power | -0.300 | 3.600 | V | PLL_3V3 | PLL power supply | -0.500 | 3.8 | V | PS_BATT | RTC / BBRAM | -0.500 | 2.000 | V | VCCO_47 | HD IO Bank power supply | -0.500 | 3.400 | V | VCCO_48 | HD IO Bank power supply | -0.500 | 3.400 | V | VCCO_64 | HP IO Bank power supply | -0.500 | 2.000 | V | VCCO_65 | HP IO Bank power supply | -0.500 | 2.000 | V | VCCO_66 | HP IO Bank power supply | -0.500 | 2.000 | V | VREF_64 | Bank input reference voltage | -0.500 | 2.000 | V | VREF_65 | Bank input reference voltage | -0.500 | 2.000 | V | VREF_66 | Bank input reference voltage | -0.500 | 2.000 | V |
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*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
use "include page" macro and link to the general B2B connector page of the module series,
For example: 6 x 6 SoM LSHM B2B Connectors Include Page |
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PD:6 x 6 SoM LSHM B2B Connectors | PD:6 x 6 SoM LSHM B2B Connectors | Include Page |
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PD:5.2 x 7.6 UltraSoM+ ADF6 and ADM6 B2B Connectors | PD:5.2 x 7.6 UltraSoM+ ADF6 and ADM6 B2B Connectors | Technical Specifications
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List of all Powerrails which are accessible by the customer - Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)
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Absolute Maximum Ratings *)
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anchor | Table_TS_AMR |
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title | Module absolute maximum ratings |
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Power Rail Name/ Schematic Name | Description | Min | Max | Unit |
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LP_DCDC | Micromodule Power | -0.300 | 6.0 | V |
DCDCIN | Micromodule Power | -0.300 | 7.0 | V |
GT_DCDC | Micromodule Power | -0.300 | 6.0 | V |
PL_DCIN | Micromodule Power | -0.300 | 7.0 | V |
3.3VIN | Micromodule Power | -0.300 | 3.600 | V |
PLL_3V3 | PLL power supply | -0.500 | 3.8 | V |
PS_BATT | RTC / BBRAM | -0.500 | 2.000 | V |
VCCO_47 | HD IO Bank power supply | -0.500 | 3.400 | V |
VCCO_48 | HD IO Bank power supply | -0.500 | 3.400 | V |
VCCO_64 | HP IO Bank power supply | -0.500 | 2.000 | V |
VCCO_65 | HP IO Bank power supply | -0.500 | 2.000 | V |
VCCO_66 | HP IO Bank power supply | -0.500 | 2.000 | V |
VREF_64 | Bank input reference voltage | -0.500 | 2.000 | V |
VREF_65 | Bank input reference voltage | -0.500 | 2.000 | V |
VREF_66 | Bank input reference voltage | -0.500 | 2.000 | V |
*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
This TRM is generic for all variants. Temperature range can be differ depending on the assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request).
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
- Variants of modules are described here: Article Number Information
- Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
- Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
- Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
- The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.
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Parameter | Min | Max | Units | Reference Document |
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LP_DCDC 1) | 3.135201 | 3.465399 | V |
| DCDCIN 1) | 3.135 | 3.465 | V |
| GT_DCDC 1) | 3.135201 | 3.465399 | V |
| PL_DCIN 1) | 3.135 | 3.465 | V |
| 3.3VIN | 3.135 | 3.465 | V |
| PLL_3V3 | 3.14201 | 3.465399 | V |
| PS_BATT | 1.200 | 1.500 | V | See FPGA datasheet. | VCCO_47 | 1.140164 | 3.400399 | V | See FPGA datasheet. | VCCO_48 | 1.140164 | 3.400399 | V | See FPGA datasheet. | VCCO_64 | 0.950970 | 1.900854 | V | See FPGA datasheet. | VCCO_65 | 0.950970 | 1.900854 | V | See FPGA datasheet. | VCCO_66 | 0.950970 | 1.900854 | V | See FPGA datasheet. | VREF_64 | 0.6 | 1.2 | V | See FPGA datasheet. | VREF_65 | 0.6 | 1.2 | V | See FPGA datasheet. | VREF_66 | 0.6 | 1.2 | V | See FPGA datasheet. |
1) Higher values may possible. For more information consult schematic and according datasheets. |
Physical Dimensions
PCB thickness: 1.6 mm (± 10 %).
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title | Physical Dimension |
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diagramName | Figure_TS_PD |
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revision | 23 |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-epub | true |
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scroll-html | true |
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Currently Offered Variants
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title-alignment | center |
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title | Trenz Electronic Shop Overview |
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Revision History
Hardware Revision History
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title | Board hardware revision number. |
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diagramWidth | 161 |
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revision | 3 |
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title-alignment | center |
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title | Hardware Revision History |
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Date | Revision | Changes | Documentation Link |
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- | REV02 | REV02 | Date | Revision | Changes | Documentation Link |
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- | REV02 | - Added capacitors C178, C187, C188, C189 (470nF) to VTT net.
- Added U18/ U37 compensation network: R119, C190, C191. R118 is optional jumper and is installed when using the internal compensation network. External compensation network is used by default.
- Connected all DDR4 TEN pins together and pulled them down with resistor R120 and added testpoint TP23.
- Added testpoints TP25, TP27, TP29, TP35, TP37...TP79.
- Changed capacitor C112 size from 0402 to 0201 and voltage rating from 16 V to 10 V.
- Changed ferrid beads from MPZ0603S121HT000 to BLM15PX800SZ1D for L1, L2, L3, L4, L5, and L7.
- Changed ferrid beads from MPZ1608S221A to BLM15PX800SZ1D for L6 and L8.
- Added diode D2 between U41 pin 3 net MR and voltage rail 3.3VIN.
- Modified trace length.
- Updated documentation overviews.
| REV02 |
- | REV01 | First Production Release | REV01 |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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cellHighlighting | true |
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Date | Revision | Contributor | Description |
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infoType | Modified date |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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infoType | Current version |
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prefix | v. |
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type | Flat |
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showVersions | false |
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| - Added power supply PLL_3V3 in table "Recommended Power up Sequencing".
- Fix typo.
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Disclaimer
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| IN:Legal Notices |
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| IN:Legal Notices |
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