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The Trenz Electronic TE0818 is an industrial grade MPSoC SOM integrating a Xilinx Zynq UltraScale+ MPSoC, DDR4 SDRAM with 64-Bit width data bus connection, SPI Boot Flash memory for configuration and operation, transceivers and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking connections in a compact 5.2 cm x 7.6 cm form factor.
Refer to http://trenz.org/te0818-info for the current online version of this manual and other available documentation.
up to 204 PL IO
up to 65 PS MIO
Storage device name | Content | Notes |
---|---|---|
DDR4 SDRAM | not programmed | |
Quad SPI Flash | not programmed | |
EEPROM | not programmed besides factory programmed MAC address | |
Programmable Clock Generator | not programmed |
Connector Type | Designator | Interface | IO CNT | Notes |
---|---|---|---|---|
B2B | JM1 | MGT PL | 12 x MGT (RX/TX) | |
B2B | JM1 | HP | 52 SE / 24 DIFF | |
B2B | JM2 | MGT PS | 2 x MGT CLK | |
B2B | JM2 | CLK | DIFF CLK | |
B2B | JM2 | MGT PL | 4 x MGT (RX/TX) | |
B2B | JM2 | MGT PS | 4 x MGT (RX/TX) | |
B2B | JM2 | CFG | JTAG | |
B2B | JM2 | CFG | MODE | |
B2B | JM3 | HD | 48 SE / 24 DIFF | |
B2B | JM3 | MGT PL | 3 x MGT CLK | |
B2B | JM3 | CLK | DIFF CLK | |
B2B | JM3 | MIO | 65 GPIO | |
B2B | JM4 | HP | 104 SE / 48 DIFF |
Test Point | Signal | Notes |
---|---|---|
TP1 | PLL_SCL | pulled-up to PS_1V8 |
TP2 | PLL_SDA | pulled-up to PS_1V8 |
TP3 | LP_DCDC | |
TP4 | DCDCIN | |
TP5 | GND | |
TP6 | TCK | |
TP7 | PL_DCIN | |
TP8 | GND | |
TP9 | GT_DCDC | |
TP10 | GND | |
TP11 | TDI | |
TP12 | TDO | |
TP13 | TMS | |
TP14 | PS_1V8 | |
TP15 | No Net Name | REF3312AIDCKT (U33) ouput voltage |
TP16 | FP_0V85 | |
TP17 | DDR_2V5 | |
TP18 | DDR_PLL | |
TP19 | PL_VCCINT | |
TP20 | AUX_R | |
TP21 | AVTT_R | |
TP22 | AUX_L | |
TP24 | AVCC_R | |
TP26 | AVTT_L | |
TP28 | AVCC_L | |
TP30 | PS_PLL | |
TP31 | PS_AVTT | |
TP32 | LP_0V85 | |
TP33 | PS_AUX | |
TP34 | PS_AVCC | |
TP36 | POR_B |
Chip/Interface | Designator | Connected To | Notes |
---|---|---|---|
DDR4 SDRAM | U2, U3, U9, U12 | SoC - PS | |
Quad SPI Flash | U7, U17 | SoC - PS | Booting. |
EEPROM | U4 | B2B - J2 | |
Clock Generator | U5 | SoC, B2B | |
Oscillator | U25 | Clock Generator | 25 MHz |
Oscillator | U32 | SoC | 33.333333 MHz |
Connector+Pin | Signal Name | Direction1) | Description |
---|---|---|---|
JM1.A45 | POR_OVERRIDE | IN | Override power-on reset delay 2). |
JM2.A30 | PG_PLL_1V8 | OUT | SI_PLL_1V8 power rail powered-up. |
JM2.A31 | ERR_OUT | OUT | PS error indication 2). |
JM2.A34 | ERR_STATUS | OUT | PS error status 2). |
JM2.A35 | LP_GOOD | OUT | Low-power domain powered-up. Pulled up to 3.3VIN. |
JM2.A36 | PLL_SCL | IN | I2C clock. Pulled up to PS_1V8. |
JM2.A37 | PLL_SDA | IN/OUT | I2C data. Pulled up to PS_1V8. |
JM2.A40 | PG_GT_L | OUT | Left GTH Transceivers powered-up. |
JM2.A41 | EN_PSGT | IN | Enable GTR transceiver power-up. |
JM2.A44 / JM2.A45 / JM2.A46 / JM2.A47 | TCK / TDI / TDO / TMS | Signal-dependent | JTAG configuration and debugging interface. JTAG reference voltage: PS_1V8 |
JM2.B29 | PG_PSGT | OUT | GTR transceivers powered-up. |
JM2.B30 | PROG_B | IN/OUT | Power-on reset 2). Pulled-up to PS_1V8. |
JM2.B33 | SRST_B | IN | System reset 2). Pulled-up to PS_1V8. |
JM2.B34 | INIT_B | IN/OUT | Initialization completion indicator after POR 2). Pulled-up to PS_1V8. |
JM2.B37 | PG_PL | OUT | Programmable logic powered-up. |
JM2.B38 | EN_FPD | IN | Enable full-power domain power-up. |
JM2.B41 | PG_FPD | OUT | Full-power domain powered-up. |
JM2.B42 | EN_LPD | IN | Enable low-power domain power-up. |
JM2.B45 | PG_DDR | OUT | DDR power supply powered-up. |
JM2.B46 | DONE | OUT | PS done signal 2). Pulled-up to PS_1V8. |
JM2.B47 | EN_DDR | IN | Enable DDR power-up. |
JM2.C30 | EN_GT_L | IN | Enable left GTH transceiver power-up. |
JM2.C31 | MR | IN | Manual reset. |
JM2.C32 | PLL_SEL0 | IN | PLL clock selection. |
JM2.C33 | PLL_RST | IN | PLL reset. Pulled-up to PS_1V8. |
JM2.C35 | EN_PL | IN | Enable programable logic power-up. |
JM2.C36 | EN_GT_R | IN | Enable right GTH transceiver power-up. |
JM2.C37 | PLL_FDEC | IN | PLL Frequency decrementation. |
JM2.C44 / JM2.C45 / JM2.C46 / JM2.C47 | MODE3..0 | IN | Boot mode selection 2):
Supported Modes depends also on used Carrier. |
JM2.D29 | EN_PLL_PWR | IN | Enable PLL power supply. |
JM2.D30 | PLL_FINC | IN | PLL Frequency incrementation. |
JM2.D31 | PLL_LOLn | OUT | Loss of lock status. |
JM2.D32 | PLL_SEL1 | IN | PLL clock selection. |
JM2.D33 | PG_GT_R | OUT | Right GTH Transceivers powered-up. |
JM2.D37 | PSBATT | IN | PS RTC Battery supply voltage 2) 3). |
JM2.D38 | PUDC_B | IN | Configuration pull-ups setting 2). Pulled-up to PL_1V8. |
JM2.D45 / JM2.D46 | DX_P / DX_N | - | SoC temperatur sensing diode pins 2). |
1) Direction:
2) See UG1085 for additional information.
3) See Recommended Operating Conditions.
Power Rail Name/ Schematic Name | Connector + Pin | Direction1) | Notes |
---|---|---|---|
VCCO_66 | JM1.A32 / JM1.A33 | IN | |
VREF_66 | JM1.A41 | IN | |
3.3VIN | JM1.A54 / JM1.A55 / JM1.B55 / JM1.B56 | IN | |
PL_1V8 | JM1.C32 / JM1.C33 / JM1.D33 / JM1.D34 | OUT | |
PL_DCIN | JM1.C56 / JM1.C57 / JM1.C58 / JM1.C59 / JM1.C60 / JM1.D56 / JM1.D57 / JM1.D58 / JM1.D59 / JM1.D60 | IN | |
LP_DCDC | JM2.A50 / JM2.A51 / JM2.A52 / JM2.B50 / JM2.B51 / JM2.B52 / JM2.C50 / JM2.C51 / JM2.C52 / JM2.D50 / JM2.D51 / JM2.D52 | IN | |
DCDCIN | JM2.A57 / JM2.A58 / JM2.A59 / JM2.A60 / JM2.B57 / JM2.B58 / JM2.B59 / JM2.B60 / JM2.C57 / JM2.C58 / JM2.C59 / JM2.C60 / JM2.D57 / JM2.D58 / JM2.D59 / JM2.D60 / | IN | |
PS_BATT | JM2.D37 | IN | |
DDR_1V2 | JM2.D47 | OUT | |
PS_1V8 | JM2.C34 / JM2.D34 / JM3.A56 / JM3.B56 / JM3.C56 / JM3.D56 | OUT | |
PLL_3V3 | JM3.A55 | IN | |
GT_DCDC | JM3.A59 / JM3.A60 / JM3.B59 / JM3.B60 / JM3.C59 / JM3.C60 / JM3.D59 / JM3.D60 / | IN | |
VCCO_48 | JM3.C7 / JM3.C8 / JM3.D8 / JM3.D9 | IN | |
VCCO_47 | JM3.C19 / JM3.C20 / JM3.D20 / JM3.D21 | IN | |
VCCO_64 | JM4.B21 / JM4.B39 | IN | |
VREF_64 | JM4.B30 | IN | |
VCCO_65 | JM4.C21 / JM4.C39 | IN | |
VREF_65 | JM4.C30 | IN |
1) Direction:
The power up sequencing highly depends on the use case. In general, it should be possible to enable/disable the processing system (PS) / programmable logic (PL) independently. Furthermore, within the processing logic it should be possible to enable/disable only low-power domain and/or low-power and full-power domain. Additionally, usage of GTR for PS side and GTH for PL side should be possible. GTH transceivers on left and right side are usable independently. Because of this flexibility the needed parts of the following table needs to be selected individually. For detailed information take a look into schematics.
Sequence | Net name | Recommended Voltage Range | Pull-up/down | Description | Notes |
---|---|---|---|---|---|
0 | - | - | - | Configuration signal setup. | See Configuration and System Control Signals. |
1 1) | PSBATT | 1.2 V ... 1.5 V | - | Battery connection. | Battery Power Domain usage. When not used, tie to GND. |
1 | 3.3VIN | 3.3 V (± 5 %) | - | Management power supply. | Management module power supply. 0.5 A recommended. |
GTH / GTR Transceiver clocking (Only necessary in cases where the PLL clock is used for GTH / GTH.): | |||||
1 1) | GT_DCDC | 3.3 V (± 5 %) 2) | GTH transceiver power supply. | Main module power supply for GTH / GTY transceiver. 5 A recommended. Power consumption depends mainly on design and cooling solution. | |
1 1) | EN_PLL_PWR | - | PU 3), 3.3VIN | PLL power enable. | |
1 1) | PG_PLL_1V8 | - | PU 3), 3.3VIN | PLL power good status. | |
2 | Processing System (PS): | Procedure for PS starting. | |||
2.1 | Low-power domain: | Bring-up for low-power domain PS. | |||
2.1.1 | LP_DCDC | 3.3 V (± 5 %) 2) | - | Low-power domain power supply. | Main module power supply for low-power domain. 5.5 A recommended. Power consumption depends mainly on design and cooling solution. |
2.1.2 | EN_LPD | - | PU 3), 3.3VIN | Low-power domain power enable. | |
2.1.3 | LP_GOOD | - | PU 3), 3.3VIN | Low-power domain power good status. | Module power-on sequencing for low-power domain finished. |
2.2 | Full-power domain: | Bring-up for full-power domain PS. | Full-power PS domain needs powered low-power PS domain. | ||
2.2.1 | DCDCIN | 3.3 V (± 5 %) 2) | Full-power domain and GTR transceiver power supply. | Main module power supply for full-power domain. 7 A recommended. Power consumption depends mainly on design and cooling solution. | |
2.2.2 | EN_FPD | 3.3 V | - | Full-power domain power enable. | |
2.2.3 | PG_FPD | - | PU 3), 3.3VIN | Full-power domain power good status. | Module power-on sequencing for full-power domain finished. |
2.2.4 | EN_DDR | 3.3 V | - | DDR memory power enable. | |
2.2.5 | PG_DDR | PU 3), 3.3VIN | DDR memory power good status. | Module power-on sequencing for DDR memory finished. | |
2.3 | GTR Transceiver | Procedure for GTR transceiver starting. | PS transceiver usage needs powered PS (low- and full-power domain). | ||
2.3.1 | EN_PSGT | 3.3 V | - | GTR transceiver power enable. | |
2.3.2 | PG_PSGT | - | PU 3), 3.3VIN | GTR transceiver power good status. | Module power-on sequencing for GTR transceiver finished. |
2 | Programmable Logic (PL) | Procedure for PL starting. | PS and PL can be started independently. | ||
2.1 | PL_DCIN | 3.3 V (± 5 %) 2) | - | Programmable logic power supply. | Main module power supply for programmable logic. 12 A recommended. Power consumption depends mainly on design and cooling solution. |
2.2 | EN_PL | - | PU 3), 3.3VIN | Programmable logic power enable. | |
2.3 | PG_PL | - | PU 3), 3.3VIN | Programmable logic power good status. | Module power-on sequencing for programmable logic finished. Periphery and variable bank voltages can be enabled on carrier. |
2.4 | VCCO_47 / VCCO_48 / VCCO_64 / VCCO_65 / VCCO_66 | 4) | - | Module bank voltages. | Enable bank voltages after PG_PL deassertion. |
3 | GTH / GTY Transceiver | Procedure for GTH / GTY transceiver starting. | PL transceiver usage needs powered PL and low-power PS domain. | ||
3.1 | GT_DCDC | 3.3 V (± 5 %) 2) | - | GTH transceiver power supply. | Main module power supply for GTH transceiver. 5 A recommended. Power consumption depends mainly on design and cooling solution. |
3.2 | EN_GT_L / EN_GT_R | 3.3 V | - | GTH / GTY left / right transceiver power enable. | Transceivers on left / right side can be used independently. |
3.3 | PG_GT_L / PG_GT_R | - | PU 3), 3.3VIN | GTH / GTY transceiver power good status. |
1) (optional)
2) Dependent on the assembly option a higher input voltage may be possible.
3) (on module)
4) See DS925 for additional information.
5.2 x 7.6 cm UltraSoM+ carrier use four Samtec AcceleRate HD High-Density Slim Body Arrays on top side.
When using the standard type on baseboard and module, the mating height is 5 mm.
Other mating heights are possible by using connectors with a different height:
Order number | REF number | Samtec Number | Type | Contribution to stacking height | Comment |
---|---|---|---|---|---|
30095 | REF-30095 | ADM6-60-01.5-L-4-2 | Module connector | 1.5 mm | Standard connector used on modules |
31137 | REF-31137 | ADF6-60-03.5-L-4-2 | Baseboard connector | 3.5 mm | Standard connector used on carrier |
The AcceleRate HD High-Density connector speed rating depends on the stacking height; please see the following table:
Stacking height | Speed rating |
---|---|
5 mm | 56 Gbps |
Current rating of Samtec AcceleRate HD High-Density B2B connectors is 1.34 A per pin (4 pins powered)
File | Modified | |
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PDF File 20200225_hsc_adm6-xx-01p5-xxx-4-a_adf6-xx-03p5-xxx-4-a.pdf | 10 01, 2022 by Martin Rohrmüller | |
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PDF File adf6.pdf | 10 01, 2022 by Martin Rohrmüller | |
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PDF File ADF6-XXX-XX.X-XXX-X-X-X-FOOTPRINT.PDF | 10 01, 2022 by Martin Rohrmüller | |
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PDF File adf6-xxx-xx.x-xxx-x-x-x-xr-mkt.pdf | 10 01, 2022 by Martin Rohrmüller | |
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PDF File adx6 mated document.pdf | 10 01, 2022 by Martin Rohrmüller | |
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Power Rail Name/ Schematic Name | Description | Min | Max | Unit |
---|---|---|---|---|
LP_DCDC | Micromodule Power | -0.300 | 6.0 | V |
DCDCIN | Micromodule Power | -0.300 | 7.0 | V |
GT_DCDC | Micromodule Power | -0.300 | 6.0 | V |
PL_DCIN | Micromodule Power | -0.300 | 7.0 | V |
3.3VIN | Micromodule Power | -0.300 | 3.600 | V |
PLL_3V3 | PLL power supply | -0.500 | 3.8 | V |
PS_BATT | RTC / BBRAM | -0.500 | 2.000 | V |
VCCO_47 | HD IO Bank power supply | -0.500 | 3.400 | V |
VCCO_48 | HD IO Bank power supply | -0.500 | 3.400 | V |
VCCO_64 | HP IO Bank power supply | -0.500 | 2.000 | V |
VCCO_65 | HP IO Bank power supply | -0.500 | 2.000 | V |
VCCO_66 | HP IO Bank power supply | -0.500 | 2.000 | V |
VREF_64 | Bank input reference voltage | -0.500 | 2.000 | V |
VREF_65 | Bank input reference voltage | -0.500 | 2.000 | V |
VREF_66 | Bank input reference voltage | -0.500 | 2.000 | V |
*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
This TRM is generic for all variants. Temperature range can be differ depending on the assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request).
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
LP_DCDC 1) | 3.135 | 3.465 | V | |
DCDCIN 1) | 3.135 | 3.465 | V | |
GT_DCDC 1) | 3.135 | 3.465 | V | |
PL_DCIN 1) | 3.135 | 3.465 | V | |
3.3VIN | 3.135 | 3.465 | V | |
PLL_3V3 | 3.14 | 3.465 | V | |
PS_BATT | 1.200 | 1.500 | V | See FPGA datasheet. |
VCCO_47 | 1.140 | 3.400 | V | See FPGA datasheet. |
VCCO_48 | 1.140 | 3.400 | V | See FPGA datasheet. |
VCCO_64 | 0.950 | 1.900 | V | See FPGA datasheet. |
VCCO_65 | 0.950 | 1.900 | V | See FPGA datasheet. |
VCCO_66 | 0.950 | 1.900 | V | See FPGA datasheet. |
VREF_64 | 0.6 | 1.2 | V | See FPGA datasheet. |
VREF_65 | 0.6 | 1.2 | V | See FPGA datasheet. |
VREF_66 | 0.6 | 1.2 | V | See FPGA datasheet. |
1) Higher values may possible. For more information consult schematic and according datasheets.
Module size: 76 mm × 52 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 5 mm.
PCB thickness: 1.6 mm (± 10 %).
Trenz shop TE0818 overview page | |
---|---|
English page | German page |
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Date | Revision | Contributor | Description |
---|---|---|---|
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The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.
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Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.
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