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  • Firmware
  • Power Management
  • JTAG routing
  • Boot Mode
  • User IO
  • LED

Firmware Revision and supported PCB Revision

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Name / opt. VHD NameDirectionPinBank PowerDescription
PWR_STATUSout361.8V_CPLDOutput for Status-LED (After successful configuration of FPGA is connected automatically with FPGA_IO0)
MODE0out351.8V_CPLDZynqMP boot mode pin 0
PG_VCCRFin341.8V_CPLDPower Good input from PWR_PRE
SRST_Bout331.8V_CPLDFPGA external system reset  / currently_not_used
PROG_Bout321.8V_CPLDFPGA reset PL configuration logic / currently_not_used
PG_GR2in311.8V_CPLDPower control input from PWR_PS and PWR_DDR
MIO28_UART1_TXout291.8V_CPLDUART Transmition pin / currently_not_used
MIO28_UART1_RXin281.8V_CPLDUART Receive pin / currently_not_used
FPGA_IO0out271.8V_CPLDFPGA GPIO  / User LED
FPGA_IO1ininout261.8V_CPLDFPGA GPIO / User dip switch interface
EN_PS_PLout143.3V_CPLDPower enable for PWR_CORE , PWR_PS and PWR_GT
EN_GR1out153.3V_CPLDPower enable for PWR_GT and PWR_PS
EN_RF_ADCout163.3V_CPLDPower enable for PWR_ADC
PG_RF_DACin173.3V_CPLDPower control input from PWR_DAC
EN_VCCRFout183.3V_CPLDPower enable for PWR_PRE
EN_GR2out193.3V_CPLDPower enable for PWR_DDR , PWR_GT and PWR_PS
PG_PS_PLin203.3V_CPLDpower control input from PWR_CORE , PWR_GT and PWR_PS
PG_GR1in213.3V_CPLDPower control input from PWR_GT and PWR_PS
PG_RF_ADCin233.3V_CPLDPower control input from PWR_ADC
EN_RF_DACout243.3V_CPLDPower enable for PWR_DAC
MODE2out21.8V_CPLDZynqMP boot mode pin 2
MODE1out31.8V_CPLDZynqMP boot mode pin 1
POR_Bout41.8V_CPLDPower-On reset signal
MODE3out51.8V_CPLDZynqMP boot mode pin 3
INIT_Bin71.8V_CPLDFPGA PL initialization activity and configuration error signal / currently_not_used
F_TDIout81.8V_CPLDJTAG ZynqMP
F_TMSout91.8V_CPLDJTAG ZynqMP
F_TCKout101.8V_CPLDJTAG ZynqMP
F_TDOin111.8V_CPLDJTAG ZynqMP
DONEin121.8V_CPLDFPGA PL configuration done indicator
JTAG_TDOout483.3V_CPLDJTAG_B2B
JTAG_TDIin473.3V_CPLDJTAG_B2B
JTAG_TCKin453.3V_CPLDJTAG_B2B
JTAG_TMSin443.3V_CPLDJTAG_B2B
CPLD_IO0in433.3V_CPLDBOOT Mode input pin 0
CPLD_IO1in423.3V_CPLDBOOT Mode input pin 1
CPLD_JTAGENin413.3V_CPLDEnable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access)
CPLD_IO2inoutin403.3V_CPLDCPLD IO to B2B / Used as dip switch interface on the carrier board (After successful configuration of  FPGA is connected automatically with FPGA_IO1)
CPLD_IO3inoutout383.3V_CPLDCPLD IO to B2B/ Used as power good, can be used to enable carrier periphery power
RESETNin373.3V_CPLDReset pin of CPLD (Active low)

Firmware

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Functional Description

JTAG

JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on B2B. In the carrier board TEB0835 can be activated this pin with S1-4 dip switch.

CPLD_JTAGEN (B2B J1-30)S1-4 on TEB0835 Carrier BoardDescription
0OFFFPGA access
1ONCPLD access

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StatesBlink SequenceComment
IDLEooooooooooooooooooo*Power Sequencing can not start. RESETN is active.
Stage 1ooooooooooooooooo*o*The correct voltage in one of the following nets are failed: VCCINT, VCINT_IO, VCCBRAM, PSINTLP, PSINTFP, PSINTFP_DDR, MGTAVCC
Stage 2ooooooooooooooo*o*o*The correct voltage in one of the following nets are failed: PSAUX, PSADC, PSIO, VCCAUX, VCCAUX_IO, PS_DDR_PLL, PSMGTRAVCC, MGTVCCAUX, PSPLL, MGTAVTT
Stage 3ooooooooooooo*o*o*o*The correct voltage in one of the following nets are failed: VCC_B88_HD, PS_MGTRAVTT, DDR_2V5 , DDR_1V2
Stage 4ooooooooooo*o*o*o*o*The correct voltage in one of the following nets are failed: VCCINT_AMS, APRE_1V15, APRE_3V3
Stage 5ooooooooo*o*o*o*o*o*The correct voltage in one of the following nets are failed: ADC_AVCC, ADC_AVCCAUX, DAC_AVCC, DAC_AVCCAUX, DAC_AVTT
WAIT_RDY / RDY and DONE='0'ooooooo*o*o*o*o*o*o*Power is ok. But the FPGA is not yet configured.
pg_all = '0'ooooo*o*o*o*o*o*o*o*An error occuresunknown error has occurred. The power supply must be switched off.
USR (RDY and DONE='1')User definedPower is ok and the FPGA is configured successfully. LED can be controlled by user, when Power is OK and FPGA part is programmed (DONE signal is high)
  • The period for erery blink (*o) is 0.5sec.

User IO

  • FPGA_IO1 (AE16 of RFSoC) is connected with CPLD_IO2 (S1-3 Dip switch on the carrier board) when the FPGA is programmed correctly otherweise this pin is high impedance. After configuration of the FPGA can user use this pin as input.
  • FPGA_IO0 (AE18 of RFSOC) is connected with LED on the RFSoC module  (D1) if the FPGA is programmed completely otherweise this LED (D1) blinks according to the state of the power-on sequencing. After configuration of the FPGA can be controlled this LED (D1) by user.

If the FPGA correctly programmed (DONE signal is high) and  the power-on sequencing state is RDY then the User IOs can be shown in the following table:

FunctionInterfaceSchematicFPGA PinNote
USER signalB2B (J1-32)FPGA_IO1AE16source by  TEB0835 Dip Switch S1-3, in case FPGA is programmed
LED (D1)--FPGA_IO0AE18controls LED, in case FPGA is programmed

Boot Mode

Boot Modes can be selected via B2B Pin Mode.

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  • REV00 to REV01
    • transfer verilog to vhdl
    • power stagemachine, add power down cyclus on error state
    • bugfix: Power Good(CPLD_IO3) depends now on module power sequencing
    • LED status changed
    • LED controllable by USR after power up
    • CPLD_IO2 connected to FPGA IO (can be controlled by user)
    • constrains and buffer changes for JTAG

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

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modified-date
modified-date
dateFormatyyyy-MM-dd

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current-version
current-version
prefixv.

REV01REV02, REV01

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modified-user

  • REV01 release (firmware release 2020-10-27)
2020-08-18v.4REV00REV01 Ivan Girshchenko / Mohsen Chamanbaz
  • REV00 release (firmware release 2019-12-18)

All

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modified-users
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