Page History
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- Firmware
- Power Management
- JTAG routing
- Boot Mode
- User IO
- LED
Firmware Revision and supported PCB Revision
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| Name / opt. VHD Name | Direction | Pin | Bank Power | Description |
|---|---|---|---|---|
| PWR_STATUS | out | 36 | 1.8V_CPLD | Output for Status-LED (After successful configuration of FPGA is connected automatically with FPGA_IO0) |
| MODE0 | out | 35 | 1.8V_CPLD | ZynqMP boot mode pin 0 |
| PG_VCCRF | in | 34 | 1.8V_CPLD | Power Good input from PWR_PRE |
| SRST_B | out | 33 | 1.8V_CPLD | FPGA external system reset / currently_not_used |
| PROG_B | out | 32 | 1.8V_CPLD | FPGA reset PL configuration logic / currently_not_used |
| PG_GR2 | in | 31 | 1.8V_CPLD | Power control input from PWR_PS and PWR_DDR |
| MIO28_UART1_TX | out | 29 | 1.8V_CPLD | UART Transmition pin / currently_not_used |
| MIO28_UART1_RX | in | 28 | 1.8V_CPLD | UART Receive pin / currently_not_used |
| FPGA_IO0 | out | 27 | 1.8V_CPLD | FPGA GPIO / User LED |
| FPGA_IO1 | ininout | 26 | 1.8V_CPLD | FPGA GPIO / User dip switch interface |
| EN_PS_PL | out | 14 | 3.3V_CPLD | Power enable for PWR_CORE , PWR_PS and PWR_GT |
| EN_GR1 | out | 15 | 3.3V_CPLD | Power enable for PWR_GT and PWR_PS |
| EN_RF_ADC | out | 16 | 3.3V_CPLD | Power enable for PWR_ADC |
| PG_RF_DAC | in | 17 | 3.3V_CPLD | Power control input from PWR_DAC |
| EN_VCCRF | out | 18 | 3.3V_CPLD | Power enable for PWR_PRE |
| EN_GR2 | out | 19 | 3.3V_CPLD | Power enable for PWR_DDR , PWR_GT and PWR_PS |
| PG_PS_PL | in | 20 | 3.3V_CPLD | power control input from PWR_CORE , PWR_GT and PWR_PS |
| PG_GR1 | in | 21 | 3.3V_CPLD | Power control input from PWR_GT and PWR_PS |
| PG_RF_ADC | in | 23 | 3.3V_CPLD | Power control input from PWR_ADC |
| EN_RF_DAC | out | 24 | 3.3V_CPLD | Power enable for PWR_DAC |
| MODE2 | out | 2 | 1.8V_CPLD | ZynqMP boot mode pin 2 |
| MODE1 | out | 3 | 1.8V_CPLD | ZynqMP boot mode pin 1 |
| POR_B | out | 4 | 1.8V_CPLD | Power-On reset signal |
| MODE3 | out | 5 | 1.8V_CPLD | ZynqMP boot mode pin 3 |
| INIT_B | in | 7 | 1.8V_CPLD | FPGA PL initialization activity and configuration error signal / currently_not_used |
| F_TDI | out | 8 | 1.8V_CPLD | JTAG ZynqMP |
| F_TMS | out | 9 | 1.8V_CPLD | JTAG ZynqMP |
| F_TCK | out | 10 | 1.8V_CPLD | JTAG ZynqMP |
| F_TDO | in | 11 | 1.8V_CPLD | JTAG ZynqMP |
| DONE | in | 12 | 1.8V_CPLD | FPGA PL configuration done indicator |
| JTAG_TDO | out | 48 | 3.3V_CPLD | JTAG_B2B |
| JTAG_TDI | in | 47 | 3.3V_CPLD | JTAG_B2B |
| JTAG_TCK | in | 45 | 3.3V_CPLD | JTAG_B2B |
| JTAG_TMS | in | 44 | 3.3V_CPLD | JTAG_B2B |
| CPLD_IO0 | in | 43 | 3.3V_CPLD | BOOT Mode input pin 0 |
| CPLD_IO1 | in | 42 | 3.3V_CPLD | BOOT Mode input pin 1 |
| CPLD_JTAGEN | in | 41 | 3.3V_CPLD | Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access) |
| CPLD_IO2 | inoutin | 40 | 3.3V_CPLD | CPLD IO to B2B / Used as dip switch interface on the carrier board (After successful configuration of FPGA is connected automatically with FPGA_IO1) |
| CPLD_IO3 | inoutout | 38 | 3.3V_CPLD | CPLD IO to B2B/ Used as power good, can be used to enable carrier periphery power |
| RESETN | in | 37 | 3.3V_CPLD | Reset pin of CPLD (Active low) |
Firmware
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Functional Description
JTAG
JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on B2B. In the carrier board TEB0835 can be activated this pin with S1-4 dip switch.
| CPLD_JTAGEN (B2B J1-30) | S1-4 on TEB0835 Carrier Board | Description |
|---|---|---|
| 0 | OFF | FPGA access |
| 1 | ON | CPLD access |
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| States | Blink Sequence | Comment |
|---|---|---|
| IDLE | ooooooooooooooooooo* | Power Sequencing can not start. RESETN is active. |
| Stage 1 | ooooooooooooooooo*o* | The correct voltage in one of the following nets are failed: VCCINT, VCINT_IO, VCCBRAM, PSINTLP, PSINTFP, PSINTFP_DDR, MGTAVCC |
| Stage 2 | ooooooooooooooo*o*o* | The correct voltage in one of the following nets are failed: PSAUX, PSADC, PSIO, VCCAUX, VCCAUX_IO, PS_DDR_PLL, PSMGTRAVCC, MGTVCCAUX, PSPLL, MGTAVTT |
| Stage 3 | ooooooooooooo*o*o*o* | The correct voltage in one of the following nets are failed: VCC_B88_HD, PS_MGTRAVTT, DDR_2V5 , DDR_1V2 |
| Stage 4 | ooooooooooo*o*o*o*o* | The correct voltage in one of the following nets are failed: VCCINT_AMS, APRE_1V15, APRE_3V3 |
| Stage 5 | ooooooooo*o*o*o*o*o* | The correct voltage in one of the following nets are failed: ADC_AVCC, ADC_AVCCAUX, DAC_AVCC, DAC_AVCCAUX, DAC_AVTT |
| WAIT_RDY / RDY and DONE='0' | ooooooo*o*o*o*o*o*o* | Power is ok. But the FPGA is not yet configured. |
| pg_all = '0' | ooooo*o*o*o*o*o*o*o* | An error occuresunknown error has occurred. The power supply must be switched off. |
| USR (RDY and DONE='1') | User defined | Power is ok and the FPGA is configured successfully. LED can be controlled by user, when Power is OK and FPGA part is programmed (DONE signal is high) |
- The period for erery blink (*o) is 0.5sec.
User IO
- FPGA_IO1 (AE16 of RFSoC) is connected with CPLD_IO2 (S1-3 Dip switch on the carrier board) when the FPGA is programmed correctly otherweise this pin is high impedance. After configuration of the FPGA can user use this pin as input.
- FPGA_IO0 (AE18 of RFSOC) is connected with LED on the RFSoC module (D1) if the FPGA is programmed completely otherweise this LED (D1) blinks according to the state of the power-on sequencing. After configuration of the FPGA can be controlled this LED (D1) by user.
If the FPGA correctly programmed (DONE signal is high) and the power-on sequencing state is RDY then the User IOs can be shown in the following table:
| Function | Interface | Schematic | FPGA Pin | Note |
|---|---|---|---|---|
| USER signal | B2B (J1-32) | FPGA_IO1 | AE16 | source by TEB0835 Dip Switch S1-3, in case FPGA is programmed |
| LED (D1) | -- | FPGA_IO0 | AE18 | controls LED, in case FPGA is programmed |
Boot Mode
Boot Modes can be selected via B2B Pin Mode.
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- REV00 to REV01
- transfer verilog to vhdl
- power stagemachine, add power down cyclus on error state
- bugfix: Power Good(CPLD_IO3) depends now on module power sequencing
- LED status changed
- LED controllable by USR after power up
- CPLD_IO2 connected to FPGA IO (can be controlled by user)
- constrains and buffer changes for JTAG
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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| Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
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| REV01 | REV02, REV01 |
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| 2020-08-18 | v.4 | REV00 | REV01 | Ivan Girshchenko / Mohsen Chamanbaz |
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| All |
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