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Refer to httpshttp://wiki.trenz-electronic.de/display/PD/<name>org/te0724-info for the current online version of this manual and other available documentation. |
The Trenz Electronic TE0724 is an industrial-grade SoC module based on Xilinx Zynq - 7010/7020, which provides a dual core ARM Cortex A9 and a 7-series FPGA logic. It provides a gigabit ethernet transceiver, 1GByte 1 GByte of DDR3L SDRAM, 32 64 MByte Flash memory as configration and data storage. it It includes strong pwerregulators power regulators for all needed voltages and a robust high-speed connector for in- and outputs. It has a 6 x 4 cm form factor.
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Additional assembly options are available for cost or performance optimization upon request.
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Storage device name | Content | Notes |
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Spansion ISSI SPI Flash S25FL256IS25LP512M, U13 | Empty | |
DA9062, U4 | Programmed | |
Microchip 24AA128T, U10 | Empty | USER EEPROM |
Microchip 24AA025E48T, U23 | MAC write protected preprogrammed, User area empty | EEPROM for MAC-Address. |
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Boot mode is selected via two Mode pins at B2B connector J2. By default the TE0724 supports JTAG and SPI Boot Mode. Connecting a SD Card via B2B connector to MIO Pins (See SD Card Interface) gives the possibility to boot from SD Card. The Mode pins are pulled up at the module.
Boot mode | MODE1 J1-2 | MODE0 J1-4 |
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JTAG (cascade) | LOW | LOW |
invalid | LOW | HIGH |
SPI | HIGH | LOW |
SD CARD (not on module) | HIGH | HIGH |
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All PS MIO banks as well as PL bank 34 are powered by on-module DC-DC power rails. Valid VCCO_35 for PL bank 35 should be supplied from via the carrier boardB2B connector.
For detailed information about the pin out, please refer to the Pin-out Tables.
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PHY Pin | PL bank 34 | B2B | Notes |
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TX/RX | IO_L1P/IO_L1N | - | |
CAN_L / CAN_H | - | J1-1 / J1-3 |
Table 8: CAN PHY connections.
On-board I2C devices are connected to PS MIO28 (SCL) and MIO29 (SDA). I2C addresses for on-board devices are listed in the table below:
I2C Device | 7bit I2C Address | Notes |
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MAC EEPROM, U23 | 0x53 | 1.8V |
USER EEPROM, U10 | 0x50 | 1.8V |
Power Management U4 | 0x58 / 0x59 | 3.3V |
J1 | - | J1-142 SDA, J1-144 SDL at 3.3V |
Table x9: I2C slave device addresses.
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The Power Management power management IC (U4) is provided by dialog Semiconductors (DA9062). It controls the power-on sequencing of the various power rails. It is preprogrammed and accessible via I2C address 0x58 / 0x59. For a detailed description of the configurable power management IC please refer to the datasheet of dialog semicondutor DA9062.
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On-board QSPI flash memory (U13) on the TE0724-02 04 is a SPANSION S25FL256S ISSI IS25LP512M with 256 512 Mbit (32 64 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
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A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I2C bus with slave device address 0x53.
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Max. I2C Speed for 24AA025E48 EEPROM is 100kHz. |
A Microchip 24AA128T serial EEPROM (U10) is availabe available for e.g. module idetification identification and user Data. The device has 128Kbit memory with max 64 bytes page write capability. It is accessible over I2C bus with slave device address 0x50.
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Max. I2C Speed for 24AA128T EEPROM is 100kHz. |
The module has following reference clock signals provided by on-board oscillators and external source from carrier board:
Clock Source | Schematic Signal | Frequency | Clock Destination |
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SiTime SiT8008BI oscillator, U9 | ETH_XTAL | 25.000000 MHz | XTAL_IN, U7 ETH PHY |
SiTime SiT8008AI oscillator, U6 | PS_CLK | 33.333333 MHz | PS_CLK_500, Bank 500 |
Table Table10 : Reference clock signals.
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LED | Color | Connected to | Description and Notes |
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D1 | Green | PS MIO7 | User LED. |
D2 | Green | PL IO_L3P_T0_34 | User LED. |
D3 | Red | PL IO_L4N_T0_34 | User LED. |
Table 11: On-board LEDs.
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The maximum power consumption of a module mainly depends on the design running on the FPGA.
Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.
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Optional assembled Pin Header J2 can be used for PMIC In-System Programming.
Pin | Signal | B2B |
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J2-1 | VIN | J1-154, J1-156, J1-158, J1-160 |
J2-2 | GND | |
J2-3 | I2C_SCL | J1-142 |
J2-4 | I2C_SDA | J1-144 |
J2-5 | ONKEY | J1-148 |
J2-6 | PWR_TP | J1-146 |
Table 12: Optional assembled Pin Header.
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The maximum power consumption of a module mainly depends on the design running on the FPGA.
Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.
Power Input | Typical Current |
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VIN | TBD* |
Table 13: Typical power consumption.
* TBD - To Be Determined soon with reference design setup.
Power supply with minimum current capability of ...A for system startup is recommended.
The on-board voltages of the TE0724 SoC module will be powered-up in order of a determined sequence after the external voltages VIN is available and nONKEY is asserted.
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To avoid any damage to the module, check for stabilized on-board voltages should be |
Table : Typical power consumption.
* TBD - To Be Determined soon with reference design setup.
Power supply with minimum current capability of ...A for system startup is recommended.
For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.
The on-board voltages of the TE0724 SoC module will be powered-up in order of a determined sequence after the external voltages '...', '...' and '...' are available.
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To avoid any damage to the module, check for stabilized on-board voltages should be carried out (i.e. power good and enable signals) before powering up any SoC's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence. |
Figure : Module power distribution diagram.
See Xilinx data sheet ... for additional information. User should also check related base board documentation when intending base board design for TE07xx module.
The TE07xx SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.
Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:
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Figure : Module power-on diagram.
If the module has one, describe it here...
NB! Following table with examples is valid for most of the 4 x 5 cm modules but depending on the module model and specific design, number and names of power rails connected to the B2B connectors may vary.
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Power Rail Name
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B2B JM1 Pins
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B2B JM2 Pins
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Direction
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VBAT_IN
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Table : Module power rails.
Different modules (not just 4 x 5 cm ones) have different type of connectors with different specifications. Following note is for Samtec Razor Beam™ LSHM connectors only, but we should consider adding such note into included file in Board to Board Connectors section instead of here.
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Current rating of Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered). |
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Bank
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Voltage
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Voltage Range
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DCDC U8 component is either TPS82140 (2 A) or MUN12A (3 A) depending on the variant.
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See Xilinx data sheet for additional information. User should also check related base board documentation when intending base board design for TE0724 module.
The TE0724 SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages. For a detailed description of the configurable Power Management IC please refer to the datasheet of dialog semicondutor DA9062.
Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in ascending order as listed in the blocks of the diagram:
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Power Rail Name | B2B JM1 Pins | Direction | Notes |
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VIN | 154, 156, 158,160 | Input | Main supply voltage from the carrier board. |
VCCIO_35 | 54 | Input | PL Bank 35 supply voltage. |
VLDO1 | 83 | Output | 3.3V (100mA) |
VLDO2 | 94 | Output | 1.8V (300mA) |
VLDO34 | 53 | Output | 2.5V (600mA) |
3.3V | 43, 74 | Output | Additional module on-board 3.3V voltage supply (2 A or 3 A variant dependent). |
1.0V | - | Buck1 & Buck2 of U4. | |
1.8V | 63 | Output | Buck3 of U4. |
VDD_DDR | - | DDR supply voltage powered by Buck4 of U4. | |
VBAT | 152 | Output/Input | Battery charger (out) and supply for RTC and 32kHz crystal (in). |
Table 14: Module power rails.
Current rating of theSamtec connector is 1.6A per pin (1 pin powered per row).
Bank | Schematic Name | Voltage | Voltage Range |
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500 MIO | 3.3V | 3.3V | - |
501 MIO | 1.8V | 1.8V | - |
502 DDR3 | VDD_DDRV | 1.35V | - |
34 HR | 3.3V | 3.3V | - |
35 HR | VCCIO_35 | User | 1.2V to 3.3V |
Table 15: Module PL I/O bank voltages.
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Trenz shop TE0724 overview page | |
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English page | German page |
Parameter | Min | Max | Units | Reference Document |
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VIN supply voltage | -0.3 | 5.5 | V | da9062_3v4.pdf |
Storage temperature | -40 | 85 | °C | - |
Table 18: Module absolute maximum ratings.
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Assembly variants for higher storage temperature range are available on request. |
Parameter | Min | Max | Units | Reference Document |
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VIN supply voltage (variant "-Z" with MUN12A for U8) | 4.5 | 5.5 | V | |
VIN supply voltage (all other variants) | 3.6 | 5.5 | V | |
Operating temperature | -40 | 85 | °C |
Table 19: Module recommended operating conditions.
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Please check Xilinx datasheet ... for complete list of absolute maximum and recommended operating ratings. |
Commercial grade: 0°C to +70°C.
Extended grade: 0°C to +85°C.
Industrial grade: -40°C to +85°C.
Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Module size: 60 mm × 40 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 5.0 mm.
PCB thickness: 1.6 mm.
Highest part on PCB: approx. 1.6 mm. Please download the step model for exact numbers.
All dimensions are given in millimeters.
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Date | Revision | Notes |
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2020-11-05 | 04 | Changed DDR3, Flash, see PCN |
2019-03-12 | 03 | changed 3.3V DCDC |
02A | Electrical same as REV 02. | |
02 | First production release | |
- | 01 | Prototypes |
Table 20: Module hardware revision history.
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
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2019-10-31 | v.56 | Martin Rohrmüller |
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2019-10-30 | v.55 | John Hartfield |
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2019-06-27 | v.54 | Martin Rohrmüller |
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2019-06-11 | v.53 | Guillermo Herrera |
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2019-03-29 | v.51 | Martin Rohrmüller |
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2018-11-20 | v.44 | John Hartfiel |
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2018-10-10 | v.43 | John Hartfiel |
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2018-10-09 | v.42 | Martin Rohrmüller |
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2018-10-01 | v.41 | Martin Rohrmüller |
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2018-09-21 | v.39 | Martin Rohrmüller |
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2018-07-20 | v.37 | John Hartfield |
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2018-07-06 | v.34 | Martin Rohrmüller |
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Table : Module PL I/O bank voltages.
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Parameter
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Units
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Reference Document
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VIN supply voltage
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V
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Storage temperature
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°C
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Table : Module absolute maximum ratings.
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Assembly variants for higher storage temperature range are available on request. |
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Table : Module recommended operating conditions.
Note |
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Please check Xilinx datasheet ... for complete list of absolute maximum and recommended operating ratings. |
Commercial grade: 0°C to +70°C.
Extended grade: 0°C to +85°C.
Industrial grade: -40°C to +85°C.
Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Module size: ... mm × ... mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ... mm.
PCB thickness: ... mm.
Highest part on PCB: approx. ... mm. Please download the step model for exact numbers.
All dimensions are given in millimeters.
Put mechanical drawings here...
Figure : Module physical dimensions drawing.
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Notes
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01
...
Prototypes
Table : Module hardware revision history.
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Put picture of actual PCB showing model and hardware revision number here...
Figure : Module hardware revision number.
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Page info | modified-date | modified-date | dateFormat | yyyy-MM-dd |
infoType | Current version
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v.60 | John Hartfiel |
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2017-05-30 | v.1 | Jan Kumann | Initial document. | all | Jan Kumann, John Hartfiel | ||||||||||
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Table 21Table : Document change history.
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