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Table of Contents
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Overview
The Trenz Electronic TEB0724-01 is a developement carrier board for the TE0724 and compatible modules. It facilitates easy access to all on the module available features.
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Refer to http://trenz.org/teb0724-info for the current online version of this manual and other available documentation.
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Key Features
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Table of Contents
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Overview
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The Trenz Electronic TEB0724-02 is a developement carrier board for the TE0724 and compatible modules. It facilitates easy access to all on the module available features.
Refer to http://trenz.org/teb0724-info for the current online version of this manual and other available documentation.
Key Features
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- Samtec 160 pin board to board connector for 4,0 cm x 6,0 cm module
- 10x 2x6 Pin Pmods, (8 usable as dual Pmods, 1x single Pmod, 1x I2C compatible Pmod)
- MicroUSB to JTAG/UART bridge
- CAN screw terminal
- RJ45 Gigabit Ethernet MagJack connector
- 6x LED, 2x Push Buttons on FPGA
- 1 LED and 1 Push Button on PS
- Power and Reset Push Buttons
- On-board Power Protection Circuit and Power on LED
Block Diagram
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Block Diagram
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Main Components
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Table 1: TE0724-01 main components.
- Module connector for 4,0x6.0 cm module
- Pmods usabel as dual Pmods, J10, J11, J12, J13, J14, J15, J16, J17
- Pmod (single), J20
- I2C Pmod, J21
- CAN screw terminal, J2
- 5V 2.1mm input jack, J18
- microUSB J4
- USB to JTAG/UART bridge FT2232H, U1
- Configuration EEPROM U3
- RJ45 Gigabit Ehternet Jack, J3
- Power Button, S1
- Reset Button, S3
- User Button PS, S5
- User LED (green) PS, D8
- 2x User Button PL, S2, S4
- 6x User LEDs (red) PL, D2-D7
- Power LED (green), D36
- 2x10 Pin header for Boot and Programming options, J6
- 2x6 Pin header for jumper setting of CAN bus termination resistors, J22
- microSD Card Slot, J5
Initial Delivery State
Not programmed.
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Storage device name
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Table 2: Initial delivery state of programmable devices on the baseboard.
Boot Process
The boot device is selected by the mode jumpers on pin header J6. Placing a jumper at pin 13-14 sets Mode0 to low level. Mode1 is set to low level by jumper on over pin 15-16. Boot modes are further described at the corresponding section of the modules, e.g. Table 2, Boot mode selection of TE0724 TRM. Default with no jumpers is boot from SD-Card.
Signals, Interfaces and Pins
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Board to Board (B2B) I/Os
I/O signals connected to the B2B connector:
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Main Components
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- Module connector for 4,0x6.0 cm module
- Pmods usabel as dual Pmods, J10, J11, J12, J13, J14, J15, J16, J17
- Pmod (single), J20
- I2C Pmod, J21
- CAN screw terminal, J2
- 5V 2.1mm input jack, J18
- microUSB J4
- USB to JTAG/UART bridge FT2232H, U1
- Configuration EEPROM U3
- RJ45 Gigabit Ehternet Jack, J3
- Power Button, S1
- Reset Button, S3
- User Button PS, S5
- User LED (green) PS, D8
- 2x User Button PL, S2, S4
- 6x User LEDs (red) PL, D2-D7
- Power LED (green), D36
- 2x10 Pin header for Boot and Programming options, J6
- 2x6 Pin header for jumper setting of CAN bus termination resistors, J22
- microSD Card Slot, J5
- Dip switches for selecting B_VCCIO_35, S6
- DCDC (B_VCCIO_35), U8
- DCDC (B_3.3V), U7
Initial Delivery State
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Configuration Signals
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The boot device is selected by the mode jumpers on pin header J6. Placing a jumper at pin 13-14 sets Mode0 to low level. Mode1 is set to low level by jumper on pin 15-16. Boot modes are further described at the corresponding section of the modules, e.g. Table 2, Boot mode selection of TE0724 TRM. Default with no jumpers is boot from SD-Card.
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Table 3: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors.
The TEB0724 carrier board supplies the attached module with 5V DC. All power rails on the module and the baseboard are generated from this at the module and routed back the carrier. For detailed information about the pin out, please refer to the Pin-out Tables.
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JTAG Interface
There is no device with JTAG port on the baseboard. JTAG access to the module is provided through B2B connector J1. This is routed to the carriers USB to JTAG/UART bridge.
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JTAG Signal
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B2B Connector Pin
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Table 4: JTAG interface signals.
System Control I/O Pins
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Table 5: System Control I/O pins.
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SD Card Interface
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Table 6: SD Card interface signals and connections.
Ethernet Interface
The TEB0724 Carrier Board has a RJ45 Gigabit Ethernet MagJack (J3) with two LEDs. On-board Ethernet MagJack pins are routed to B2B connector J1 via MDI. LEDs are also routed to the B2B connector.
Ethernet PHY connection
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J1-25
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Table 7: Ethernet MagJack
I2C Interface
On-board I2C bus is accaessable with the following pins:
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Table 8: I2C pins.
There are no I2C devices on the base board. Pullup resistors have to be provided by the module.
On-board Peripherals
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Pmods
The GPIOs of the 10 Pmods (J10 to J17, J20, J21) are connected with 100 Ohm differential routing to the B2B connector. J21 is a pure I2C compatible Pmod, without additional signals. The other 9 are GPIO Pmods where despite J20 all others can be used as dual Pmods. By default VCCIO_35 is connected with a 0 Ohm resistor to 3.3V. De-soldering this resistor and using not fitted pin header J19 instead, the variable bank power VCCIO_35 for the Pmods J10, J11, J12, J13, J14, J16 can be selected.
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Signals, Interfaces and Pins
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Board to Board (B2B) I/Os
I/O signals connected to the B2B connector:
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microUSB JTAG/UART Interface
The microUSB connector provides JTAG access to the module through the carriers USB to JTAG/UART bridge, routed to B2B connector J1. The UART is routed via a levelshifter. There is no device with JTAG port on the baseboard.
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SD Card Interface
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Ethernet Interface
The TEB0724 Carrier Board has a RJ45 Gigabit Ethernet MagJack (J3) with two LEDs. On-board Ethernet MagJack pins are routed to B2B connector J1 via MDI. LEDs are also routed to the B2B connector.
Ethernet PHY connection
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I2C Interface
On-board I2C bus is accaessable with the following pins:
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There are no I2C devices on the base board. Pullup resistors have to be provided by the module.
Pmods
The GPIOs of the 10 Pmods (J10 to J17, J20, J21) are connected with 100 Ohm differential routing to the B2B connector. J21 is a pure I2C compatible Pmod, without additional signals. The other 9 are GPIO Pmods where despite J20 all others can be used as dual Pmods.
Via dip switches S6-1 to S6-3 the variable bank power B_VCCIO_35 for the Pmods J10, J11, J12, J13, J14, J16 can be selected. Respect power regulator limits!
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CAN Screw Terminal
The CAN bus is routed to screw terminal J2.
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Jumpers on J22-1 to J22-3 and J22-2 to J22-4 connect proper split termination resistors to the CAN bus.
Pin Header
Pin Header J6 provides access to power functions, bootmode selection and PMIC In-Circuit Programming (For initial PMIC In-Circuit Programming of the module, Diode D28 has to be removed).
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Alternatively to selecting B_VCCIO_35 by using S6 dip switches, VCCIO_35 ( e.g. SoM TE0724, Bank 35) can be selected by removing R45 and adding a jumper on optional J19. In table 18 valid jumper positions are given. Voltages and maximum current ratings could be found in the corresponding TRM of the attached module, (e.g. TE0724 TRM#PowerRails ).
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Optional fitted headers J7, J8 and J9 are to provide full access to the Pins at the B2B connector, especially for testing and extension purposes. Description follows below.
PL Button and LED IOs are additionally routed to optionally assembled pin header J8.
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Optional pin header J7 gives access to otherwise not used PS MIO IOs at a 3.3V bank.
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Optional pin header J9 gives access to otherwise not used PS MIO IOs at a 1.8V bank.
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On-board Peripherals
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USB to JTAG/UART bridge
The TEB0724 carrier board has on-board microUSB 2.0 (J4) high-speed to UART/FIFO IC FT2232H (U1) from FTDI. Channel A can be used as JTAG Interface (MPSSE) to program on module JTAG devices. Channel B can be used as UART Interface routed via a level shifter to the 1.8V section of the B2B connector, usually connected to the PS of the SoM. There is also a 256-byte serial EEPROM connected to the FT2232H chip pre-programmed with license code to support Xilinx programming tools.
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Oscillators
The module has the following reference clock signals provided by on-board oscillators:
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On-board LEDs
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On-board Push Buttons
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Dip-Switches
Dip-switch S6-1..3 are used to select the adjustable board power. Tabel 14 shows the signals, table 15 how to adjust the switches for corresponding B_VCCIO_35 Voltages.
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Power and Power-On Sequence
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Power Consumption
Power supply with minimum current capability of 3A for system startup is recommended.
The maximum power consumption depends on the attached module the design running on the module and additional peripherals.
Xilinx provide a power estimator excel sheets to calculate power consumption for FPGAs. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.
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To avoid any damage to the base board and attached module, check for stabilized voltages should be carried out (i.e. power good and enable signals) before powering up any SoC's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence. |
Power Distribution Dependencies
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User should also check related module documentation and Xilinx data sheet, respectively.
Power-On Sequence
The power-on sequence is solely controlled by the attached module. The baseboard DCDC regulators U7 and U8 are enabled by the 3.3V rail of the module. Optional sequenzing signals for integration of additional hardware are PWR_GPIO2 and PWR_GPIO4.
If the attached module uses an external bank power VCCIO_35, this has to be powered up after the modules SOCs powerrails are up and before any other signal is applied to the bank IOs. The 1.8V and 3.3V power rails are used for the SD Card level shifter U13. The datasheet states to first power up 1.8V and then 3.3V, this has to be taken into account when reconfiguring the power circuit of the attached SoM.
Power-Off is in reverse order. VCCIO_35 has to be disabled before the SoCs core voltages are turned off.
Power Rails
Some of the power rails are sourced by the attached module, see coresponding TRMs of this for further information (e.g. TE0724 TRM#PowerRails).
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Board to Board Connectors
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Technical Specifications
Absolute Maximum Ratings
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Recommended Operating Conditions
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Please check also the attached SOMs datasheet for a complete list of absolute maximum and recommended operating ratings. |
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Physical Dimensions
Module size: 105 mm × 100 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 4 mm.
PCB thickness: 1.6 mm.
Highest part on PCB: approx. 13.5 mm. Please download the step model for exact numbers.
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In 'Physical Dimension' section, top and button view of moduloe must be insterted, information regarding physical dimention can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part)for every SoM. For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:
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Currently Offered Variants
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Revision History
Hardware Revision History
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
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Document Change History
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Table 9: Pmod connections.
USB to JTAG/UART bridge
The TEB0724 carrier board has on-board microUSB 2.0 (J4) high-speed to UART/FIFO IC FT2232H (U1) from FTDI. Channel A can be used as JTAG Interface (MPSSE) to program on module JTAG devices. Channel B can be used as UART Interface routed to via a level shifter to the 1.8V section of the B2B connector, usually connected to the PS of the SoM. There is also a 256-byte serial EEPROM connected to the FT2232H chip pre-programmed with license code to support Xilinx programming tools.
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Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content. |
CAN Screw Terminal
The CAN bus is routed to screw terminal J2.
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Table 10: CAN bus connection.
Jumpers on J22-1 to J22-3 and J22-2 to J22-4 connect proper split termination resistors to the CAN bus.
Oscillators
The module has the following reference clock signals provided by on-board oscillators:
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Table 11: Reference clock signals.
On-board LEDs
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MIO user LED
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Table 12: On-board LEDs.
On-board Push Buttons
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S2
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PS MIO user button, pulled up, on push de-asserted
Table 13: On-board Push Buttons.
Pin Header
Pin Header J6 provides access to power functions, bootmode selection and PMIC In-Circuit Programming.
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Table 14: Pin Header J6.
For voltage selection VCCIO_35 (SoM TE0724, Bank 35) other than 3.3V the header J19 can optionaly assembled. Therefore 0 Ohm resistor R45 has to be removed!
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J19-5
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Table 15: Optional Pin Header J19.
Optional fitted headers J7, J8 and J9 are to provide full access to the Pins at the B2B connector, especially for testing and extension purposes. Description follows below.
PL Button and LED IOs are additionally routed to optionally assembled pin header J8.
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Table 16: Optional Pin Header J8.
Optional pin header J7 gives access to otherwise not used PS MIO IOs at a 3.3V bank.
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Table 17: Optional Pin Header J7.
Optional pin header J9 gives access to otherwise not used PS MIO IOs at a 1.8V bank.
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J1-42
Table 18: Optional Pin Header J9.
Power and Power-On Sequence
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Power Consumption
The maximum power consumption depends on the attached module the design running on the module and additional peripherals.
Xilinx provide a power estimator excel sheets to calculate power consumption for FPGAs. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.
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Table 19: Typical power consumption.
* TBD - To Be Determined soon with reference design setup.
Power supply with minimum current capability of 3A for system startup is recommended.
Warning |
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To avoid any damage to the base board and attached module, check for stabilized voltages should be carried out (i.e. power good and enable signals) before powering up any SoC's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence. |
Power Distribution Dependencies
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User should also check related module documentation and Xilinx data sheet, respectively.
Power-On Sequence
The power-on sequence is solely controlled by the attached module. Optional sequenzing signals for integration of additional hardware are PWR_GPIO2 and PWR_GPIO4. If the attached module uses the adjustable bank power VCCIO_35, this has to be powered up after the modules SOCs powerrails are up and before any other signal is applied to the bank IOs. The 1.8V and 3.3V power rails are used for the SD Card level shifter U13. The datasheet states to first power up 1.8V and then 3.3V, this has to be taken into account when reconfiguring the power circuit of the attached SoM.
Power Rails
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Power Rail Name
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B2B J1 Pins
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Direction on B2B
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1.8V
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VLDO1
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VBAT
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Table 20 : Board power rails.
Board to Board Connectors
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The TEB0724 base board has a 160-pin double-row REF-192552-01 connector on the top side.
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Order
number
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Table 21: Connectors for module and base board.
Variants Currently In Production
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Technical Specifications
Absolute Maximum Ratings
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Parameter
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Units
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Reference Document
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VIN supply voltage
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V
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Storage temperature
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-30
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°C
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Table 20: Board absolute maximum ratings.
Note |
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Assembly variants for higher storage temperature range are available on request. |
Recommended Operating Conditions
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Table 21: Board recommended operating conditions.
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Please check also the attached SOMs datasheet for complete list of absolute maximum and recommended operating ratings. |
Operating Temperature Ranges
Commercial grade: 0°C to +70°C.
Extended grade: 0°C to +85°C.
Industrial grade: -40°C to +85°C.
Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Physical Dimensions
Module size: 105 mm × 100 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 4 mm.
PCB thickness: 1.6 mm.
Highest part on PCB: approx. 13.5 mm. Please download the step model for exact numbers.
All dimensions are given in millimeters.
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title | Figure 4: Module physical dimensions drawing. |
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Revision History
Hardware Revision History
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Notes
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01
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Prototypes
Table 22: Module hardware revision history.
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
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Document Change History
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Date
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Revision
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Contributors
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Description
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2018-07-02
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v.1
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Initial document.
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Disclaimer
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