Page History
Template Revision 2.12
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Important General Note:
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Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
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Figure template:
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title | Text |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Table template:
- Layout macro can be use for landscape of large tables
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anchor | Table_tablename |
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title | Text |
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The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below
<type>_<main section>_<name>
- type: Figure, Table
- main section:
- "OV" for Overview
- "SIP" for Signal Interfaces and Pins,
- "OBP" for On board Peripherals,
- "PWR" for Power and Power-On Sequence,
- "B2B" for Board to Board Connector,
- "TS" for Technical Specification
- "VCP" for Variants Currently in Production
- "RH" for Revision History
- name: custom, some fix names, see below
- Fix names:
"Figure_OV_BD" for Block Diagram
"Figure_OV_MC" for Main Components
"Table_OV_IDS" for Initial Delivery State
"Table_PWR_PC" for Power Consumption
- "Figure_PWR_PD" for Power Distribution
- "Figure_PWR_PS" for Power Sequence
- "Figure_PWR_PM" for Power Monitoring
- "Table_PWR_PR" for Power Rails
- "Table_PWR_BV" for Bank Voltages
"Table_TS_AMR" for Absolute_Maximum_Ratings
"Table_TS_ROC" for Recommended_Operating_Conditions
- "Figure_TS_PD" for Physical_Dimensions
- "Table_VCP_SO" for TE_Shop_Overview
"Table_RH_HRH" for Hardware_Revision_History
- "Figure_RH_HRN" for Hardware_Revision_Number
- "Table_RH_DCH" for Document_Change_History
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Note for Download Link of the Scroll ignore macro:
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Table of Contents
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Overview
Trenz Electronic TEM0007 module is an industrial-grade FPGA micromodule integrating a Microsemi Polarfire SoC FPGA, Gigabit Ethernet PHY, USB PHY 2.0, one GByte LPDDR4 SDRAM, 64 MByte SPI Flash memory for configuration and operation, and power supply. A large number of configurable I/Os is provided via robust board-to-board (B2B) connectors.
Refer to http://trenz.org/tem0007-info for the current online version of this manual and other available documentation.
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Notes :
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Key Features
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id | Comments |
Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options
Key Features' must be split into 6 main groups for modues:
- SoC/FPGA
- Package:
- Speed:
- Temperature:
- RAM/Storage
- E.g. SDRAM, SPI
- On Board
- E.g. CPLD, PLL
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
Key Features' must be split into 6 main groups for carrier:
- Modules
- TE0808, TE807, TE0803,...
- RAM/Storage
- E.g. SDRAM, SPI
- On Board
- E.g. CPLD, PLL
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
- SoC/FPGA
- Industrial-grade Microsemi Polarfire SoC MPFS250T-1FCVG484I
- RAM/Storage
- 1 GByte LPDDR4
- 64 MByte SPI Flash Memory
- On Board
- System Controller CPLD
- MAC address serial EEPROM
- Interface
- 10/100/1000 Mbps Gigabit Ethernet PHY
- Highly Integrated Full-Featured Hi-Speed USB 2.0 ULPI Transceiver
- Trenz 4 x 5 module socket connectors (3 x Samtec LSHM series connectors)
- Power
- On-board DC-DC converter
- Dimension
- 40 mm x 50 mm
Block Diagram
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id | Comments |
add drawIO object here.
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For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" . |
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anchor | Figure_OV_BD |
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title | TEM0007 block diagram |
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Main Components
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id | Comments |
Notes :
- Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" . |
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anchor | Figure_OV_MC |
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title | TEM0007 main components |
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- Microsemi Polarfire SoC MPFS250T, U2
- 1 GByte LPDDR4 SDRAM, U6
- Integrated 10/100/1000 Mbps Energy Efficient Ethernet Transceiver, U7
- Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver, U11
- Lattice Semiconductor MachXO2 System Controller CPLD, U1
- B2B Connector Samtec Razor Beam, JM1...3
- EEPROM, U10
- Serial NOR Flash, U3
Initial Delivery State
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Notes : Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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anchor | Table_OV_IDS |
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title | Initial delivery state of programmable devices on the module |
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Storage device name
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Content
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Notes
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SPI NOR Flash, U3
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Signals, Interfaces and Pins
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Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
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anchor | Table_SIP_B2B |
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title | General SoC I/O to B2B connectors information |
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JTAG Interface
JTAG access to the TEM0007 SoM through B2B connector JM2.
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anchor | Table_SIP_JTG |
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title | JTAG pins connection |
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JTAG Signal
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B2B Connector
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JM2-99
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Pulled Low: Microsemi Polarfire SoC
Pulled High: Lattice MachXO CPLD
UART Interface
The UART interface is connected from the Polarfire SoC to the B2B connector. If this interface is not necessary, these pins can be used for other functionality.
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anchor | Table_OBP_UART |
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title | UART interface description |
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SDIO Interface
The SDIO interface is connected from the Polarfire SoC to the B2B connector. If this interface is not necessary, these pins can be used for other functionality.
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anchor | Table_OBP_SDIO |
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title | SDIO interface description |
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MSSIO Interface
The MSSIO interface is connected from the Polarfire SoC to the B2B connector.
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anchor | Table_OBP_MSSIO |
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title | MSSIO interface description |
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SGMII Interface
The Polarfire Soc provides two SGMII interfaces whereby one interface is connected to the B2B connector.
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anchor | Table_OBP_SGMII |
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title | SGMII interface description |
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MGT Lanes
There are four MGT (Multi Gigabit Transceiver) lanes and two two clocks connected between the B2B connector JM3 and the Polarfire SoC bank 5. Each MGT lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, signal schematic name, and board-to-board pin connection:
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anchor | Table_SIP_MGT |
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title | MGT Lanes Connection |
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Lane
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Schematic
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Gigabit Ethernet
On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY SGMII interface is connected to the Polarfire SoC.
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anchor | Table_OBP_ETH |
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title | Gigabit Ethernet pin description |
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System Controller CPLD I/O Pins
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SPI_CS , SPI_DQ0... SPI_DQ3
SPI_SCK
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.
Example:
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Test Points
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anchor | Table_OBP_TestPoints |
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title | Test Points Information |
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On-board Peripherals
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- 11
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USB Interface
USB PHY is provided by Microchip USB3320. The ULPI interface is connected to the Polarfire SoC. I/O voltage is fixed at 3.3 V. Reference clock input for the USB PHY is supplied by the on-board 52.00 MHz oscillator (U12).
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anchor | Table_OBP_USB |
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title | General Overview of the USB PHY Signals |
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DP - 18,
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OTG-D_P
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Notes :
- add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
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anchor | Table_OBP |
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title | On board peripherals |
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System Controller CPLD
The System Controller CPLD (U1) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.
Gigabit Ethernet
On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U7). The Ethernet PHY SGMII interface is connected to the Polarfire SoC. The reference clock input of the PHY is supplied from an on-board 25.00 MHz oscillator (U8).
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anchor | Table_OBP_ETH |
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title | Ethernet PHY to Polarfire SoC connections |
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Bank 5 - N6
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SGMII0_IN_P
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U7 - 1
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Bank 5 - L5
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SGMII0_OUT_P
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U7 - 4
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USB PHY
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U2 - G4
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OTG-STP
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U11 - 29
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U2 - F1
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OTG-DIR
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U11 - 31
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OTG_DATA0
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LPDDR4 SDRAM
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TEM0007 SoM has a one GByte volatile LPDDR4 SDRAM IC for storing user application code and data.
- Part number: IS43LQ32256A-062BLI
- Supply voltage: +1.8 V / +1.1 V
- Speed: 1600 MHz
- Temperature: Industrial (-40°C to +85°C)
EEPROM
There is a 2 Kbit EEPROM provided on the module TEM0007 with a pre-programmed globally unique MAC.
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anchor | Table_OBP_EEP |
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title | I2C EEPROM interface MSSIOs and pins |
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SPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
The TEM0007 is equipped with a MT25QU512ABB8E12-0SIT flash memory chip, U3, which provided storage for FPGA configuration files. After configuration, the remaining free memory can be used for application data storage.
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anchor | Table_OBP_SPI |
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title | SPI Flash interface pins |
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Power and Power-On Sequence
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
- Power on-sequence
- Power distribution
- Voltage monitoring circuit
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For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" . |
Power Supply
Power supply with minimum current capability of 3 A for system startup is recommended.
Power Consumption
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anchor | Table_PWR_PC |
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title | Power Consumption |
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* TBD - To Be Determined
Power Distribution Dependencies
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anchor | Figure_PWR_PD |
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title | Power Distribution |
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Power-On Sequence
The power sequence is the recommended one. The final sequence depends on the system controller.
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anchor | Figure_PWR_PS |
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title | Power Sequency |
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Voltage Monitor Circuit
The TEM0007 delivers two voltage monitor circuits. The first circuit is responsible for the selection of voltage "VDDAUX1". This voltage is selected on the basis of the voltage of "VCCIOB". If "VCCIOB" is higher than 2.9 V, "VDDAUX1" should be +3.3 V. If it is smaller, "VDDAX1" should be +2.5 V. The second circuit monitors the +1.0 V power rail. According to this rail, the reset is set/unset to realize a brown-out detection. Furthermore, a possibility for a manual reset is available.
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anchor | Figure_PWR_VMC |
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title | Voltage Monitor Circuit |
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B2B Connector
JM2 Pin
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Bank
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Voltage
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VCCIOB
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VCCIOB
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Recommended Operating Conditions
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Revision History
Hardware Revision History
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id | Comments |
Set correct links to download arrier, e.g. TE0706 REV02:
TE0706-02 -> https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents
Note:
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