Versions Compared

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.


Page properties
hiddentrue
idComments

Template Revision 2.12

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"


HTML
<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
<style>
.wrapped{
  width: 100% !important;
  max-width: 1200px !important;
 }
</style>


Page properties
hiddentrue
idComments

Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:

        Scroll Title
        anchorFigure_anchorname
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

      • Scroll Title
        anchorTable_tablename
        titleText

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefault
        style
        widths
        sortByColumn1
        sortEnabledfalse
        cellHighlightingtrue

        ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



Page properties
hiddentrue
idComments

-----------------------------------------------------------------------


Page properties
hiddentrue
idComments

Note for Download Link of the Scroll ignore macro:


Scroll Ignore

Download PDF version of this document.


Scroll pdf ignore

Table of Contents

Table of Contents

Overview

The Trenz Electronic TEM0005-02 is a low-cost module with Microsemi SmartFusion2 SoC and 32 MByte flash memory for configuration and operation. SmartFusion2 combines a 166 MHz Cortex-M3 MCU with 256 KByte Flash and 80 KByte SRAM as well as 12 kLUT FPGA Core Logic.

Refer to http://trenz.org/tem0005-info for the current online version of this manual and other available documentation.

Page properties
hiddentrue
idComments

Notes :

Key Features

Page properties
hiddentrue
idComments

Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features'  must be split into 6 main groups for modules and mainboards:

  • SoC/FPGA
    • Package: SFVC784
    • Device: ZU2...ZU5*
    • Engine: CG, EG, EV*
    • Speed: -1LI, -2LE,*, **
    • Temperature: I, E,*, **
  • RAM/Storage
    • Low Power DDR4 on PS
      • Data width: 32bit
      • Size: def. 2GB*
      • Speed:***
    • eMMC
      • Data width: 8Bit
      • size: def. 8GB *
    • QSPI boot Flash in dual parallel mode (size depends on assembly version)
      • Data width: 8bit
      • size: def. 128MB *
    • HyperRAM/Flash (optional, default not assembled)
      • size:*
    • MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
  • On Board
    • Lattice LCMXO2
    • PLL SI5338
    • Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
    • Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
  • Interface
    • 132 x HP PL I/Os (3 banks)
    • ETH
    • USB
    • 4 GTR (for USB3, Sata, PCIe, DP)
    • MIO for UART
    • MIO for SD
    • MIO for PJTAG
    • JTAG
    • Ctrl
  • Power
    • 3.3V-5V Main Input
    • 3.3V Controller Input
    • Variable Bank IO Power Input
  • Dimension
    • 4 cm x 5 cm
  • Notes
    • * depends on assembly version
    • ** also non low power assembly options possible
    • *** depends on used U+ Zynq and DDR4 combination


Key Features'  must be split into 6 main groups for carrier:

  • Modules
    • TE0808, TE807, TE0803,...
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension


  • SoC/FPGA
    • Package: VFG400
    • Device: M2S010, M2S050 *
    • Engine: 166Mhz 32Bit ARM Cortex-M3
    • Speed: Standard
    • Temperature: C, I*
  • RAM/Storage
    • Low Power DDR3
      • Data width: 16bit
      • Size: def. 2Gb
    • SPI Flash
      • size: 256 M bit 
    • 2Kb EEPROM
  • On Board
    • Crypto Authentication IC
    • Voltage monitor IC
    • 10/100 Mbps PHY Ethernet
  • Interface
    • Samtec ST5 B2B Connector
  • Power
    • 3.3V supplied from carrier
  • Dimension
    • 56 x 31 mm
  • Notes
    • * depends on assembly version

Block Diagram

Page properties
hiddentrue
idComments

add drawIO object here.

Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .



Scroll Title
anchorFigure_OV_BD
titleTEM0005 block diagram


Scroll Ignore
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue

draw.io Diagram
borderfalse
diagramNameTEM0005_OV_BD
simpleViewerfalse
width639
linksauto
tbstylehidden
diagramDisplayName
lboxtrue
diagramWidth641
revision12



Scroll Only

Image Added


Main Components

Page properties
hiddentrue
idComments

Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


Note

For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .



Scroll Title
anchorFigure_OV_MC
titleTEM0005 main components


Scroll Ignore
draw.io Diagram
borderfalse
diagramNameTEM0005_OV_MC
simpleViewerfalse
width600
linksauto
tbstylehidden
diagramDisplayName
lboxtrue
diagramWidth641
revision20


Scroll Only

Image Added


  1. Microsemi SmartFusion2 SoC, U2
  2. Dual DCDC Regulator, U7
  3. EEPROM, U4
  4. 10/100 Mb Ethernet, U1
  5. QSPI Flash, U3
  6. Authentication IC, U6
  7. DDR3 Memory, U5
  8. B2B Connector, J1

Initial Delivery State

Page properties
hiddentrue
idComments

Notes :

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty


Scroll Title
anchorTable_OV_IDS
titleInitial delivery state of programmable devices on the module

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Storage device name

Content

Notes

Quad SPI Flash

Not Programmed


EEPROMNot Programmed


CryptoAuthenticationNot Programmed


Configuration Signals

Page properties
hiddentrue
idComments
  • Overview of Boot Mode, Reset, Enables.


Scroll Title
anchorTable_OV_RST
titleReset process.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Signal

B2BI/ONote
RESET


J1-11
Active low reset 


Signals, Interfaces and Pins

Page properties
hiddentrue
idComments

Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector, J1.

Scroll Title
anchorTable_SIP_B2B
titleGeneral PL I/O to B2B connectors information

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

FPGA BankInterfaceI/O Signal CountVoltage LevelNotes
Bank 1GPIO8x Single Ended3.3V
UART4x Single Ended3.3V
I2C2x Single Ended3.3V
GOLDEN1x Single Ended3.3V
Bank 2ULPI/I/O12x Single Ended3.3V
I2C2x Single Ended3.3V
GPIO10x Single Ended 3.3V
SC SPI4x Single Ended3.3V
SPI17x Single Ended3.3V
Bank 3JTAG5x Single Ended3.3V
Reset 1x Single Ended3.3V
Bank 4I/O24x Single Ended/12 LVDS pairs3.3V
Bank 6I/O28x Single Ended/14 LVDS pairsVDDI6max 2.5V
Bank 7I/O4x Single Ended3.3V



JTAG Interface

JTAG access to the TEM0005 SoM through B2B connector J1.

Scroll Title
anchorTable_SIP_JTG
titleJTAG pins connection

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

JTAG Signal

B2B Connector

TMSJ1-14
TDIJ1-8
TDOJ1-10
TCK

J1-12

TRSTJ1-7


Test Points

Page properties
hiddentrue
idComments

you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

Test PointSignalB2BNotes
10PWR_PL_OKJ2-120



Scroll Title
anchorTable_SIP_TPs
titleTest Points Information

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Test PointSignalConnected toNotes
TP1CLKOUTRegulator, U7


On-board Peripherals

Page properties
hiddentrue
idComments

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


Page properties
hiddentrue
idComments

Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


Scroll Title
anchorTable_OBP
titleOn board peripherals

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Chip/InterfaceDesignatorNotes
QSPIU3
DDR3L SDRAMU5
EEPROMU4
Authentication ICU6
Ethernet PHYU1
OscillatorsY3


(Quad) SPI Flash Memory

Page properties
hiddentrue
idComments

Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

The TEM0005 is equipped with a (Q)SPI flash memory, U3 provided in order to store data and configuration. 

Scroll Title
anchorTable_OBP_SPI
titleQuad SPI interface MIOs and pins

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

SchematicU3 PinConnected toNotes
SPI0_SS0nCEFPGA Bank 2
SPI0_CLKSCKFPGA Bank 2
SPI0_SDOSI/IO0FPGA Bank 2
SPI0_SDISO/IO0FPGA Bank 2


EEPROM

The TEM0005 is equipped with an EEPROM IC, U4. The I2C signals are connected to authentication IC as well.

Scroll Title
anchorTable_OBP_EEP
titleI2C EEPROM interface MIOs and pins

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

SchematicU4 PinNotes
I2C0_SCLSCL
I2C0_SDASDA



Scroll Title
anchorTable_OBP_I2C_EEPROM
titleI2C address for EEPROM

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

 PinI2C AddressDesignatorNotes
SCL/SDA0x70U4


Authentication IC

There is an Authentication IC ATECC608A provided on TEM0005, The IC is connected to I2C0 bus.

Scroll Title
anchorTable_OBP_Auth
titleAuthentication IC information

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

 PinSchematicNotes
SCLI2C0_SCLSerial Clock
SDAI2C1_SCLSerial Data



Scroll Title
anchorTable_OBP_I2C_Authentication IC
titleI2C address for Authentication IC

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

 PinI2C AddressDesignatorNotes
SCL/SDA0xC0U6This is the default value, which can be changed, see device datasheet.


DDR3L SDRAM

Page properties
hiddentrue
idComments

Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TEM0005 SoM has 2 Gb volatile DDR3L SDRAM IC for storing user application code and data.

  • Part number: IS43TR16128CL-125KBLI
  • Supply voltage: 1.5 V
  • Temperature: -40 to 95 °C

Ethernet Transceiver

On board 10/100 Mbps Ethernet Transceiver U1 is provided on the module TEM0005. 

Scroll Title
anchorTable_OBP_ETH
titleEthernet PHY to Zynq SoC connections

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

U1 Pin Signal NameConnected toNote
RXM/RXPETH1_RXB2B, J1
TXM/TXPETH1_TXB2B, J1
LED0/NWAYENETH1_LED0B2B, J1
LED1/SPEEDETH1_LED1B2B, J1
MDIOETH1_MDIOFPGA Bank 7, U2
MDCETH1_MDCFPGA Bank 7, U2
REXT-GND
INTRPETH1_INTRPFPGA Bank 7, U2
XO/XI-Crystal Oscillator, Y3
nRSTETH1_RSTFPGA Bank 7, U2
CONFIG0...2ETH1_COL/CRC/RXDVFPGA Bank 7, U2
TXCETH1_TXCFPGA Bank 7, U2
TXENETH1_TXENFPGA Bank 7, U2
TXD0...3ETH1_TXD0...3FPGA Bank 7, U2
RXD0...3ETH1_RXD0...3FPGA Bank 7, U2
RXCETH1_RXCFPGA Bank 7, U2
RXCERETH1_RXCERFPGA Bank 7, U2



Clock Sources

Scroll Title
anchorTable_OBP_CLK
titleOsillators

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DesignatorDescriptionFrequencyNote
Y3Crystal Oscillator25 MHzConnected to ETH PHY



Power and Power-On Sequence

Page properties
hiddentrue
idComments

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power supply with minimum current capability of 1.5 A for system startup is recommended.

Power Consumption

Scroll Title
anchorTable_PWR_PC
titlePower Consumption

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Power Input PinTypical Current
VINTBD*


* TBD - To Be Determined

Power Distribution Dependencies

Scroll Title
anchorFigure_PWR_PD
titlePower Distribution


Scroll Ignore
draw.io Diagram
borderfalse
diagramNameTEM0005_PWR_PD
simpleViewerfalse
width639
linksauto
tbstylehidden
diagramDisplayName
lboxtrue
diagramWidth640
revision5



Scroll Only

Image Added


Power-On Sequence

Scroll Title
anchorFigure_PWR_PS
titlePower Sequency


Scroll Ignore
draw.io Diagram
borderfalse
diagramNameTEM0005_PWR_PS
simpleViewerfalse
width639
linksauto
tbstylehidden
diagramDisplayName
lboxtrue
diagramWidth641
revision3


Scroll Only

Image Added


Voltage Monitor Circuit

The TEM0005 is equipped with a voltage monitoring IC, U8. Reset Logic Output (nRST) asserts low when any of the V1, V2, or ADJ inputs are below their reset thresholds. 

Scroll Title
anchorFigure_PWR_VMC
titleVoltage Monitor Circuit


Scroll Ignore
draw.io Diagram
borderfalse
diagramNameTEM0005_PWR_VMC
simpleViewerfalse
width639
linksauto
tbstylehidden
diagramDisplayName
lboxtrue
diagramWidth642
revision4


Scroll Only

Image Added


Power Rails

Scroll Title
anchorTable_PWR_PR
titleModule power rails.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue


Power Rail Name

B2B Connector J1 Pin

DirectionNotes
3.3V1, 2, 3, 4Input
VDDI622Input


Bank Voltages

Scroll Title
anchorTable_PWR_BV
titleZynq SoC bank voltages.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Bank          

Schematic Name

Voltage

Notes
Bank01.5V1.5V
Bank13.3V3.3V
Bank23.3V3.3V
Bank33.3V3.3V
Bank43.3V3.3V
Bank53.3V3.3V


Bank6VDDI6max. 2.5V

supplied by carrier

Bank73.3V3.3V



Board to Board Connectors

Page properties
hiddentrue
idComments
  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors

    Include Page
    6 x 6 SoM LSHM B2B Connectors
    6 x 6 SoM LSHM B2B Connectors

Include Page
DRAFT:3.1 x 5.6 SoM ST5/SS5 B2B Connectors
DRAFT:3.1 x 5.6 SoM ST5/SS5 B2B Connectors

Technical Specifications

Absolute Maximum Ratings

Scroll Title
anchorTable_TS_AMR
titlePS absolute maximum ratings

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

SymbolsDescriptionMinMaxUnit
VINInput Supply Voltage-0.33.63V
STG_TStorage Temperature-45125°C


Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Scroll Title
anchorTable_TS_ROC
titleRecommended operating conditions.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

ParameterMinMaxUnitsReference Document
VIN3.153.45VSee the carrier datasheets.
OPT_T0 /-4085°CSee Microsemi Smartfusion2 datasheet. Depends on assembly version.


Physical Dimensions

  • Module size: 56 mm × 31 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 4 mm.

PCB thickness:  1.6 mm.

Page properties
hiddentrue
idComments

In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .



Scroll Title
anchorFigure_TS_PD
titlePhysical Dimension


Scroll Ignore
draw.io Diagram
borderfalse
diagramNameTEM0005_TS_PD
simpleViewerfalse
width639
linksauto
tbstylehidden
diagramDisplayName
lboxtrue
diagramWidth641
revision3


Scroll Only
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue

Image Added


Currently Offered Variants 

Page properties
hiddentrue
idComments

Set correct link to the shop page overview table of the product on English and German.

Example for TE0706:

    ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

    DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706


Scroll Title
anchorTable_VCP_SO
titleTrenz Electronic Shop Overview

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Trenz shop TEM0005 overview page
English pageGerman page


Revision History

Hardware Revision History

Page properties
hiddentrue
idComments

Set correct links to download  arrier, e.g. TE0706 REV02:

  TE0706-02  ->   https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

  • Date format:  YYYY-MM-DD


Scroll Title
anchorTable_RH_HRH
titleHardware Revision History

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DateRevisionChangesDocumentation Link
2019-10-01REV01
  • Initial Release
REV01
2020-05-20REV02
  • Support M2S050 ->added R29,R30, C24..C26,C31
  • Added resistor R32
  • Full upd LIB
REV02


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Scroll Title
anchorFigure_RV_HRN
titleBoard hardware revision number.


Scroll Ignore
draw.io Diagram
borderfalse
diagramNameTEM0005_RV_HRN
simpleViewerfalse
width200
linksauto
tbstylehidden
diagramDisplayName
lboxtrue
diagramWidth175
revision6


Scroll Only

Image Added


Document Change History

Page properties
hiddentrue
idComments
  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


Scroll Title
anchorTable_RH_DCH
titleDocument change history.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DateRevisionContributorDescription

Page info
infoTypeModified date
dateFormatyyyy-MM-dd
typeFlat

Page info
infoTypeCurrent version
prefixv.
typeFlat
showVersionsfalse

Page info
infoTypeModified by
typeFlat
showVersionsfalse

  • initial Release

--

all

Page info
infoTypeModified users
typeFlat
showVersionsfalse

  • --


Disclaimer

Include Page
IN:Legal Notices
IN:Legal Notices