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Important General Note:
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Export PDF to download, if vivado revision is changed!
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
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Figure template (note: inner scroll ignore/only only with drawIO object):
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Create DrawIO object here: Attention if you copy from other page, use |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Table template:
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Table of contents
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Overview
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NIOS II Design with SDRAM Controller and 5 different LED sequences, that can be toggled using the user button.
Refer to http://trenz.org/max1000-info for the current online version of this manual and other available documentation.
Key Features
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Revision History
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title | Design Revision History |
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- initial release
Release Notes and Know Issues
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title | Known Issues |
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Requirements
Software
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title | Software |
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Hardware
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Design supports following modules:
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title | Hardware Modules |
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Design supports following carriers:
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title | Hardware Carrier |
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Additional HW Requirements:
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title | Additional Hardware |
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Download
Reference Design is only usable with the specified Quartus version. Do never use different Versions of Quartus Software for the same Project.
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Reference Design is available on:
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Basic Design Steps
Add/ Remove project specific description
- Open file "test_board.quar"
- Select Tools → Platform Designer from Quartus menu
- Open file "NIOS_test_board.qsys" in Platform Designer
- Open the component "onchip_ram" (double-click)
- Enable "Initialize memory content" and "Enable non-default initialization file" at Memory initialization, if disabled
- Specify Path for User created initialization file. You can find the file at \software\test_board\mem_init\NIOS_test_board_onchip_ram.hex
- Select Generate → Generate HDL... from the Platform Designer menu
The Generation window will appear
Select "VHDL" as the synthesis language and "None" from the simulation model dropdown menu
Select “Create block symbol file(.bsf)”, if not selected
- Click Generate and close Platform Designer
- Select Processing → Start Compilation from the Quartus menu to compile the Design
Launch
Programming
JTAG
- Connect the Module to USB-Port
- Open the Quartus Prime Programmer from Tools → Programmer
- If the Arrow-USB-Blaster is not visible:
- Click "Hardware Setup..."
- Choose at the drop-down menu "Currently selected hardware" Arrow-USB-Blaster[USB0]
- Close "Hardware Setup"
- If the correct configuration file is not set:
- Delete other files
- Click "Add file..."
- select the correct *.sof file (Path: <project_directory>\output_files\test_board.sof)
- Click start
MAX10 Flash
- Do step 1 to step 3 from section Programming → JTAG, if not done yet
- If the correct configuration file is not set:
- Delete other files
- Click "Add file..."
- Select the correct *.pof file (Path: <project_directory>\output_files\test_board.pof)
- Click start
Usage
- Prepare Hardware like described on section Programming
- Connect UART USB (most cases same as JTAG)
UART
- Open Serial Console "PuTTY"
- Change settings in category "Session"
- Connection Type: Serial
- COM Port: see device manager (Win OS)
- Speed: 115200
- Select "Implicit CR in every LF" in category "Terminal"
- Click Open
- Press reset button at module
- SDRAM test is running
- Flash test is running
- After the tests finished, you can toggle between following LED sequences by pressing user button
- Spirit level
- Case statement sequence
- Shift register sequence
- Knightrider sequence
- Pulse-width modulation sequence
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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Authors
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- Initial release
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Legal Notices
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