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Receiving, levelshifting and forwarding of
- control,
- sensor, measurement and
- status signals
security logic
Push Buttons
USR LED

Firmware Revision and supported PCB Revision

...

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title	On-board LEDs

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B9J11-

VHDL Port name	Direction	SC CPLD Pin	CPLD Bank	Connected to	Function	Notes
X0A0_P	in8	J8	3	CPLD to CRUVI communication	currently not used	X1	A8	8	J11-5	X2	A7	8	J11-7	X3	A6	8	J11-9	X4	D8	8	J11-4	X5	B6	8	J11-10	X6	C9	8	J11-1	X7	E8	8	J11-2	J9-14	PWM signal phase B, low	-
A0_N	in	K8	3			J9-16	PWM signal phase D, high	-
A1_P	in	M13	3			J9-20	PWM signal phase A, low	-
A1_N	in	M12	3			J9-22	PWM signal phase C, high	-
A2_P	in	M9	3			J9-26	PWM signal phase D, low	-
A2_N	in	M8	3			J9-28	PWM signal phase C, low	-
A3_P	in	N8	3			J9-32	PWM signal phase B, high	-
A3_N	in	N7	3			J9-34	PWM signal phase A, high	-
A4_P	out	M7	3	J9-38	current measurement phase B	-
A4_N	out	N6	3	J9-40	push button S2 signal	-
A0_P	in	J8	3	J9-14	A0_N	in	K8	3	J9-16	A1_P	in	M13	3	J9-20	A1_N	in	M12	3	J9-22	A2_P	in	M9	3	J9-26	A2_N	in	M8	3	J9-28	A3_P	in	N8	3	J9-32	A3_N	in	N7	3	J9-34	A4_P	out	M7	3	J9-38	A4_N	out	N6	3	J9-40	A5_P	out	K5	3	J9-44	motor disable signal	disabled when high
A5_N		J5	3	J9-46	CPLD to - CRUVI communication	currently not used
B0_P		N5	3	J9-15	CPLD to - CRUVI communication	currently not used
B0_N	in	N4	3	J9-17	LED D2 signal	active high
B1_B1_P		J7	3	J9-21	CPLD to - CRUVI communication	currently not usedPWM enable
B1_N	in	K7	3	J9-23	clock input for ADCs	5-20 MHz
B2_P	out	L11	3	J9-27	Encoder/Sensor signal A	-
B2_N	out	M11	3	J9-29	Encoder/Sensor signal B	-
B3_P	out	L10	3	J9-33	Encoder/Sensor signal I	-
B3_N	out	M10	3	J9-35	Back EMF signal phase B	-
B4_P	out	J6	3	J9-398	Back EMF signal phase C	-
B4_N	out	K6	3	J9-41	Back EMF signal phase A	-
B5_P	B5_P	out	L5	3	J9-45	current measurement phase A	-
B5_N	out	L4	3	J9-47	voltage measurement DC_LINK	-
HSIO		N9	3	J9-2	CPLD to - CRUVI I/O communication	currently not used
HSO		N10	3	J9-6
RESET		M5	3	J9-8
HSI		N12	3	J9-10
TDI		F5	1B	J9-51, J10-9	JTAG / user IO CPLD firmware dependent	JTAG pinsharing currently not enabled
TDO		F6	1B	J9-53, J10-3	JTAG / user IO CPLD firmware dependent
TMS		G1	1B	J9-55, J10-5	JTAG / user IO CPLD firmware dependent
JTAGEN		E5	1B	J9-57	JTAG enable CPLD firmware dependent
TCK		G2	1B	J9-59, J10-1	JTAG / user IO CPLD firmware dependent
SMB_ALERT		K2	2	J9-3	CPLD to - CRUVI I/O communication	currently not used
SMB_SDA		H5	2	J9-5
SMB_SCL		H4	2	J9-7
REFCLK		M2	2	J9-11
BUTTON1	in	C10	8	S2	User button forwarded to CRUVI	activ low,
BUTTON2	in	B10	8	S1	Motor control enable/disable	activ low
ENC_A	in	A10	8	U13-13	Sensor/Encoder input channel A	-
ENC_B	in	A9	8	U13-12	Sensor/Encoder input channel B	-
ENC_I	in	A11	8	U13-14	Sensor/Encoder input channel I	-
LED0	inout	D6	8	D2	User LED forwarded from CRUVI	active high
LED1	inout	B2	8	D1	Status LED	blinking → motor control aktiv, static on → on system ok and motor control disabled
M_BEMF_B_D	in	B5	8	U15-13	Back EMF signal phase B	-
M_BEMF_C_D	in	A5	8	U15-12	Back EMF signal phase C	-
M_BEMF_A_D	in	A4	8	U15-14	Back EMF signal phase A	-
M_PWM_AH	out	F1	1A	U8-2	Phase A half bridge high (DC_LINK) side driver signal	-
M_PWM_AL	out	E3	1A	U8-3	Phase A half bridge low (PGND) side driver signal	-
M_PWM_BH	out	E1	1A	U9-2	Phase B half bridge high (DC_LINK)side driver signal	-
M_PWM_BL	out	D1	1A	U9-3	Phase B half bridge low (PGND) side driver signal	-
M_PWM_CH	out	E4	1A	U10-2	Phase C half bridge high (DC_LINK)side driver signal	-
M_PWM_CL	out	C1	1A	U10-3	Phase C half bridge low (PGND) side driver signal	-
M_PWM_DH	out	C2	1A	U11-2	Phase D half bridge high (DC_LINK) side driver signal	-
M_PWM_DL	out	B1	1A	U11-3	Phase D half bridge low (PGND) side driver signal	-
SD_IA	in	E6	8	U3-6	Current measurement phase A	33 Ohm series Resistor-
SCLK_A	out	B3	8	U3-7, U5-7	Clock for ADC for current measurement phase A and B	(5-20 MHz)
SD_V	in	B4	8	U7-6	Voltage measurement DC_LINK	33 Ohm series Resistor-
SD_IB	in	A2	8	U5-6	Current measurement phase B	33 Ohm series Resistor-
SCLK_V_A	out	A3	8	U7-7	Clock for ADC for voltage measurement DC_LINK	(5-20 MHz)
M_DISABLE_D_D	out	J1	2	U11-5	Halfe bridge disable phase D	disabled when high, pull up connected, weak pull up enabled
M_DISABLE_A_D	out	M1	2	U8-5	Halfe bridge disable phase A	disabled when high, pull up connected connected, weak pull up enabled
M_DISABLE_B_D	out	L2	2	U9-5	Halfe bridge disable phase B	disabled when high, pull up connected connected, weak pull up enabled
M_DISABLE_C_D	out	K1	2	U10-5	Halfe bridge disable phase C	disabled when high, pull up connected, weak pull up connected enabled
REFCLK		M2	2	J9-11	-	currently not used
RST		M3	2	J10-6	-	currently not used (CPLD RESET)
UART_RX		N2	2	J10-7	-	currently not used/implemented (UART)
UART_TX		N3	2	J10-8	-	currently not used/implemented (UART)
CLK_25MHZ	in	H6	2	U26-3	Clock input for accurate 25 Mhz clk.	currently not used

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title	SC CPLD ports

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VHDL Port nameDirectionSC CPLD PinConnected toFunctionNotesACBUS0A4FTDI U4, pin 22GPIO's available to user

currently not used/implemented

(FIFO or other FTDI functions when FTDI reprogrammed)
ACBUS1B4FTDI U4, pin 23ACBUS2A5FTDI U4, pin 24ACBUS3B5FTDI U4, pin 25ACBUS4A6FTDI U4, pin 26ACBUS5B6FTDI U4, pin 27ACBUS6A7FTDI U4, pin 28ACBUS7A8FTDI U4, pin 29ADBUS4A2FTDI U4, pin 17ADBUS5B2FTDI U4, pin 18ADBUS6A3FTDI U4, pin 19ADBUS7B3FTDI U4, pin 20P_TCKING2FTDI U4, pin 12Forwarded JTAG signals from FTDI chip. Signal names: TCK, TDI, TDO, TMS
(FIFO or other FTDI functions when FTDI reprogrammed)
P_TDIINF5FTDI U4, pin 13P_TDOOUTF6FTDI U4, pin 14P_TMSING1FTDI U4, pin 15M_TCKOUTH5JB2, pin 1004x5 Module JTAG
Bank with VCCIO is VREF_JTAG from Module
M_TDIOUTJ2JB2, pin 96M_TDOINJ1JB2, pin 98M_TMSOUTH6JB2, pin 94FMC_TCKOUTF8J1, pin D29FMC JTAG
TRST not used
FMC_TDIOUTM7J1, pin D30FMC_TDOINN7J1, pin D31FMC_TMSOUTM8J1, pin D33FMC_TRSTN8J1, pin D34PCIE_TCKL11J3, pin A5PCIe JTAG
Currently not used
PCIE_TDIN12J3, pin A6PCIE_TDOM12J3, pin A7PCIE_TMSM13J3, pin A8PCIE_TRSTG10J3, pin B9PCIE_PERSTINF12J3, pin A11Indication that PCIe Bus is up (power, clocks)EN_FMCOUTL4U14, pin 9Enable switched 3.3V FMC powerpulled downEN_FMC_VADJOUTK7U1, pin 41Enable IO power FMC_VADJpulled downEN_PEROUTF13Q4, pin 5Enable perepherie power 3V3_PERpulled downFAN_FMC_ENOUTK8Q1, pin 5Enable FMC FANfloating during configuration (no pull down)FMC_PG_C2MOUTM5J1, pin D1Indicate that all FMC related powers are uppulled upFMC_PRSNT_M2C_LINE9J1, pin H2Indicate if FMC installedLow when FMC present, CPLD weak pullup enabledFMC_SCLOUTJ8J1, pin C31I²C 2-wire serial busMUX in CPLDFMC_SDAINOUTF9J1, pin C30PG_FMC_VADJINJ6U1, pin 35Indicate FMC VADJ power is upFF_RSTLOUTB9J13, pin 6 and J18, pin 6Reset configurationBoth FF are resetted simultanously when pulled LOWFFA_INTLINE8J13, pin 5Indicate interrrupt

LOW when fault condition, pulled up

FFA_MPRSINC10J13, pin 3Indicate FF Module installedLOW when Module present, pulled upFFA_MSELOUTC9J13, pin 4Select attached FF ModulePull low to use I²CFFA_SCLOUTD6J13, pin 8I²C 2-wire serial busMUX in CPLDFFA_SDAINOUTE6J13, pin 7FFB_INTLINA10J18, pin 5Indicate interrruptLOW when fault condition, pulled upFFB_MPRSINA11J18, pin 3Indicate FF Module installedLOW when Module present, pulled upFFB_MSELOUTB10J18, pin 4Select attached FF ModulePull low to use I²CFFB_SCLOUTD8J18, pin 8I²C 2-wire serial busMUX in CPLDFFB_SDAINOUTA9J18, pin 7CPLD_IO_1INB12JB1, pin 88(M)IOs from 4x5 Module(M)IOs used for ETH PHY LEDs
CPLD_IO_2INA12JB1, pin 92(M)IOs from 4x5 ModuleM10_RSTD1

TP22

Not used
M10_RXE4TP24M10_TXE3TP23EN1OUTD11JB1, pin 27Enable on module powerDepends on module, on some similar to reset.MODEOUTB11JB1, pin 31Boot Mode selectionFor Zynq modules only. (LOW → SD, HIGH → primary QSPI)NOSEQOUTE13JB1, pin 8Disable module CPLD power managementDepends on module. On some modules no extended CPLD power management avaialble.PGOODINOUTC11JB1, pin 29Power good signal

This is only for monitoring, do not use as powerenable! Pulled up.

RESINOUTE12JB2, pin 17Module ResetAktive LOWM3.3VOUTINM4JB2, pin 9 and 11Indicates module power is up

Used for perepherie power enable. Floating when no module installed (no pull down).

SFPA_LOSINM10J12, pin 8SFP signal lossHIGH indicates signal lossSFPA_M-DEF0INF10J12, pin 6SFP modul absentHIGH when module physically absentSFPA_RS0OUTN10J12, pin 7SFP rate select RXLOW for 1000BASE-SX, HIGH for 10GBASE-SRSFPA_RS1OUTM11J12, pin 9SFP rate select TXLOW for 1000BASE-SX, HIGH for 10GBASE-SRSFPA_SCLOUTL10J12, pin 5I²C 2-wire serial busMUX in CPLDSFPA_SDAINOUTN9J12, pin 4SFPA_TX_DISOUTM9J12, pin 3SFP transmitter disableHIGH disables transmitterSFPA_TX_FAULTING9J12, pin 2Indicates SFP laser faultHIGH indicates faultVID0_FMC_VADJOUTE10U1, pin 34FMC_VADJ Voltage selectChip internal pulled up
VID1_FMC_VADJOUTJ7U1, pin 33VID2_FMC_VADJOUTL5U1, pin 32VID0INK6S2-1For FMC_VADJ Voltage select
VID1INN5S2-2VID2INN4S2-3FMC_JTAGINL3S2-6Select FMC JTAG portCM0INM3S2-7SoM enable powerCM1INL2S2-8SoM BootmodeCM2INK2S3-1disable SoM pwersequenzingUSR0INK1S3-2FMC VADJ power enablealso if no FMC installedUSB_OCIND9U12, pin 5BUTTONINN6S1Module reset buttonLED1OUTJ5D1user LEDLED2OUTK5D2LED_D4OUTC2D4Status LEDPHY_LED1OUTD12J9Phy LEDs
PHY_LED1ROUTC13J9PHY_LED2OUTB13J9PHY_LED2ROUTC12J9A_00_NINJ10JB1, pin 38SDA IN "three wire" I²CA_00_PINK10JB1, pin 36SCL IN"three wire" I²CA_01_NOUTL12JB1, pin 35TX dataRGPIOA_01_POUTK11JB1, pin 37SDA OUT"three wire" I²CA_02_NINJ12JB1, pin 41RX CLKRGPIOA_02_PINK12JB1, pin 39RX dataRGPIOA_03_NH10JB1, pin 44Module to CPLD communicationcurrently not usedA_03_PJ9JB1, pin 42A_04_NH13JB1, pin 47A_04_PJ13JB1, pin 45A_05_NH8JB1, pin 57A_05_PH9JB1, pin 55A_06_PING13JB1, pin 51A_06_NING12JB1, pin 49I2C GPIO MUX 0I2C MUX also used for FireFlys MSELA_07INL13JB1, pin 34I2C GPIO MUX 1

Functional Description

Power Management

The M3_3VOUT rail of the attached SoM is used to power up the powerrails on TEF1002. further dependencies ar given in the table below:

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anchor	Table_power_management
title	Power Management

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Motor driver PWM signals

CRUVI interface signals are utilized to drive the half bridge PWM motor driver signals. They are logical connected to prevent driving the high and low simultanously:

M_PWM_AH <= '1' when ((A3_N='1') and (A1_P ='0')) else '0';
M_PWM_AL <= '1' when ((A1_P='1') and (A3_N ='0')) else '0';

M_PWM_BH <= '1' when ((A3_P='1') and (A0_P ='0')) else '0';
M_PWM_BL <= '1' when ((A0_P='1') and (A3_P ='0')) else '0';

M_PWM_CH <= '1' when ((A1_N='1') and (A2_N ='0')) else '0';
M_PWM_CL <= '1' when ((A2_N='1') and (A1_N ='0')) else '0';

M_PWM_DH <= '1' when ((A0_N='1') and (A2_P ='0')) else '0';
M_PWM_DL <= '1' when ((A2_P='1') and (A0_N ='0')) else '0';

Motor disable

The M_DISABLE signal set via push button S1 is used to disable all 4 motor drivers. This signal is logical or to the PWM enable signal from B1_P on the CRUVI connector.

M_DISABLE_OUT <= M_DISABLE or not B1_P;

M_DISABLE_A_D <= M_DISABLE_OUT;
M_DISABLE_B_D <= M_DISABLE_OUT;
M_DISABLE_C_D <= M_DISABLE_OUT;
M_DISABLE_D_D <= M_DISABLE_OUT;

The motor disable signal is also forwarded to the CRUVI interface:
A5_P <= M_DISABLE;

Sensor/Encoder, Back EMF

Sensor signals are forwarded to the CRUVI interface:

B2_P <= ENC_A;
B2_N <= ENC_B;
B3_P <= ENC_I;

B3_N <= M_BEMF_B_D;
B4_N <= M_BEMF_A_D;
B4_P <= M_BEMF_C_D;

Current and voltage measurement

Data signals from the 3 ADCs are forwarded to the CRUVI interface:
B5_N <= SD_V;
B5_P <= SD_IA;
A4_P <= SD_IB;

The corresponding clock signals are derived from the CRUVI interface signal B1_N:
SCLK_V_A <= B1_N;
SCLK_A <= B1_N;

Button

Motor disable button

S1 is utilized to switch the motor control on/off. The button is debounced. On press it switches the state of M_DISABLE signal and sets the corresponding LED status.

User Button

User button S2 is forwarded to the CRUVI interface signal A4_N:
A4_N <= BUTTON1;

LEDs

Status LED

The LED D1 is utilized for board status information in the following way

...

Status LED

The Status LED D4 is utilized in the following way:

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anchor	Table_LED_Status
title	Status LED description

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FMC VADJ Power

Three of the dip switches are linked to the voltage selection signals of FMC_VADJ:

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anchor	Table_FMC_VADJ
title	FMC_VADJ selection

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ON

...

ON

...

ON

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SFP control

SFP control signals are handled by RGPIO:

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anchor	Table_SFP_Control
title	Connection SFP Control

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FFA & FFB control

When RGPIO is aktive the FF resets are driven low via rgpio_out_data_i(23).

For FF I2C see I2C chapter. Module Present and Interrupt signals are forwarded to SoM via RGPIO ports:

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anchor	Table_FF_Control
title	Connection FF Control

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PCIE

The PCIexpress signal "PERST#" is forwarded to the SoM using RGPIO port: rgpio_in_data_i(11) <= PCIE_PERST;

JTAG MUX

The folowing table summarizes the JTAG MUX. Only FMC and SoM JTAG have to be handled in the CPLD explicitly. Discrimination between Module CPLD and Module SOC/FPGA are done via hard connected dip switch. Same is true for TEF1002 CPLD MAX10.

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anchor	Table_JTAG
title	JTAG selection

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OFF

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Module control

The module control signals are connected to dip switches:

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anchor	Table_SoM_Control
title	Connection SoM Control

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RESET

The push button signal is connected to the RESIN signal of the SoM (low active reset).

I²C and MUX

The SEL vector is used to select different I2C devices:

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anchor	Table_I2C_SoM
title	Connection I2C to SoM

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A "three wire" I²C interface is used to connect the CPLD I2C to the SoM:

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anchor	Table_I2C_SoM
title	Connection I2C to SoM

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The devices SDA are driven in the following way: DEVICE_XY_SDA <= '0' when SEL= "XY" and A_00_N='0' else 'Z';

The SDA to the SoM is generated by the logical AND connection of all devices: SDAs <= (SFPA_SDA AND FMC_SDA AND FFA_SDA AND FFB_SDA )

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anchor	Table_SC_I2C_MUX
title	SC I2C MUX ports

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PHY LEDs

As soon as the module M3_3VOUT is ready the following signals are used to drive the PHY LEDs.

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anchor	Table_PHY_LEDs
title	Connection of PHY LEDs

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RGPIO

The RGPIO is for communiction betweenn SoC and SC CPLD it handels the signals:

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anchor	Table_RGPIO
title	Signals handeld by RGPIO

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LOW when fault condition, pulled up

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anchor	Table_RGPIO_SoM
title	Connection RGPIO to SoM

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USR LED

User LEDs are accesible via RGPIO:

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anchor	Table_UserLED_LEDsStatus
title	Connection of User LEDs

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Signal VHDLnameFunctionNotesSoC write(19)LED1-user definedSoC write(18)LED2-user defined

Status LED description

Sequenz		Description
ON	LED ON	All OK, motor control disabled
********	continuous blinking	All OK, motor control enabled
ooooooo to ******o	1 to 7 times blinking with a break	currently not used

USR LED

User LED D2 is controlled via the CRUVI signal B0_N:
LED0 <= B0_N;

Appx. A: Change History and Legal Notices

...

Date

Document Revision

CPLD Firmware Revision

Supported PCB Revision

Authors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

Page info

	current-version
	current-version
prefix	v.

REV01

REV01, REV02

Page info

	modified-user
	modified-user

initial version

All

Page info

	modified-users
	modified-users

...

Trenz Electronic Documentation

Versions Compared

Old Version 2

New Version Current

Key

Firmware Revision and supported PCB Revision

Functional Description

Power Management

Motor driver PWM signals

Motor disable

Sensor/Encoder, Back EMF

Current and voltage measurement

Button

Motor disable button

User Button

LEDs

Status LED

Status LED

FMC VADJ Power

SFP control

FFA & FFB control

PCIE

JTAG MUX

Module control

RESET

I²C and MUX

PHY LEDs

RGPIO

USR LED

USR LED

Appx. A: Change History and Legal Notices

Trenz Electronic Documentation

Page History

Versions Compared

Old Version 2

New Version Current

Key

Firmware Revision and supported PCB Revision

Functional Description

Power Management

Motor driver PWM signals

Motor disable

Sensor/Encoder, Back EMF

Current and voltage measurement

Button

Motor disable button

User Button

LEDs

Status LED

Status LED

FMC VADJ Power

SFP control

FFA & FFB control

PCIE

JTAG MUX

Module control

RESET

I2C and MUX

PHY LEDs

RGPIO

USR LED

USR LED

Appx. A: Change History and Legal Notices

I²C and MUX