Page History

Warning
PCN is not ready and TRM style on this page must be checked (style and content)

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Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM"

Template Change history:

Version	Changes	Author
4.2	Changes Xilinx to AMD	ED
4.1	Minor changes Notes Tables	ED
4.0	Rework for smaller TRM which can be generated faster Reduce Signal Interfaces Pin Reduce On Board Periphery Reduce Power Move Configuration Signals from Overview to own section	JH
3.12	Version History changed from list to table all changed title-alignment for tables from left to center	ma
3.11	update "Recommended Operating Conditions" section
3.1	New general notes for temperature range to "Recommended Operating Conditions"
3.02	add again fix table of content with workaround to use it for pdf and wiki Export Link for key features examples Notes for different Types (with and without Main FPGA) Export Link for Signals, Interfaces and Pins examples Notes for different Types (Modul, Modul Hybrid, Evalboard, Carrier)
3.01	remove fix table of content and page layout ( split page layout make trouble with pdf export) changed and add note to signal and interfaces, to on board periphery section ...(not finished)
3.00	→ separation of Carrier/Module and evaluation kit TRM
2.15	add excerpt macro to key features
2.14	add fix table of content add table size as macro

Custom_table_size_100

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Important General Note:

If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template:

Scroll Title

anchor	Figure_anchorname
title-alignment	center
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Table template:
- Layout macro can be use for landscape of large tables

Scroll Title

anchor	Table_tablename
title-alignment	center
title	Text

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Example	Comment
1	2

The anchors of the Scroll Title should be named consistent across TRMs. A incomplete list of examples is given below
- <type>_<main section>_<name>
  - type: Figure, Table
  - main section:
    - "OV" for Overview
    - "SIP" for Signal Interfaces and Pins,
    - "OBP" for On board Peripherals,
    - "PWR" for Power and Power-On Sequence,
    - "B2B" for Board to Board Connector,
    - "TS" for Technical Specification
    - "VCP" for Variants Currently in Production
    - "RH" for Revision History
  - name: custom, some fix names, see below
- Fix names:
  - "Figure_OV_BD" for Block Diagram
  - "Figure_OV_MC" for Main Components
  - "Table_OV_IDS" for Initial Delivery State
  - "Table_PWR_PC" for Power Consumption
  - "Figure_PWR_PD" for Power Distribution
  - "Figure_PWR_PS" for Power Sequence
  - "Figure_PWR_PM" for Power Monitoring
  - "Table_PWR_PR" for Power Rails
  - "Table_PWR_BV" for Bank Voltages
  - "Table_TS_AMR" for Absolute_Maximum_Ratings
  - "Table_TS_ROC" for Recommended_Operating_Conditions
  - "Figure_TS_PD" for Physical_Dimensions
  - "Table_VCP_SO" for TE_Shop_Overview
  - "Table_RH_HRH" for Hardware_Revision_History
  - "Figure_RH_HRN" for Hardware_Revision_Number
  - "Table_RH_DCH" for Document_Change_History
Use Anchor in the document: add link macro and add "#<anchorname>
Refer to Anchor from external : <page url>#<pagename without space characters>-<anchorname>

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-----------------------------------------------------------------------

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Note for Download Link of the Scroll ignore macro:

Link to the base folder of the module (remove de/ or en/ from the URL):
Example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5_Carriers/TE0728/

Scroll Ignore
Download PDF version of this document.

Overview

Trenz Electronic TEM0007 module is an industrial-grade FPGA micromodule integrating a Microsemi Polarfire SoC FPGA, Gigabit Ethernet PHY, USB 2.0 PHY,

...

SPI Flash memory for configuration and operation, and power supply. A large number of configurable I/Os is provided via robust board-to-board (B2B) connectors.

Refer to http://trenz.org/tem0007-info for the current online version of this manual and other available documentation.

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Notes :

short description of the PCB
Short Link of the wiki resources reference:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0728-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Key Features

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Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

→ See examples for different types <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-KeyFeatures

Excerpt
SoC/FPGA

...

...

...

...

...

...

...

...

...

...

...

Industrial-grade Microsemi Polarfire SoC MPFS250T-1FCVG484I

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Block Diagram

...

Notes
¹⁾ Please, take care of the possible assembly options. Furthermore, check whether the power supply is powerful enough for your FPGA design. Attention: IO number connected to B2B connector depends on the used device!
²⁾ Please, take care of the possible assembly options.
³⁾ A higher or lower input voltage may be possible.

Block Diagram

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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.

Note
For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .

Note

Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name.

Example: TE0812 Block Diagram

Note

All created DrawIOs should be named according to the Module name:

Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD

Scroll Title

anchor	Figure_OV_BD
title-alignment	center
title	TEM0007 block diagram

Scroll Ignore

draw.io Diagram

tbstyle
border	true

diagramName	Figure_OV_BD
simpleViewer	true
width
links	auto

...

17

Scroll Only
Image Modified

Main Components

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Notes :

Picture of the PCB (top and bottom side) with labels of important components
Add List below

Note
For more information regarding how to add board photos, Please refer to "Diagram Drawing Guidline" .

Scroll Title

anchor	Figure_OV_MC
title-alignment	center
title	TEM0007 main components

Scroll Ignore

draw.io Diagram

tbstyle
border	true

diagramName	TEM0007_OV_MC
simpleViewer	false
width
links	auto

...

, JM2, JM3
EEPROM, U10
Serial NOR Flash, U3

Initial Delivery State

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Note

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

Scroll Title

anchor	Table_OV_IDS
title-alignment	center
title	Initial delivery state of programmable devices on the module

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Storage device name	Content	Notes
LPDDR4 SDRAM	not programmed
SPI NOR Flash

...

	not programmed besides factory programmed MAC address
System Controller CPLD, U1	Standard firmware	See TEM0007 CPLD.

Signals, Interfaces and Pins

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id	Comments

For subsection examples see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-Signals,InterfacesandPins

Note
Table with all connectors and Designator List of different interfaces per connector IO CNT (for FPGA IOs where functionality can be changed by customer)

Connectors

Scroll Title

anchor	Table_SIP_C
title-alignment	center
title	Board Connectors

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Connector Type	Designator	Interface	IO CNT	Notes

...

hidden	true
id	Comments

you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delete the Test Point section.

Example:

...

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

GPIO	up to 48 SE / 24 DIFF	only 40 SE / 20 DIFF for MPFS025 variants
B2B	JM1	MSSIO	2 x MSSIO
B2B	JM1	I2C or MSSIO	I2C or 2 x MSSIO
B2B	JM1	SDIO or MSSIO	SDIO or 6 x MSSIO
B2B	JM1	UART or MSSIO	2 x UART or 4 x MSSIO
B2B	JM1	ETH - MDI	ETH
B2B	JM2	HSIO	18 SE / 9 DIFF
B2B	JM2	GPIO	up to 36 SE / 18 DIFF	only 8 SE / 4 DIFF for MPFS025 variants
B2B	JM2	CFG	JTAG
B2B	JM3	HSIO	16 SE / 8 DIFF
B2B	JM3	SGMII	1 x SGMII (RX/TX)
B2B	JM3	MGT FPGA	4 x MGT (RX/TX)
B2B	JM3	MGT CLK	2 x MGT CLK
B2B	JM3	USB	USB

Test Points

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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delete the Test Point section.

Example:

Test Point	Signal	Notes¹⁾
TP1	PWR_PL_OK

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Scroll Title

anchor	Table_SIP_TPs
title-alignment	center
title	Test Points Information

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Test Point	Signal	Notes
TP1	+3.3V
TP2	+2.5V
TP3	+2.5V_XCVR
TP4	+1.8V
TP5	-	Signal at U17 pin 3. See schematics.
TP6	+1.1V_LPDDR4
TP7	+1.0V
TP8	VDDAUX1
TP9	AVDD18
TP10	AVDD33
TP11	DVDD1V0
TP12	VCCIOB_SW
TP13	+2.5V_VDDA
TP14	+1.0V_VDDA
TP15	+2.5V_VDD

On-board Peripherals

...

anchor	Table_SIP_TPs
title-alignment	center
title	Test Points Information

...

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

On-board Peripherals

...

hidden	true
id	Comments

Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

Example:

...

B2B connector J1
SoC MIO

...

anchor	Table_OBP
title-alignment	center
title	On board peripherals

...

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id	Comments

For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

Configuration and System Control Signals

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Overview all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
In case it's connected to CPLD always link to CPLD description and add not from the current implementation here(in case it's available)

...

anchor	Table_OV_CNTRL
title-alignment	center
title	Controller signal.

...

Signal Name

...

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

...

Enter the default value for power supply and startup of the module here.

Order of power provided Voltages and Reset/Enable signals

Link to Schematics, for power images or more details

Power Rails

...

hidden	true
id	Comments

List of all power rails which are accessible by the customer

Main Power Rails and Variable Bank Power

Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

Example:

Chip/Interface	Designator	Connected To	Notes
ETH PHY	U10	B2B connector J1 SoC MIO	Gigabit ETH PHY

Scroll Title

anchor	Table_

...

ED: TODO → Following needs to be updated to new TRM style.

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

...

anchor	Table_SIP_B2B
title	General SoC I/O to B2B connectors information

...

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Recommended Power up Sequencing

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List baseboard design hints for final baseboard development.

...

anchor	Table_BB_DH
title-alignment	center
title	Baseboard Design Hints

Chip/Interface	Designator	Connected To
System Controller CPLD	U1	B2B DCDC SoC Power Monitor
Gigabit Ethernet	U7	SoC - MSS B2B - JM1
USB PHY	U11	SoC - MSS B2B -JM3
LPDDR4 SDRAM	U6	SoC - MSS
EEPROM	U10	SoC - MSS
SPI Flash Memory	U3	SoC - MSS
Oscillator	U4	SoC - MSS
Oscillator	U5	Soc - FPGA
Oscillator	U8	ETH PHY
Oscillator	U12	USB PHY

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id	Comments

For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

Configuration and System Control Signals

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hidden	true
id	Comments

Overview all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
In case it's connected to CPLD always link to CPLD description and add not from the current implementation here(in case it's available)

Scroll Title

anchor	Table_OV_CNTRL
title-alignment	center
title	Controller signal.

Scroll Table Layout

orientation	portrait

...

Name	Direction¹⁾	Description
JM1-7	NOSEQ	IN/OUT	See 4 x 5 SoM Integration Guide and TEM0007 CPLD.
JM1-28	SC_EN1	IN	See 4 x 5 SoM Integration Guide and TEM0007 CPLD.
JM1-30	SC_PGOOD	IN/OUT	See 4 x 5 SoM Integration Guide and TEM0007 CPLD.
JM1-32	SC_BOOTMODE	IN	See 4 x 5 SoM Integration Guide and TEM0007 CPLD.
JM1-89	JTAGSEL	IN	See 4 x 5 SoM Integration Guide and TEM0007 CPLD.
JM2-18	SC_nRST	IN	See 4 x 5 SoM Integration Guide and TEM0007 CPLD.
JM2-93 / JM2-95 / JM2-97 / JM2-99	TMS / TDI / TDO / TCK	Signal-dependent	JTAG configuration and debugging interface. JTAG reference voltage: 3.3VIN

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Power and Power-On Sequence

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Enter the default value for power supply and startup of the module here.

Order of power provided Voltages and Reset/Enable signals

Link to Schematics, for power images or more details

Power Rails

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hidden	true
id	Comments

List of all power rails which are accessible by the customer

Main Power Rails and Variable Bank Power

scroll

JTAG Interface

JTAG access to the TEM0007 SoM through B2B connector JM2.

...

JTAG Signal

...

B2B Connector

...

JM2-99

...

Pulled Low: Microsemi Polarfire SoC

Pulled High: Lattice MachXO CPLD

Power Rail Name/ Schematic Name	Connector + Pin	Direction¹⁾	Notes
VIN	JM1.1 / JM1.3 / JM1.5 / JM2.2 / JM2.4 / JM2.6 / JM2.8	IN	Supply voltage from the carrier board
3.3VIN	JM1.13 / JM1.15	IN	Supply voltage from the carrier board
3.3VIN	JM2.91	OUT	JTAG reference voltage
+1.8V	JM1.39	OUT	Internal +1.8V voltage level
VCCIOB	JM2.1 / JM2.3	IN	General purpose I/O bank voltage
VCCIOD	JM2.7 / JM2.9	IN	High speed I/O bank voltage (max. +1.8 V)
+3.3V	JM2.10 / JM2.12	OUT	Internal +3.3 V voltage level

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Recommended Power up Sequencing

Page properties

hidden	true
id	Comments

List baseboard design hints for final baseboard development.

Scroll Title

anchor	Table_BB_DH
title-alignment	center
title	Baseboard Design Hints

UART Interface

The UART interface is connected from the Polarfire SoC to the B2B connector. If this interface is not necessary, these pins can be used for other functionality.

...

anchor	Table_OBP_UART
title	UART interface description

...

SDIO Interface

The SDIO interface is connected from the Polarfire SoC to the B2B connector. If this interface is not necessary, these pins can be used for other functionality.

...

SGMII Interface

The Polarfire Soc provides two SGMII interfaces whereby one interface is connected to the B2B connector.

...

anchor	Table_OBP_SGMII
title	SGMII interface description

...

MSSIO Interface

The MSSIO interface is connected from the Polarfire SoC to the B2B connector.

...

anchor	Table_OBP_MSSIO
title	MSSIO interface description

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	Configuration signal setup.	See Configuration and System Control Signals.
1	3.3VIN	3.3 V (± 5 %)	-	Management and SoC power supply.	Main module power supply for management and SoC. 3 A recommended. Power consumption depends mainly on design and cooling solution.
2	VIN	3.3 V (± 5 %) ¹⁾	-	Main module power supply.	Main module power supply for management and SoC. 5.5 A recommended. Power consumption depends mainly on design and cooling solution.
3	+1.8V	-	-	1.8 V on-module power supply.
4	VCCIOB / VCCIOD	²⁾	-	Module bank voltages.	Enable bank voltages after 1.8 V are available on carrier.

¹⁾ A higher or lower input voltage may be possible.

²⁾ See DS0147 for additional information.

Board to Board Connectors

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This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series,
For example: 6 x 6 SoM LSHM B2B Connectors
Include Page
6 x 6 SoM LSHM B2B Connectors
6 x 6 SoM LSHM B2B Connectors

Include Page

	4 x 5 SoM LSHM B2B Connectors
	4 x 5 SoM LSHM B2B Connectors

Technical Specifications

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id	Comments

List of all power rails which are accessible by the customer

Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)

Absolute Maximum Ratings ^*)

Scroll Title

anchor	Table_TS_AMR
title-alignment	center
title	Absolute maximum ratings

Scroll Table Layout

sortDirection
orientation	portrait

...

anchor	Figure_TS_PD
title	Physical Dimension

...

Scroll Only

scroll-pdf	true
scroll-office	true
scroll-chm	true
scroll-docbook	true
scroll-eclipsehelp	true
scroll-epub	true
scroll-html	true

Image Removed

Currently Offered Variants

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MGT Lanes

There are four MGT (Multi Gigabit Transceiver) lanes and two clocks connected between the B2B connector JM3 and the Polarfire SoC bank 5. Each MGT lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, signal schematic name, and board-to-board pin connection:

...

anchor	Table_SIP_MGT
title	MGT Lanes Connection

...

Lane

...

Schematic

...

Gigabit Ethernet

On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY SGMII interface is connected to the Polarfire SoC.

...

anchor	Table_OBP_ETH
title	Gigabit Ethernet pin description

...

System Controller CPLD I/O Pins

The System Controller CPLD (U1) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.

...

hidden	true
id	Comments

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

...

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

...

anchor	Table_OBP_SC
title	System Controller CPLD special purpose pin description

...

- 11

...

USB Interface

USB PHY is provided by Microchip USB3320. The ULPI interface is connected to the Polarfire SoC. I/O voltage is fixed at 3.3 V. Reference clock input for the USB PHY is supplied by the on-board 52.00 MHz oscillator (U12).

...

anchor	Table_OBP_USB
title	General Overview of the USB PHY Signals

...

DP - 18,

...

OTG-D_P

...

Test Points

...

anchor	Table_OBP_TestPoints
title	Test Points Information

...

On-board Peripherals

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id	Comments

Notes :

add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs

Page properties

hidden	true
id	Comments

Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

...

anchor	Table_OBP
title	On board peripherals

...

System Controller CPLD

The System Controller CPLD (U1) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.

Gigabit Ethernet

On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U7). The Ethernet PHY SGMII interface is connected to the Polarfire SoC. The reference clock input of the PHY is supplied from an on-board 25.00 MHz oscillator (U8).

...

anchor	Table_OBP_ETH
title	Ethernet PHY to Polarfire SoC connections

...

Bank 5 - N6

...

SGMII0_IN_P

...

U7 - 1

...

Bank 5 - L5

...

SGMII0_OUT_P

...

U7 - 4

...

USB PHY

Hi-speed USB ULPI PHY (U11) is provided with USB3320 from Microchip. The ULPI interface is connected to the Polarfire SoC via MSSIO14...25 bank 2. The I/O voltage is fixed at 3.3 V and PHY reference clock input is supplied from the on-board 52.00 MHz oscillator (U12).

...

anchor	Table_OBP_USB
title	USB PHY to Polarfire SoC connections

...

U2 - G4

...

OTG-STP

...

U11 - 29

...

U2 - F1

...

OTG-DIR

...

U11 - 31

...

OTG_DATA0

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LPDDR4 SDRAM

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id	Comments

Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TEM0007 SoM has a one GByte volatile LPDDR4 SDRAM IC for storing user application code and data.

Part number: IS43LQ32256A-062BLI
Supply voltage: +1.8 V / +1.1 V
Speed: 1600 MHz
Temperature: Industrial (-40°C to +85°C)

EEPROM

There is a 2 Kbit EEPROM provided on the module TEM0007 with a pre-programmed globally unique MAC.

...

anchor	Table_OBP_EEP
title	I2C EEPROM interface MSSIOs and pins

...

anchor	Table_OBP_I2C_EEPROM
title	I2C address for EEPROM

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SPI Flash Memory

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id	Comments

Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

The TEM0007 is equipped with a MT25QU512ABB8E12-0SIT flash memory chip, U3, which provided storage for FPGA configuration files. After configuration, the remaining free memory can be used for application data storage.

...

anchor	Table_OBP_SPI
title	SPI Flash interface pins

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Oscillators

...

anchor	Table_OBP_CLK
title	Osillators

...

Power and Power-On Sequence

...

hidden	true
id	Comments

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

Power on-sequence
Power distribution
Voltage monitoring circuit

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Power Supply

Power supply with minimum current capability of 3 A for system startup is recommended.

Power Consumption

...

anchor	Table_PWR_PC
title	Power Consumption

...

* TBD - To Be Determined

Power Distribution Dependencies

...

anchor	Figure_PWR_PD
title	Power Distribution

...

Scroll Only
Image Removed

Power-On Sequence

The power sequence is the recommended one. The final sequence depends on the system controller.

...

anchor	Figure_PWR_PS
title	Power Sequency

...

Scroll Only
Image Removed

Voltage Monitor Circuit

The TEM0007 delivers two voltage monitor circuits. The first circuit is responsible for the selection of voltage "VDDAUX1". This voltage is selected on the basis of the voltage of "VCCIOB". If "VCCIOB" is higher than 2.9 V, "VDDAUX1" should be +3.3 V. If it is smaller, "VDDAX1" should be +2.5 V. The second circuit monitors the +1.0 V power rail. According to this rail, the reset is set/unset to realize a brown-out detection. Furthermore, a possibility for a manual reset is available.

...

anchor	Figure_PWR_VMC
title	Voltage Monitor Circuit

...

Scroll Only
Image Removed

Power Rails

...

anchor	Table_PWR_PR
title	Module power rails.

...

B2B Connector

JM1 Pin

...

B2B Connector

JM2 Pin

...

VCCIOB

...

Bank Voltages

...

anchor	Table_PWR_BV
title	Polarfire SoC bank voltages.

...

Bank

...

Voltage

...

VCCIOB

...

hidden	true
id	Comments

...

use "include page" macro and link to the general B2B connector page of the module series,

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Technical Specifications

Absolute Maximum Ratings

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VCCIOB

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Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

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VCCIOB

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Physical Dimensions

Module size: 40 mm × 50 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm.

PCB thickness: 1.74 mm.

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id	Comments

In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Power Rail Name/ Schematic Name	Description	Min	Max	Unit
VIN	Supply voltage	-0.3	6.0	V
3.3VIN	Supply voltage	-0.3	3.75	V
VCCIOB	I/O bank voltage	-0.5	3.6	V
VCCIOD	I/O bank voltage	-0.5	2.0	V

^*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

This TRM is generic for all variants. Temperature range can be differ depending on the assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Variants of modules are described here: Article Number Information
Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.

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Parameter	Min	Max	Units	Reference Document
VIN	3.135	3.465	V
3.3VIN	3.135	3.465	V
VCCIOB	1.14	3.465	V	See FPGA datasheet.
VCCIOD	1.14	1.89	V	See FPGA datasheet.

¹⁾ Higher and lower values may be possible. For more information consult schematic and according datasheets.

Physical Dimensions

Module size: 40 mm × 50 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm.

PCB thickness: 1.74 mm.

Page properties

hidden	true
id	Comments

In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guideline" .

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title	Physical Dimension

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draw.io Diagram

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Currently Offered Variants

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id	Comments

Set correct link to the shop page overview table of the product on English and German.

Example for TE0706:

ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706

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Trenz shop TEM0007 overview page
English page	German page

Revision History

Hardware Revision History

...

Example for TE0728:

ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

...

For Baseboards or modules, where no overview page is available (and revision number is coded in the direct link) use shop search link, e.g. TE0706:

ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

Date format: YYYY-MM-DD
Example:
Date Revision Changes Documentation Link
2020-11-25 REV02
Resistors R14 and R15 was replaced by 953R (was 5K1)
Resistor R5 was replaced by 5K1, R8 by 953R (was 9K09 and 1K69 respectively)
REV02

...

Revision History

Hardware Revision History

...

hidden	true
id	Comments

Set correct links to download arrier, e.g. TE0706 REV02:

TE0706-02 -> https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

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title	Board hardware revision number.

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draw.io Diagram

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Date	Revision	Changes	Documentation Link
2020-05-26	01	Inital Release

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title	Board hardware revision number.

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dash.

Document Change History

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Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
- Add new row below first
- Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
- Metadata is only used of compatibility of older exports

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Date

Revision

Contributor

Description

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Link fixed

2023-11-07

v.45

ED

Initial Release

--

all

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--

Disclaimer

Include Page

	IN:Legal Notices
	IN:Legal Notices

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Trenz Electronic Documentation

Page History

Versions Compared

Old Version 21

New Version Current

Key

Overview

Key Features

Block Diagram

Block Diagram

Main Components

Initial Delivery State

Signals, Interfaces and Pins

Connectors

Test Points

On-board Peripherals

On-board Peripherals

Configuration and System Control Signals

Page propertieshiddentrueidComments

Power Rails

ED: TODO → Following needs to be updated to new TRM style.

Board to Board (B2B) I/Os

Recommended Power up Sequencing

System Controller CPLD

Gigabit Ethernet

USB PHY

LPDDR4 SDRAM

EEPROM

SPI Flash Memory

Oscillator

Configuration and System Control Signals

Power and Power-On Sequence

Power Rails

JTAG Interface

Recommended Power up Sequencing

UART Interface

SDIO Interface

SGMII Interface

MSSIO Interface

Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings *)

Currently Offered Variants

MGT Lanes

Gigabit Ethernet

System Controller CPLD I/O Pins

USB Interface

Test Points

On-board Peripherals

System Controller CPLD

Gigabit Ethernet

USB PHY

LPDDR4 SDRAM

EEPROM

SPI Flash Memory

Oscillators

Power and Power-On Sequence

Power Supply

Power Consumption

Power Distribution Dependencies

Power-On Sequence

Voltage Monitor Circuit

Power Rails

Bank Voltages

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Physical Dimensions

Recommended Operating Conditions

Physical Dimensions

Currently Offered Variants

Revision History

Hardware Revision History

Revision History

Hardware Revision History

Document Change History

Disclaimer

Table of contents

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Absolute Maximum Ratings ^*)