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Refer to httpshttp://wiki.trenz-electronic.de/display/PD/<name>org/te0724-info for the current online version of this manual and other available documentation.

The Trenz Electronic TE0724 is an industrial-grade SoC module based on Xilinx Zynq - 7010/7020, which provides a dual core ARM Cortex A9 and a 7-series FPGA logic. It provides a gigabit ethernet transceiver, 1GByte 1 GByte of DDR3L SDRAM, 32 64 MByte Flash memory as configration and data storage. it It includes strong pwerregulators power regulators for all needed voltages and a robust high-speed connector for in- and outputs. It has a 6 x 4 cm form factor.

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Xilinx Zynq XC7Z010-1CLG400I or XC7Z020-1CLG400I

Dual-core ARM Cortex-A9 MPCore
Max. 667 MHz

Shock proof and vibration resistant
Size 6 x 4 cm
Plug-On-Modul with 1 × 160 Pin High-Speed connector
1 GByte DDR3L SDRAM
32 64 MByte QSPI Flash Speicher
1 x GBit Ethernet PHY
1 x MAC-Address EEPROM
128 KBit EEPROM
1 x CAN Transceiver
On-Board DC/DC-regulators
Excellent signal integrity due to well dirstributed evenly-spread supply pins

Additional assembly options are available for cost or performance optimization upon request.

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XILINX ZYNQ XC7Z020-2CLG400C, U1
Gigabit Ethernet Transceiver Alaska 88E1512, U7
Power Manager Dialog DA9062, U4
1GByte - 2x 4Gbit DDR3L RAM, U3, U5
32MByte Spansion 64MByte ISSI SPI Flash S25FL256IS25LP512M, U13
128KByte Serial EEPROM Microchip 24AA, U10
CAN Transceiver MCP2542FDT, U2
160 Pin Samtec B2B Connector ST5-80-1.50-L-D-P-TR, J1

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Storage device name	Content	Notes
Spansion ISSI SPI Flash S25FL256IS25LP512M, U13	Empty
DA9062, U4	Programmed
Microchip 24AA128T, U10	Empty	USER EEPROM
Microchip 24AA025E48T, U23	MAC write protected preprogrammed, User area empty	EEPROM for MAC-Address.

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Boot mode is selected via two Mode pins at B2B connector J2. By default the TE0724 supports JTAG and SPI Boot Mode. Connecting a SD Card via B2B connector to MIO Pins (See SD Card Interface) gives the possibility to boot from SD Card. The Mode pins are pulled up at the module.

Boot mode	MODE1 J1-2	MODE0 J1-4
JTAG (cascade)	LOW	LOW
invalid	LOW	HIGH
SPI	HIGH	LOW
SD CARD (not on module)	HIGH	HIGH

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All PS MIO banks as well as PL bank 34 are powered by on-module DC-DC power rails. Valid VCCO_35 for PL bank 35 should be supplied from via the carrier boardB2B connector.

For detailed information about the pin out, please refer to the Pin-out Tables.

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On-board QSPI flash memory (U13) on the TE0724-02 04 is a SPANSION S25FL256S ISSI IS25LP512M with 256 512 Mbit (32 64 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

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A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I²C bus with slave device address 0x53.

Note
Max. I2C Speed for 24AA025E48 EEPROM is 100kHz.

USER EEPROM

A Microchip 24AA128T serial EEPROM (U10) is availabe available for e.g. module idetification identification and user Data. The device has 128Kbit memory with max 64 bytes page write capability. It is accessible over I²C bus with slave device address 0x50.

Note
Max. I2C Speed for 24AA128T EEPROM is 100kHz.

Oscillators

The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

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LED	Color	Connected to	Description and Notes
D1	Green	PS MIO7	User LED.
D2	Green	PL IO_L3P_T0_34	User LED.
D3	Red	PL IO_L4N_T0_34	User LED.

Table 11: On-board LEDs.

Power and Power-On Sequence

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Power Consumption

The maximum power consumption of a module mainly depends on the design running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

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Table 12: Typical power consumption.

* TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of ...A for system startup is recommended.

The on-board voltages of the TE0724 SoC module will be powered-up in order of a determined sequence after the external voltages VIN is available and nONKEY is asserted.

Warning
To avoid any damage to the module, check for stabilized on-board voltages should be carried out (i.e. power good and enable signals) before powering up any SoC's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence.

Power Distribution Dependencies

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anchor	PD_TE0724
title	Figure 4: TE0724 power distribution diagram.

Pin Header

Optional assembled Pin Header J2 can be used for PMIC In-System Programming.

Pin	Signal	B2B
J2-1	VIN	J1-154, J1-156, J1-158, J1-160
J2-2	GND
J2-3	I2C_SCL	J1-142
J2-4	I2C_SDA	J1-144
J2-5	ONKEY	J1-148
J2-6	PWR_TP	J1-146

Table 12: Optional assembled Pin Header.

Power and Power-On Sequence

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Power Consumption

The maximum power consumption of a module mainly depends on the design running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power Input	Typical Current
VIN	TBD*

Table 13: Typical power consumption.

* TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of ...A for system startup is recommended.

The on-board voltages of the TE0724 SoC module will be powered-up in order of a determined sequence after the external voltages VIN is available and nONKEY is asserted.

Warning
To avoid any damage to the module, check for stabilized on-board voltages should be carried out (i.e. power good and enable signals) before powering up any SoC's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence.

Power Distribution Dependencies

DCDC U8 component is either TPS82140 (2 A) or MUN12A (3 A) depending on the variant.

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title	Figure 3: TE0724 power distribution

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See Xilinx data sheet for additional information. User should also check related base board documentation when intending base board design for TE0724 module.

Power-On Sequence

The TE07024 SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages. For a detailed description of the configurabel Power Management IC please refer to the datasheet of dialog semicondutor DA9062.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

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anchor	PS_TE0724
title	Figure 5: TE0724 Module power-on diagram.

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Power Rails

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Power Rail Name

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B2B JM1 Pins

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Direction

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VBAT

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See Xilinx data sheet for additional information. User should also check related base board documentation when intending base board design for TE0724 module.

Power-On Sequence

The TE0724 SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages. For a detailed description of the configurable Power Management IC please refer to the datasheet of dialog semicondutor DA9062.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in ascending order as listed in the blocks of the diagram:

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anchor	PS_TE0724
title	Figure 4: TE0724 Module power-on diagram.

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Power Rails

Power Rail Name	B2B JM1 Pins	Direction	Notes
VIN	154, 156, 158,160	Input	Main supply voltage from the carrier board.
VCCIO_35	54	Input	PL Bank 35 supply voltage.
VLDO1	83	Output	3.3V (100mA)
VLDO2	94	Output	1.8V (300mA)
VLDO34	53	Output	2.5V (600mA)
3.3V	43, 74	Output	Additional module on-board 3.3V voltage supply (2 A or 3 A variant dependent).
1.0V	-		Buck1 & Buck2 of U4.
1.8V	63	Output	Buck3 of U4.
VDD_DDR	-		DDR supply voltage powered by Buck4 of U4.
VBAT	152	Output/Input	Battery charger (out) and supply for RTC and 32kHz crystal (in).

Table 14: Module power rails.

Current rating of theSamtec connector is 1.6A per pin (1 pin powered per row).

Bank Voltages

Bank	Schematic Name	Voltage	Voltage Range
500 MIO	3.3V	3.3V	-
501 MIO	1.8V	1.8V	-
502 DDR3	VDD_DDRV	1.35V	-
34 HR	3.3V	3.3V	-
35 HR	VCCIO_35	User	1.2V to 3.3V

Table 15: Module PL I/O bank voltages.

Board to Board Connectors

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This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, for example: 4 x 5 SoM LSHM B2B Connectors

Include Page

	4 x 6 SoM SS5/ST5 B2B Connectors
	4 x 6 SoM SS5/ST5 B2B Connectors

Variants Currently In Production

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Trenz shop TE0724 overview page
English page	German page

Technical Specifications

Absolute Maximum Ratings

Parameter	Min	Max	Units	Reference Document
VIN supply voltage	-0.3	5.5	V	da9062_3v4.pdf
Storage temperature	-40	85	°C	-

Table 18: Module absolute maximum ratings.

Note
Assembly variants for higher storage temperature range are available on request.

Recommended Operating Conditions

Parameter	Min	Max	Units
VIN supply voltage (variant "-Z" with MUN12A for U8)	4.5	5.5	V
VIN supply voltage (all other variants)	3.6	5.5	V
Operating temperature	-40	85	°C

Table 19: Module recommended operating conditions.

Note
Please check Xilinx datasheet ... for complete list of absolute maximum and recommended operating ratings.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Extended grade: 0°C to +85°C.

Industrial grade: -40°C to +85°C.

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

Module size: 60 mm × 40 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 5.0 mm.
PCB thickness: 1.6 mm.
Highest part on PCB: approx. 1.6 mm. Please download the step model for exact numbers.

All dimensions are given in millimeters.

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title	Figure 5: TE0724 Mechanical Dimensions.

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Revision History

Hardware Revision History

Date	Revision	Notes
2020-11-05	04	Changed DDR3, Flash, see PCN
2019-03-12	03	changed 3.3V DCDC
	02A	Electrical same as REV 02.
	02	First production release
-	01	Prototypes

Table 20: Module hardware revision history.

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

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title	Figure 6: TE0724 module hardware revision number.

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Document Change History

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Date

Revision

Contributors

Description

Page info

infoType	Modified date
dateFormat	yyyy-MM-dd
type	Flat

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infoType	Current version
dateFormat	yyyy-MM-dd
prefix	v.
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infoType	Modified by
dateFormat	yyyy-MM-dd
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update for "-Z" variant (MUN12A)

2020-11-17

v.58

Martin Rohrmüller

update to REV04 (DDR, Flash)

2019-10-31

v.56

Martin Rohrmüller

VBAT is In/OUT (charger)

2019-10-30

v.55

John Hartfield

correction on power section

2019-06-27

v.54

Martin Rohrmüller

Updated Power Distribution dependencies Figure (VBAT: Charge and Use)

2019-06-11

v.53

Guillermo Herrera

typo correction on Bank voltage section

2019-03-29

v.51

Martin Rohrmüller

update to REV03

2018-11-20

v.44

John Hartfiel

remove typo

2018-10-10

v.43

John Hartfiel

Add notes to EEPROM section

2018-10-09

v.42

Martin Rohrmüller

corrected mating high at physical dimensions

2018-10-01

v.41

Martin Rohrmüller

corrected typo in power up order
updated B2B power rating

2018-09-21

v.39

Martin Rohrmüller

B2B Connectors as include from general page

2018-07-20

v.37

John Hartfield

small style changes

2018-07-06

v.34

Martin Rohrmüller

Initial document.

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Table 13: Module power rails.

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Bank Voltages

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Bank

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Voltage

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Voltage Range

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Table 14: Module PL I/O bank voltages.

Board to Board Connectors

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Variants Currently In Production

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Technical Specifications

Absolute Maximum Ratings

...

Parameter

...

Units

...

Reference Document

...

VIN supply voltage

...

V

...

Storage temperature

...

-40

...

°C

...

Table 15: Module absolute maximum ratings.

Note
Assembly variants for higher storage temperature range are available on request.

Recommended Operating Conditions

...

Table 16: Module recommended operating conditions.

Note
Please check Xilinx datasheet ... for complete list of absolute maximum and recommended operating ratings.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Extended grade: 0°C to +85°C.

Industrial grade: -40°C to +85°C.

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

Module size: ... mm × ... mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ... mm.
PCB thickness: ... mm.
Highest part on PCB: approx. ... mm. Please download the step model for exact numbers.

All dimensions are given in millimeters.

Put mechanical drawings here...

Figure : Module physical dimensions drawing.

Revision History

Hardware Revision History

...

Notes

...

01

...

Prototypes

...

Table : Module hardware revision history.

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Put picture of actual PCB showing model and hardware revision number here...

Figure : Module hardware revision number.

Document Change History

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2.Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number
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Current version

Date	Revision	Contributors	Description

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Trenz Electronic Documentation

Versions Compared

Old Version 22

New Version Current

Key

USER EEPROM

Oscillators

Power and Power-On Sequence

Power Consumption

Power Distribution Dependencies

Pin Header

Power and Power-On Sequence

Power Consumption

Power Distribution Dependencies

Power-On Sequence

Power Rails

Power-On Sequence

Power Rails

Bank Voltages

Board to Board Connectors

Variants Currently In Production

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Operating Temperature Ranges

Physical Dimensions

Revision History

Hardware Revision History

Document Change History

Bank Voltages

Board to Board Connectors

Variants Currently In Production

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Operating Temperature Ranges

Physical Dimensions

Revision History

Hardware Revision History

Document Change History