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Trenz Electronic TE0728 is an automotive-grade FPGA module integrating a Xilinx Automotive an Automotive Xilinx Zynq-7020 7 FPGA, two 100 Mbit Ethernet transceivers (PHY) , 512 MByte DDR3L SDRAM, 16 MByte DDR3 SDRAM, QSPI Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips.
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- Xilinx
XA7Z020- XC7Z020-1CLG484Q (Automotive)
- Rugged for shock and high vibration
- Dimensions: 6 x 6 cm
Temperature range: Automotive- [XA7Z014S is available on other assembly options]
- Package: CL/CLG484
- Speed Grade: -1
- Temperature Grade: Expanded (-40 to +128 °C)
- Dual-Core ARM Cortex-A9 MPCore
- 2 x 100 MBit Ethernet transceiver (PHY)
- 512 MByte DDR3L SDRAM, 16-bit-wide
- DDR3 SDRAM, up to 512MB, up to 1066 Mb/s, connected to PS [different size is available on other assembly options]
16 MByte - QSPI Flash memory (with XiP support)
- Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
76 single ended I/O, 24 LVDS pairs (48 I/O) and 42 MIO available on board-to-board connectors- [different size is available on other assembly options]
- Programmable SIT8918A , PS clock generator
- 2 Kbit serial EEPROM
- Three user LEDs
- CAN transceiver (PHY)
- 12 V power supply with watchdog
- On-board high-efficiency DC-DC converters
- System management and power sequencing
- eFUSE bit-stream encryption
- AES bit-stream encryption
- Temperature compensated RTC (real-time clock)
- Three user LEDs
- Evenly-spread supply pins for good signal integrity
Other assembly options for cost or performance optimization plus high volume prices available on request.
Depending on the customer design, additional cooling might be required.
Block Diagram
- 2 x 100 MBit Ethernet transceiver (PHY)
- Board to Board (B2B)
- Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
- I/O Interface
- 42x MIO
- 200x HR
- 128x PS IO
- 0x GTP Transceiver
- 0x GTX Transceiver
- Power Supply
- 12 V power supply with watchdog
- Others:
- Dimensions: 6 x 6 cm
- Rugged for shock and high vibration
- On-board high-efficiency DC-DC converters
- System management and power sequencing
- eFUSE bit-stream encryption
- AES bit-stream encryption
- Evenly-spread supply pins for good signal integrity
Block Diagram
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Main Components
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- Add List below
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| Image Modified
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- 512 MByte DDR3 SDRAM, Cypress DDR3 Memory, U1
- Xilinx Automotive XA7Z020-1CLG484Q ,U2
- 100 MBit Ethernet transceiver DP83848transceiver, U3
- 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U4
- Standard Clock Oscillators @ 25MHz 3.3V, SiTime SiT1618AA, U5
- 1.5 A Low Dropout Linear Regulator, Texas Instruments, TPS74801-Q1, U6
- Real Time Clock, Micro Crystal @32.768 MHz, 3.3V, RV-3029-C3, U7
- 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U8
- 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U9
- 100 MBit Ethernet transceiver DP83848MPHPEP, U10
- 64 Kbit I2C EEPROM, 24LC64, U11
- Low-Quiescent-Current Proggrammable Delay Supervisory Circuit, Texas Instruments TPS3808G01-Q1, U12
- 16 MByte QSPI Nor Flash memory, Cypress S25FL127, U13
- Standard Clock Oscillators @ 50MHz 3.3V, SiTime SiT8918AA, U14
- Low-Quiescent-Current Priggrammable Delay Supervisory Circuit, Texas Instruments TPS3808G01-Q1, U15
- CAN Tranceiver, Texas Instruments SN65HVD230Q1, U16
- B2B connector Samtec Micro Tiger Eye Connector SEM-140-02-03, JM2
- B2B connector Samtec Micro Tiger Eye Connector SEM-140-02-03, JM3
- B2B connector Samtec Micro Tiger Eye Connector SEM-140-02-03, JM1
- User LED Green
Initial Delivery State
- 100 MBit Ethernet transceiver, U10
- User LED Green, D4
- Real Time Clock, U7
- Standard Clock Oscillators, U5
- 64 Kbit I2C EEPROM, U11
- CAN Tranceiver, U16
- QSPI NOR Flash memory, U13
- Standard Clock Oscillators, U14
- Low-Quiescent-Current Programmable Delay Supervisory Circuit, U15
- Low-Quiescent-Current Programmable Delay Supervisory Circuit, U12
- B2B connector , JM2
- B2B connector , JM3
- B2B connector , JM1
FPGA (U2), DDR3 SDRAM (U1) and QSPI (U13) can be varied on other assembly option, for more information contact us.
Initial Delivery State
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device nameDevice | Symbol | Content |
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Quad SPI Flash | U13 | Empty24xx64 |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables,
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Signal | FPGA Bank | Pin | B2BMIO pin | Signal State | Boot Mode |
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Boot_R | 500 | E4 | J2-11 | MIO4 | Low | QSPI | MIO4 | High | SD Card |
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Zynq-7020SoC includes a reset that is driven by the reset system. Hardware resets are driven by the power-on reset signal (PS_POR_B) and the system reset signal (PS_SRST_B).
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FPGA Bank | Pin | B2B | PS_POR_B | 500 | B5 | JM2-9 | PS_SRST_B | 501 | C9 | JM2-2 | B2B | I/O | Note |
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Reset | J2-7 | Input | Comes from Carrier | RST_OUT | J2-9 | Output | PS_PROB_B |
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Signals, Interfaces and Pins
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Board to Board (B2B) I/Os
TE0728 Module has 3 B2B connectors and every connector has 80 pins (2 row, 40 pins).
FPGA bank number and number of I/O signals connected to the B2B connector:
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FPGA Bank | Type | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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13 | HR | JM1J1 | 48 Single ended (24 Diff) | VCCO_13 | variable from carrier | 500 | JM1MIO | J1 | 4 Singel ended | 3.3V |
| 501 | MIO | J2 | 38 Singel ended | VMIO1 | variable from carrier | 33 | HR | JM3J3 | 34 Single ended (17 Diff) | 3.3V |
| 35 | JM3203.3V | 35 | JM2 | J2 | 20 Single ended (10 Diff) 22 Single ended (11 Diff) | 22501 | JM2 | 38 | VMIO1 | MIO1 VREF is connected to resistor divider to support HSTL18 | |
JTAG Interface
Ethernet PHY
Ethernet pins connections to Board to Board (B2B). Ethernet components ETH1 and ETH2 are connected to B2B connector J3JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.
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title | JTAG pins connectionEthernet PHY B2B connectors. |
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JTAG Signal | B2B Pin |
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TMS | JM2-12 |
TDI | JM2-10 |
TDO | JM2-8 |
TCK | JM2-6 |
MIO Pins
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title | MIOs pins |
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UART
There is no fixed mapping for PS7 UART, if needed it can be mapped to free pins from MIO1 Bank or via EMIO to PL pins.
Recommended mapping for primary (console, debug) UART are MIO52, MIO53.
On-board Peripherals
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Notes :
Schematic | ETH1 | ETH2 | Direction | Notes |
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CTREF | J3-57 | J3-25 | In | Magnetics center tap voltage | TD+ | J3-58 | J3-28 | Out | Transfer | TD- | J3-56 | J3-26 | Out |
| RD+ | J3-52 | J3-22 | In | Receive | RD- | J3-50 | J3-20 | In |
| LED1 | J3-55 | J3-23 | Out | LED Yellow on carrier, multiple usage-ACK | LED2 | J3-53 | J3-21 | Out |
| LED3 | J3-51 | J3-19 | Out | LED Green on carrier, multiple usage-Link | POWERDOWN/INT | L21 | R20 | In |
| RESET_N | M15 | R16 | In | Active low PHY Reset |
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CAN PHY
CAN pins connections to Board to Board (B2B).
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Schematic | B2B | Direction | Notes |
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CANH/CANL | J1-2/J1-4 | Inout/Inout |
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JTAG Interface
JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.
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JTAG Signal | B2B Pin |
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TMS | J2-12 | TDI | J2-10 | TDO | J2-8 | TCK | J2-6 |
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MIO Pins
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Chip/Interface | Product | Notes |
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SPI Flash | U13 | 16 MByte Flash |
EEPROM | U11 | 64 Kbit EEPROM |
RTC | U7 | Real Time Clock |
DDR3 SDRAM | U1 | Volatile Memory |
Ethernet | U3, U10 | CAN Transceiver | U16 | User LED | D4 | Green LED |
Quad SPI Flash Memory
On-board QSPI flash memory is used to store initial FPGA configuration. Datasheet is provided in Texas Instruments. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500.
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title | Quad SPI interface MIOs and pins |
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MIO Pin | Connected to | B2B | Notes |
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MIO0 | MIO0 | - | RTC interrupt | MIO1...MIO6 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | - | SPI Flash | MIO7 | LED RED | - | LED | MIO8/MIO9 | Tx/Rx | - | CAN Transceiver | MIO10...MIO13 | IO_0 ... IO_3 | J1 | GPIO | MIO14/MIO15 | SCL/SDA | - | I2C | MIO16...MIO39 | - | J2 | GPIO | MIO40...MIO48 | CLK, Cmd, Data0...Data3, wp, cd | J2 | SD | MIO48 | PS_MIO48_501 | J2 | LED Red on Carrier | MIO49 | PS_MIO49_501 | J2 | LED Yellow on Carrier | MIO50 | PS_MIO49_501 | J2 | LED Green on Carrier | MIO51 | PS_MIO51_501 | J2 | GPIO | MIO52/MIO53 | UART_Txd / UART_Rxd | J2 | UART transfer/recieve |
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On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transceiver PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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RTC
The RTC has an I2C Bus (2-wire SerialInterface) and offers temperature compensated time. The STC-Smart Temperature Compensation is calibrated in the factory and leads to a very high time-accuracy.
RTC intruppt is connected to MIO0 connected to Bank 500, pin G6.
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MIO Pin | Schematic | Pin | Notes |
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MIO15 | SDA | U7-5 | On-board RTC, and EEPROM |
MIO14 | SCL | U7-4 | On-board RTC, and EEPROM |
EEPROM
Quad SPI Flash Memory
On-board QSPI flash memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency.
Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500The Microchip Technology Inc. 24xx64 is a 64 Kbit Electrically Erasable PROM. The device is organized as a single block of 8K x 8-bit memory with a 2-wire serial interface. Lowvoltage design permits operation down to 1.7V, with standby and active currents of only 1 μA and 3 mA, respectively. It has been developed for advanced, lowpower applications such as personal communications or data acquisition. The 24xx64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space.
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title | I2C EEPROM Quad SPI interface MIOs and pins |
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PinMIO15SDA | U11-3 | On-board RTC, and EEPROM | MIO14 | SCL | U11-1 | On-board RTC, and EEPROM | |
LEDs
SPI_CS |
| MIO2 | SPI_DQ0/M0 |
| MIO3 | SPI_DQ1/M1 |
| MIO4 | SPI_DQ2/M2 |
| MIO5 | SPI_DQ3/M3 |
| MIO6 | SPI_SCK/M4 |
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RTC
The RTC has an I2C Bus (2-wire SerialInterface) and offers temperature compensated time. The STC-Smart Temperature Compensation is calibrated in the factory and leads to a very high time-accuracy.
RTC interrupt is connected to MIO0 connected to Bank 500 through pin G6.
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title | I2C Address for RTC |
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SchematicColorConnected toActive Level | IO Standard | D9 | Green | DONE | Low | not applicable | D8 | RED | MIO7 | High | not applicable | D4 | Green | Bank 33 - V18 | High | LVCMOS33 | |
DDR3 SDRAM
The TE0728 SoM has two 512 MByte volatile DDR3 SDRAM IC for storing user application code and data.
Configuration of the DDR3 memory controller in the FPGA should be done using the MIG tool in the Xilinx Vivado Design Suite IP catalog.
Ethernet
There are two 100 MBit Extreme Temperature Ethernet provided by Texas Instrument on the board. Datasheet is provided TI website. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz source is provided from MEMS Oscillator. There is no sharing of signals for the two PHY's.
PUDC pin is connected with pull-up to 3.3V those pre-configuration pull-ups are disabled by default. Strapping resistor exist to change the PUDC mode.
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MIO14...15 | 0x56 | U7 | Slave address |
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EEPROM
The Microchip Technology Inc. 24xx64 is a 64 Kbit Electrically Erasable PROM. The device is organized as a single block of 8K x 8-bit memory with a 2-wire serial interface. The 24xx64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space.
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title | I2C address for EEPROM |
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MIO Pin | I2C Address | Designator | Notes |
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MIO14...15 | 0x50 | U11 | Slave address |
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LEDs
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title | Ethernet PHY to Zynq SoC connectionsOn-board LEDs |
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SchematicETH1ETH2PullupNotesCTREFJ3-57 | J3-25 | Magnetics center tap voltage | TD+ | J3-58 | J3-28 | on-board | TD- | J3-56 | J3-26 | on-board | RD+ | J3-52 | J3-22 | on-board | RD- | J3-50 | J3-20 | on-board | LED1 | J3-55 | J3-23 | on-board | LED2 | J3-53 | J3-21 | on-board | LED3 | J3-51 | J3-19 | on-board | POWERDOWN/INT | L21 | R20 | on-chip | It is recommended to configure FPGA I/O as input with Pullup or as output driving 1 if Interrupt not used. | RESET_N | M15 | R16 | on-chip | It is recommended to configure FPGA I/O as input with Pullup or as output (active low PHY Reset). | |
CAN Transceiver
DONE | Low | D8 | RED | MIO7 | High | D4 | Green | Bank 33 - V18 | High |
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DDR3 SDRAM
The TE0728 SoM has a volatile DDR3 SDRAM, 256Mx16bit (512MB), IC for storing user application code and data. Size of DDR3 can be varied in different assembly versions.
- Part number: NT5CB256M16CP-DIH
- Supply voltage: 1.5V
- Organization: 256M x 16 bits
DDR3 SDRAM can be varied on demand for other assembly options. DDR3 can have density of maximum 512MB due to available addressing. The maximum possible speed for DDR3 SDRAM is 1066 Mb/s.
Ethernet
There are two 100 MBit Extreme Temperature Ethernet provided by Texas Instrumen on the board. Datasheet is provided at TI website. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz sources is provided from MEMS Oscillator. There is no sharing of signals for the two PHY's.
PUDC pin is connected with pull-up to 3.3V those pre-configuration pull-ups are disabled by default. Strapping resistor exist to change the PUDC mode.Controller Area Network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers. The datasheet is available in TI website. Each CAN transceiver is designed to provide differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps.
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title | CAN Tranciever interface MIOsEthernet PHY to Zynq SoC connections |
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MIO Pin | Schematic | Pin | Notes |
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MIO8 | D | U16-1 | Driver Input |
MIO9 | R | U16-4 | Reciever Output |
Low Dropout Linear Regulator
The low-dropout (LDO) provides an easy-to-use robust power management solution for a wide variety of applications. User programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current on start-up. The soft-start is monotonic and well- suited for powering many different types of Monitoring or Provides a Sequencing Signal processors and ASICs. The enable input and power for Other Supplies good output allow easy sequencing with external regulators. This complete flexibility permits the user to configure a solution that meets the sequencing Voltage Startup requirements of FPGAs, DSPs, and other applications with special start-up requirements.
Clock Sources
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title | Osillators |
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Bank | Signal Name | ETH1 | ETH2 | Signal Description |
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34 | ETH-RST | M15 | R16 | Ethernet reset, active-low. | 34 | ETH_COL | L16 | P20 |
| 34 | MDC | P16 | T17 | Ethernet management clock. | 34 | MDIO | M16 | T16 | Ethernet management data. | 34 | ETH_TX_D0 | J22 | N22 | Ethernet transmit data 0. Output to Ethernet PHY. | 34 | ETH_TX_D1 | M17 | P21 | Ethernet transmit data 1. Output to Ethernet PHY. | 34 | ETH_TX_D2 | K21 | P22 | Ethernet transmit data 2. Output to Ethernet PHY. | 34 | ETH_TX_D3 | M22 | R21 | Ethernet transmit data 3. Output to Ethernet PHY. | 34 | ETH_TX_EN | J21 | M21 | Ethernet transmit enable. | 34 | ETH_RX_D0 | L17 | R18 | Ethernet receive data 0. Input from Ethernet PHY. | 34 | ETH_RX_D1 | K18 | R19 | Ethernet receive data 1. Input from Ethernet PHY. | 34 | ETH_RX_D2 | J18 | T18 | Ethernet receive data 2. Input from Ethernet PHY. | 34 | ETH_RX_D3 | J20 | T19 | Ethernet receive data 3. Input from Ethernet PHY. | 34 | ETH_RX_DV | N17 | P15 | Ethernet receive data valid. |
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CAN Transceiver
Controller Area Network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers. The datasheet is available in TI website. Each CAN transceiver is designed to provide differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps.
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title | CAN Tranciever interface MIOs |
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Bank | Signal name | Notes |
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500 | D - Tx | Driver Input | 500 | R - Rx | Reciever Output |
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Oscillators
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title | Osillators |
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Designator | Description | Frequency | Used as |
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U14 | MEMS Oscillator | 50 MHz | PS_CLK | U5 | MEMS Oscillator | 25 MHz | Ethernet PHY Clock | U7 | RTC (internal oscillator) | 32.768 KHz | CLKOUT of RTC is not connected |
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Power and Power-On Sequence
Power Supply
Power supply with minimum current capability of 2.5A for system startup is recommended.
Power Consumption
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Power Input Pin | Typical Current |
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VIN | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
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Power on Sequence
The TE07028 SoM meets the recommended criteria to power up the Xilinx Zynq properly by keeping a specific sequence of enabling the on-board DC-DC converters and regulators dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages. When
Power and Power-On Sequence
Power Supply
Power supply with minimum current capability of 3.5 A for system startup is recommended.
Power Consumption
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title | Power Consumption |
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* TBD - To Be Determined
Power on Sequence
The PS and PL power supplies are fully independent. PS power supplies (VCCPINT, VCCPAUX, VCCPLL, VCCO_DDR, VCCO_MIO0, and VCCO_MIO1) can be powered before or after any PL power supplies. The PS and PL power regions are isolated to prevent damage. The recommended power-on sequence is VCCPINT, then VCCPAUX and VCCPLL together, then the PS VCCO supplies (VCCO_MIO0, VCCO_MIO1, and VCCO_DDR) to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The PS_POR_B input is required to be asserted to GND during the power-on sequence until VCCPINT, VCCPAUX and VCCO_MIO0 have reached minimum operating levels to ensure PS eFUSE integrity.
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Power Distribution Dependencies
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The PS and PL power supplies are fully independent. PS power supplies (VCCPINT, VCCPAUX, VCCPLL, VCCO_DDR, VCCO_MIO0, and VCCO_MIO1) can be powered before or after any PL power supplies. The PS and PL power regions are isolated to prevent damage. The recommended power-on sequence is VCCPINT, then VCCPAUX and VCCPLL together, then the PS VCCO supplies (VCCO_MIO0, VCCO_MIO1, and VCCO_DDR) to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The PS_POR_B input is required to be asserted to GND during the power-on sequence until VCCPINT, VCCPAUX and VCCO_MIO0 have reached minimum operating levels to ensure PS eFUSE integrity.
Voltage Monitor Circuit
The microprocessor supervisory circuits monitor system voltages from 0.4 V to 5 V, asserting an open-drain RESET signal when the SENSE voltage drops below a preset threshold or when the manual reset (MR) pin drops to a logic low. The RESET output remains low for the user adjustable delay time after the SENSE voltage and MR return above their thresholds. Datasheet is available in Texas Instruments website.
When the U8 and U9 generates PWRGD signal, it turns on the U4 which generates PWRGD_3.3V, it turns on the U6 and it generates PWROK signal which is connected to MR. Whenever the supply voltage for U12 drops down below the threshold it resets the system. Actually it resets the system when all regulators are working.
Power Rails
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title | Module power rails.Power On Sequence |
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B2B Name | B2B JM1 Pin | B2B JM2 Pin | B2B JM3 Pin | Direction | Notes |
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VIN | 1,3 | - | - | Input | Supply voltage from carrier board. |
VCCO_13 | 39 | - | - | I/O | VBATT | - | 1 | - | Output | RTC Supply voltage |
3.3V | 19 | 2, 4 | 25,57 | Output | Internal 3.3V voltage level. |
1.8V | - | 5 | - | Output | Internal 1.8V voltage level. |
Bank Voltages
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anchor | Table_PWR_BV |
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title | Zynq SoC bank voltages. |
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VCCO_MIO1_500
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Supplied by the carrier board. JM2,JM3
Board to Board Connectors
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Voltage Monitor Circuit
The microprocessor supervisory circuits monitor system voltages asserting an open-drain RESET signal when the SENSE voltage drops below a preset threshold or when the manual reset (MR) pin drops to a logic low. The RESET output remains low for the user adjustable delay time after the SENSE voltage and MR return above their thresholds. Datasheet is available in Texas Instruments website.
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title | Voltage Monitor Circuit |
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Power Rails
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6 x 6 modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.
3 x REF-189018-01 (compatible to SEM-140-02-03.0-H-D-A), (80 pins, "40" per row)
Operating Temperature:-55°C ~ 125°C
Current Rating: 2.6A per ContactNumber of Positions: 80
Number of Rows: 2
Technical Specifications
Absolute Maximum Ratings
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title | PS absolute maximum ratingsModule power rails. |
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Symbols | Description | Min | Max | Unit |
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VCCPINT | PS internal logic supply voltage | -0.5 | 1.1 | V |
VCCPAUX | PS auxiliary supply voltage | -0.5 | 2.0 | V |
VCCPLL | PS PLL supply | -0.5 | 2.0 | V |
VCCO_DDR | PS DDR I/O supply voltage | -0.5 | 2.0 | V |
VPREF | PS input reference voltage | -0.5 | 2.0 | V |
VCCO_MIO0 | PS MIO I/O supply voltage for HR I/O banks | -0.5 | 3.6 | V |
VCCO_MIO1 | PS MIO I/O supply voltage for HR I/O banks | 1.71 | 3.45 | V |
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Power Signal | B2B JM1 Pin | B2B JM2 Pin | B2B JM3 Pin | Direction | Notes |
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VIN | 1,3 | - | - | Input | Supply voltage from carrier board. | VCCO_13 | 39 | - | - | Input |
| VBATT | - | 1 | - | Output | RTC Supply voltage | 3.3V | 19 | 4 | 25,57 | Output | Internal 3.3V voltage level. | VMIO | - | 2 |
| Input | Variable and supplied by carrier | 1.8V | - | 5 | - | Output | Internal 1.8V voltage level. |
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Bank Voltages
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anchor | Table_TSPWR_AMR_PLBV |
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title | PL absolute maximum ratingsZynq SoC bank voltages. |
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Symbols | Description | Min | Max | Unit |
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VCCINT | PL internal logic supply voltage | -0.5 | 1.1 | V |
VCCPAUX | PL auxiliary supply voltage | -0.5 | 2.0 | V |
VCCPLL | PL PLL supply | -0.5 | 1.1 | V |
VPREF | PL input reference voltage | -0.5 | 2.0 | V |
VCCO | PL supply voltage for HR I/O banks | -0.5 | 3.6 | V |
VIN | I/O input voltage for HR I/O banks | 1.71 | 3.45 | V |
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| Schematic Name | | I/O Type | Notes |
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500 | VCCO_MIO0_500 | 3.3V | MIO |
| 501 | VCCO_MIO1_501 | 2.5V or 3.3V | MIO | supplied by carrier. | 502 | VCCO_DDR_502 | 1.5V | DDR3 |
| 13 | VCCO_13 | 1.8V or 3.3V | HR | Supplied by the carrier board. J1 | 33 | 3.3V | 3.3V | HR | Supplied by carrier board. J3 | 34 | 3.3V | 3.3V | HR |
| 35 | 3.3V | 3.3V | HR | Supplied by the carrier board. J2, J3 |
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Board to Board Connectors
Include Page |
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| 6 x 6 SoM TEM and SEM B2B Connectors |
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| 6 x 6 SoM TEM and SEM B2B Connectors |
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Technical Specifications
Absolute Maximum Ratings
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title | Recommended operating conditionsAbsolute maximum ratings |
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ParameterUnitsReference DocumentDescription |
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VIN supply voltage | -0.3 |
.56065 | V | TPS54260-Q1 datasheets. |
Supply voltage for PS MIO banks | 1.71465See Xilinx DS187 datasheet. | I/O input voltage for banks-0.2 | VCCO_MIO + 0.20 | V | See Xilinx DS187 datasheet. | Supply voltage for PS DDR | 1.14 | 1.89 | V | See Xilinx DS187 datasheet. |
input voltage for PS DDR20VCCO_DDR + 0.20See Xilinx DS187 datasheet. | Supply PL supply voltage for HR I/ |
Os banks1.14 | 3.465 | V | See Xilinx DS187 datasheet. | I/O input voltage for HR I/O banks | -0.20 | VCCIO + 0.20 | V | See Xilinx DS187 datasheet. |
Storage Temperature | -65 | 150 | °C | See Xilinx DS187 datasheet. |
CAN Transceiver Temperature | -40 | 125 | °C | See Texas Instrument sn65hvd230q-q1 datasheet. |
SPI Flash Memory | -40 | 85 | °C | See Cypress S25FL127S datasheet. |
DDR3 SDRAM Temperature | -40 | 95 | °C | See Nanya NT5CC256M16CP-DIA datasheet. |
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Temprature range: -40°C to +85°C.
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
O banks | Storage Temperature | -40 | +85 | °C |
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Recommended Operating Conditionse
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Symbol | Min | Max | Units | Reference Document |
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VIN supply voltage | 3.5 | 60 | V | TPS54260-Q1 datasheets. | VMIO | 1.71 | 3.465 | V | See Xilinx DS187 data sheet. | VCCO | 1.14 | 3.465 | V | See Xilinx DS187 datasheet. | Operating Temperature | -40 | +105 | °C |
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Physical Dimensions
Module size: 60 mm × 60 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 7 mm.
PCB thickness: 1.6 mm.
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Currently
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Offered Variants
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title | Trenz Electronic Shop Overview |
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Revision History
Hardware Revision History
Product changes can be seen in PCN page.
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Date | Revision | Note | PCN | Documentation Link |
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- | 01 | Prototypes | - | - |
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Date | Revision | Changes |
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| 04 | - U1 DDR3 IC changed from NT5CB256M16CP-DIH to NT5CC256M16CP-DIH
- Net DDR3-ODT0: added series resistor R55
- Added Traceability pad
- Net PS-POR-B: added pull-down resistor R56
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2015-12-01 | 03 | |
2015-06-12 | 02 | |
2015-03-03 | 01 | |
Hardware revision number is printed on the PCB board next to the module model number separated by the dash.
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf PDF export template - Metadata is only used of compatibility of older exports
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| change list | | 2019-05-16 | v. 367 | Pedram Babakhani | | -- | all | Page info |
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infoType | Modified users |
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