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Main Components
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Table 4: B2B connector pin-outs of available PL and PS banks of the TE0807-02 03 SoM.
All MIO banks are powered from on-module DC-DC power rail. All PL I/O Banks have separate VCCO pins in the B2B connectors, valid VCCO should be supplied from the baseboard.
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Bank | Type | Lane | Signal Name | B2B Pin | FPGA Pin |
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224 | GTH | 0 |
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225 | GTH | 0 |
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226 | GTH | 0 |
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227 | GTH | 0 |
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505 | GTR | 0 |
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Table 5: MGT lanes
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PS MIO | Function | Connected to |
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0 | SPI0 | U7-B2, CLK |
1 | SPI0 | U7-D2, DO/IO1 |
2 | SPI0 | U7-C4, WP/IO2 |
3 | SPI0 | U7-D4, HOLD/IO3 |
4 | SPI0 | U7-D3, DI/IO0 |
5 | SPI0 | U7-C2, CS |
6 | N/A | Not connected |
7 | SPI1 | U17-C2, CS |
8 | SPI1 | U17-D3, DI/IO0 |
9 | SPI1 | U17-D2, DO/IO1 |
10 | SPI1 | U17-C4, WP/IO2 |
11 | SPI1 | U17-D4, HOLD/IO3 |
12 | SPI1 | U17-B2, CLK |
13 ... 77 | user dependent | B2B connector J2 |
Table 11: TE0807-02 03 PS MIO mapping
On-board Peripherals
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Table 12: Peripherals connected to the PS MIO pins.
DDR4 SDRAM
The TE0807-02 03 SoM is equipped with with four DDR4 -2400 SDRAM modules chips with a total of up to 8 GByte memory density. The SDRAM modules chips are connected to the Zynq MPSoC's PS DDR controller (bank 504) with a 64bit wide data bus.
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Power Rail Name | B2B J1 Pins | B2B J2 Pins | B2B J3 Pins | B2B J4 Pins | Directions | Note |
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PL_DCIN | 151, 153, 155, 157, 159 | - | - | - | Input | - |
DCDCIN | - | 154, 156, 158, 160, | - | - | Input | - |
LP_DCDC | - | 138, 140, 142, 144 | - | - | Input | - |
PS_BATT | - | 125 | - | - | Input | - |
GT_DCDC | - | - | 157, 158, 159, 160 | - | Input | - |
PLL_3V3 | - | - | 152 | - | Input | U5 (programmable PLL) 3.3V nominal input |
SI_PLL_1V8 | - | - | 151 | - | Output | Internal voltage level 1.8V nominal output |
PS_1V8 | - | 99 | 147, 148 | - | Output | Internal voltage level |
PL_1V8 | 91, 121 | - | - | - | Output | Internal voltage level |
DDR_1V2 | - | 135 | - | - | Output | Internal voltage level |
VCCO47 | - | - | 43, 44 | - | Input | - |
VCCO48 | - | - | 15, 16 | - | Input | - |
VCCO64 | - | - | - | 58, 106 | Input | - |
VCCO65 | - | - | - | 69, 105 | Input | - |
VCCO66 | 90, 120 | - | - | - | Input | - |
Table 19: TE0807-02 03 power rails
Bank Voltages
Bank | Type | Schematic Name | Voltage | Reference Input Voltage | Voltage Range |
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47 | HD | VCCO47 | user | - | 1.2V to 3.3V |
48 | HD | VCCO48 | user | - | 1.2V to 3.3V |
64 | HP | VCCO64 | user | VREF_64, pin J4-88 | 1.2V to 1.8V |
65 | HP | VCCO65 | user | VREF_65, pin J4-15 | 1.2V to 1.8V |
66 | HP | VCCO66 | user | VREF_66, pin J1-108 | 1.2V to 1.8V |
500 | MIO | PS_1V8 | 1.8V | - | - |
501 | MIO | PS_1V8 | 1.8V | - | - |
502 | MIO | PS_1V8 | 1.8V | - | - |
503 | CONFIG | PS_1V8 | 1.8V | - | - |
Table 20: TE0807-02 03 I/O bank voltages
See Xilinx Zynq UltraScale+ datasheet DS925 for the voltage ranges allowed.
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Parameter | Min | Max | Unit | Notes / Reference Document |
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PL_DCIN | -0.3 | 74 | V | TPS82085SIL / EN63A0QI data sheet/ Limit is LP_DCDC over EN/PG |
DCDCIN | -0.3 | 74 | V | TPS82085SIL / TPS51206 data sheet/ Limit is LP_DCDC over EN/PG |
LP_DCDC | -0.3 | 4 | V | TPS3106K33DBVR data sheet |
GT_DCDC | -0.3 | 74 | V | TPS82085SIL data sheet/ Limit is LP_DCDC over EN/PG |
PS_BATT | -0.5 | 2 | V | Xilinx DS925 data sheet |
PLL_3V3 | -0.5 | 3.8 | V | Si5345/44/42 data sheet |
VCCO for HD I/O banks | -0.5 | 3.4 | V | Xilinx DS925 data sheet |
VCCO for HP I/O banks | -0.5 | 2 | V | Xilinx DS925 data sheet |
I/O input voltage for HD I/O banks | -0.55 | VCCO + 0.55 | V | Xilinx DS925 data sheet |
I/O input voltage for HP I/O banks | -0.55 | VCCO + 0.55 | V | Xilinx DS925 data sheet |
PS I/O input voltage (MIO pins) | -0.5 | VCCO_PSIO + 0.55 | V | Xilinx DS925 data sheet, VCCO_PSIO 1.8V nominally |
PS GTR reference clocks absolute input voltage | -0.5 | 1.1 | V | Xilinx document DS925 |
PS GTR absolute input voltage | -0.5 | 1.1 | V | Xilinx document DS925 |
MGT clock absolute input voltage | -0.5 | 1.3 | V | Xilinx document DS925 |
MGT Receiver (RXP/RXN) and transmitter | -0.5 | 1.2 | V | Xilinx DS925 data sheet |
Voltage on input pins of | -0.5 | VCC + 0.5 | V | NC7S08P5X data sheet, see schematic for VCC |
Voltage on input pins (nMR) of | -0.3 | VDD + 0.3 | V | TPS3106 data sheet, |
"Enable"-signals on TPS82085SIL (EN_PLL_PWR, EN_LPD) | -0.3 | 7 | V | TPS82085SIL data sheet |
Storage temperature (ambient) | -40 | 100 | °C | ROHM Semiconductor SML-P11 Series data sheet |
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Parameter | Min | Max | Unit | Notes / Reference Document |
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PL_DCIN | 3.3 | 3.6 | V | EN63A0QI / TPS82085SIL data sheet/ Limit is LP_DCDC over EN/PG |
DCDCIN | 3.3 | 3.6 | V | TPS82085SIL / TPS51206PSQ data sheet/ Limit is LP_DCDC over EN/PG |
LP_DCDC | 3.3 | 3.6 | V | TPS82085SIL / TPS3106 data sheet |
GT_DCDC | 3.3 | 3.6 | V | TPS82085SIL data sheet/ Limit is LP_DCDC over EN/PG |
PS_BATTPS_BATT | 1.2 | 1.5 | V | Xilinx DS925 data sheet |
PLL_3V3 | 3.3 | 3.47 | V | Si5345/44/42 data sheet 3.3V typical |
VCCO for HD I/O banks | 1.14 | 3.4 | V | Xilinx DS925 data sheet |
VCCO for HP I/O banks | 0.95 | 1.9 | V | Xilinx DS925 data sheet |
I/O input voltage for HD I/O banks. | -0.2 | VCCO + 0.2 | V | Xilinx DS925 data sheet |
I/O input voltage for HP I/O banks | -0.2 | VCCO + 0.2 | V | Xilinx DS925 data sheet |
PS I/O input voltage (MIO pins) | -0.2 | VCCO_PSIO + 0.2 | V | Xilinx DS925 data sheet, VCCO_PSIO 1.8V nominally |
PL bank reference voltage VREF pin | -0.5 | 2 | V | Xilinx DS925 data sheet |
Voltage on input pins of NC7S08P5X 2-Input AND Gate | 0 | VCC | V | NC7S08P5X data sheet, |
Voltage on input pin 'MR' of | 0 | VDD | V | TPS3106 data sheet, |
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Module size: 52 mm × 76 mm. Please download the assembly diagram for exact numbers
Mating height with standard connectors: 4mm5mm
PCB thickness: 1.6mm
Highest part on PCB: approx. 3mm. Please download the step model for exact numbers
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Date | Revision | Notes | PCN Link | Documentation Link |
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2020-06-05 | 03 | current available module revision | PCN-20200511 | TE0807-03 |
- | 02 | current available module revision | - | TE0807-02 |
- | 01 | first production release | - | TE0807-01 |
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Document Change History
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2021-09-07 |
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2021-06-10 | v.27 | John Hartfiel |
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2021-05-17 | v.26 | John Hartfiel |
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2021-05-03 | v.25 | Martin Rohrmüller |
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2021-03-11 | v.24 | Antti Lukats |
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2019-06-14 | Jun 2019v.22 | John Hartfiel |
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2018-08-07 | Aug 2018v.20 | Ali Naseri |
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Table 24: Document change history
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