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Refer to httpshttp://wiki.trenz-electronic.de/display/PD/<name>org/te0724-info for the current online version of this manual and other available documentation.

The Trenz Electronic TE0724 is an industrial-grade SoC module based on Xilinx Zynq - 7010/7020, which provides a dual core ARM Cortex A9 and a 7-series FPGA logic. It provides a gigabit ethernet transceiver, 1GByte 1 GByte of DDR3L SDRAM, 32 64 MByte Flash memory as configration and data storage. it It includes strong pwerregulators power regulators for all needed voltages and a robust high-speed connector for in- and outputs. It has a 6 x 4 cm form factor.

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• Xilinx Zynq XC7Z010-1CLG400I or XC7Z020-1CLG400I
• Dual-core ARM Cortex-A9 MPCore
• Max. 667 MHz
• Shock proof and vibration resistant
• Size 6 x 4 cm
• Plug-On-Modul with 1 × 160 Pin High-Speed connector
• 1 GByte DDR3L SDRAM
• 32 64 MByte QSPI Flash Speicher
• 1 x GBit Ethernet PHY
• 1 x MAC-Address EEPROM
• 128 KBit EEPROM
• 1 x CAN Transceiver
• On-Board DC/DC-regulators
• Excellent signal integrity due to well dirstributed evenly-spread supply pins

Additional assembly options are available for cost or performance optimization upon request.

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1. XILINX ZYNQ XC7Z020-2CLG400C, U1
2. Gigabit Ethernet Transceiver Alaska 88E1512, U7
3. Power Manager Dialog DA9062, U4
4. 1GByte - 2x 4Gbit DDR3L RAM, U3, U5
5. 32MByte Spansion 64MByte ISSI SPI Flash S25FL256IS25LP512M, U13
6. 128KByte Serial EEPROM Microchip 24AA, U10
7.  CAN Transceiver MCP2542FDT, U2
8.  160 Pin Samtec B2B Connector ST5-80-1.50-L-D-P-TR, J1

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Boot mode is selected via two Mode pins at B2B connector J2. By default the TE0724 supports JTAG and SPI Boot Mode. Connecting a SD Card via B2B connector to MIO Pins (See SD Card Interface) gives the possibility to boot from SD Card. The Mode pins are pulled up at the module.

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All PS MIO banks as well as PL bank 34 are powered by on-module DC-DC power rails. Valid VCCO_35 for PL bank 35 should be supplied from via the carrier boardB2B connector.

For detailed information about the pin out, please refer to the Pin-out Tables. 

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On-board QSPI flash memory (U13) on the TE0724-02 04 is a SPANSION S25FL256S ISSI IS25LP512M with 256 512 Mbit (32 64 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

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A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I²C bus with slave device address 0x53.

USER EEPROM

A Microchip 24AA128T serial EEPROM (U10) is availabe available for e.g. module idetification identification and user Data. The device has 128Kbit memory with max 64 bytes page write capability. It is accessible over I²C bus with slave device address 0x50.

Oscillators

The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

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Table 11: On-board LEDs.

Power and Power-On Sequence

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Power Consumption

The maximum power consumption of a module mainly depends on the design running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

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Table 12: Typical power consumption.

 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of ...A for system startup is recommended.

The on-board voltages of the TE0724 SoC module will be powered-up in order of a determined sequence after the external voltages VIN  is available and nONKEY is asserted.

Power Distribution Dependencies

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Pin Header

Optional assembled Pin Header J2 can be used for PMIC In-System Programming.

Table 12: Optional assembled Pin Header.

Power and Power-On Sequence

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Power Consumption

The maximum power consumption of a module mainly depends on the design running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table 13: Typical power consumption.

 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of ...A for system startup is recommended.

The on-board voltages of the TE0724 SoC module will be powered-up in order of a determined sequence after the external voltages VIN  is available and nONKEY is asserted.

Power Distribution Dependencies

DCDC U8 component is either TPS82140 (2 A) or MUN12A (3 A) depending on the variant.

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See Xilinx data sheet for additional information. User should also check related base board documentation when intending base board design for TE0724 module.

Power-On Sequence

The TE07024 SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages. For a detailed description of the configurabel Power Management IC please refer to the datasheet of  dialog semicondutor DA9062.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

Power Rails

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Power Rail Name

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B2B JM1 Pins

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Direction

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VBAT

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Table 13: Module power rails.

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Bank Voltages

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Bank

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Voltage

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Voltage Range

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Table 14: Module PL I/O bank voltages.

Board to Board Connectors

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The TE0724 module has two 160-pin double-row REF-189019-02 connectors on the bottom side.

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Order
number

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See Xilinx data sheet for additional information. User should also check related base board documentation when intending base board design for TE0724 module.

Power-On Sequence

The TE0724 SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages. For a detailed description of the configurable Power Management IC please refer to the datasheet of dialog semicondutor DA9062.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in ascending order as listed in the blocks of the diagram:

Power Rails

Table 14: Module power rails.

Current rating of theSamtec connector is 1.6A per pin (1 pin powered per row).

Bank Voltages

Table 15: Module PL I/O bank voltages.

Board to Board Connectors

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Table 16: Module connector specifications.

Variants Currently In Production

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Table 1518: Module absolute maximum ratings.

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Recommended Operating Conditions

Table 1619: Module recommended operating conditions.

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• Module size: 60 mm × 40 mm.  Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: 45.08 0 mm.

• PCB thickness: 1.6 mm.

• Highest part on PCB: approx. 1.6 mm. Please download the step model for exact numbers.

All dimensions are given in millimeters.

Scroll Title
title Figure 65: TE0724 Mechanical Dimensions.
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Revision History

Hardware Revision History

Table 20Table : Module hardware revision history.

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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

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Table 21Table : Document change history.

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