Page History
Template Revision 2.12
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id | Comments |
Important General Note:
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Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
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Figure template:
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anchor | Figure_anchorname |
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title | Text |
Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Table template:
- Layout macro can be use for landscape of large tables
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anchor | Table_tablename |
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title | Text |
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The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below
<type>_<main section>_<name>
- type: Figure, Table
- main section:
- "OV" for Overview
- "SIP" for Signal Interfaces and Pins,
- "OBP" for On board Peripherals,
- "PWR" for Power and Power-On Sequence,
- "B2B" for Board to Board Connector,
- "TS" for Technical Specification
- "VCP" for Variants Currently in Production
- "RH" for Revision History
- name: custom, some fix names, see below
- Fix names:
"Figure_OV_BD" for Block Diagram
"Figure_OV_MC" for Main Components
"Table_OV_IDS" for Initial Delivery State
"Table_PWR_PC" for Power Consumption
- "Figure_PWR_PD" for Power Distribution
- "Figure_PWR_PS" for Power Sequence
- "Figure_PWR_PM" for Power Monitoring
- "Table_PWR_PR" for Power Rails
- "Table_PWR_BV" for Bank Voltages
"Table_TS_AMR" for Absolute_Maximum_Ratings
"Table_TS_ROC" for Recommended_Operating_Conditions
- "Figure_TS_PD" for Physical_Dimensions
- "Table_VCP_SO" for TE_Shop_Overview
"Table_RH_HRH" for Hardware_Revision_History
- "Figure_RH_HRN" for Hardware_Revision_Number
- "Table_RH_DCH" for Document_Change_History
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Table of Contents
Table of Contents |
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- SoC FPGA
- Intel Cyclone V (5CSEMA5F31C8N)
- Package: FBGA 896 pins
- Speed Grade: 8
- Temperature: Commercial (Tj = 0 °C to 85 °C)
- RAM/Storage
- 1 GByte DDR3 SDRAM for HPS
- 1 GByte DDR3 SDRAM for FPGA
- 32 MByte SPI for HPS
- 32 MByte SPI for FPGA
- On Board
- up to 7 x SMA Connector
- Temperature Sensor
- Intel MAX10 for board management
- Interface
- LPC FMC Connector
- 4 x PMOD Connector
- JTAG via micro USB B Connector
- UART via micro USB B Connector
- 4 x USB 2.0
- Ethernet via RJ45 Connector
- SD Card
- HDMI
- Power
- 12 V Input supply voltage
- Dimension
- 160 mm x 130 mm
Block Diagram
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id | Comments |
add drawIO object here.
Note |
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For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" . |
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anchor | Figure_OV_BD |
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title | TEI0022-01 block diagram |
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Key Features' must be split into 6 main groups for modues:
- SoC/FPGA
- Package:
- Speed:
- Temperature:
- RAM/Storage
- E.g. SDRAM, SPI
- On Board
- E.g. CPLD, PLL
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
Key Features' must be split into 6 main groups for carrier:
- Modules
- TE0808, TE807, TE0803,...
- RAM/Storage
- E.g. SDRAM, SPI
- On Board
- E.g. CPLD, PLL
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
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BOOTSEL[1..0] Signal State
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Notes :
- For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- SD
- USB
- ETH
- FMC
- ...
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
- JTAG
- UART
- I2C
- MGT
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JTAG Interface
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JTAGSEL1
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JTAGSEL1
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I2C
The TEI0022 provides three independent I2C busses. One bus is used to connect the FMC I2C with the Intel Cyclone V HPS. The second bus is to connect the HDMI device to the Intel Cyclone V FPGA. The third bus is used to handle the other on-board I2C devices.
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anchor | Table_OBP_I2C |
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title | On-board peripherals' I2C-interfaces device slave addresses |
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anchor | Figure_OV_I2C |
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title | TEI0022-01 I2C |
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The connector supports single ended (VCCIO: FMC_VADJ) and differential signaling as the I/O's are routed from the FPGA banks as LVDS-pairs to the FMC connector.
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FMC_TCK, Pin J4-D29
FMC_TMS, Pin J4-D33
FMC_TDI, Pin J4-D30
FMC_TDO, Pin J4- D31
FMC_TRST#, Pin J4- D34
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FMC_SCL, Pin J4-C30
FMC_SDA, Pin J4-C31
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FMC_PRSNT_M2C#, Pin J4-H2 (pulled-up to +3.3V)
FMC_PG_C2M, Pin J4-D1 (pulled-up to +3.3V)
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'PG' = 'Power Good'-signal
'C2M' = carrier to (Mezzanine) module
'M2C' = (Mezzanine) module to carrier
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FAN Connector
The TEI0022 board offers one FAN connector for cooling the FPGA device. Depending on the assembly 5 V or 12 V are usable.
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Connector
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Connected to
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FAN_EN,
(High Side Switch U55, Pin 3)
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SMA Connector
The TEI0022 board offers seven SMA connectors for trigger and clock input and output.
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anchor | Table_SIP_SMA |
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title | SMA connectors |
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SMA Connector
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Connected to
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J15
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SD Card Connector
SD Card connector J3 is connected to the Intel Cyclone V.
On-board Peripherals
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id | Comments |
Notes :
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JTAG Interface
The TEI0022 uses as JTAG interface the FT2232 (U21) chip. With this and the settings it is possible to access the Cyclone V programmable logic, the processing system, the Intel MAX10 and the FMC.
UART Interface
A UART connection between the USB B connector J5 and the Intel Cyclone HPS U10 is possible via the FT234XD (U30) chip.
DIP-Switches
There are three 4-bit DIP-switches present on the TEI0022 board to configure options and set parameters. The following section describes the functionalities of the particular switches.
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DIP-Switch S8
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Buttons
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On-Board LEDs
The TEI0022 board is equipped with several LEDs to signal current states and activities. The functionality of the LEDs D11...14 are user LEDs. The LED D8 shows the Intel Cyclone V configuration progress. LEDs D15, D18...19 shows the UART connection and the other LEDs mentioned in the table are supply power status LEDs.
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anchor | Table_OBP_LED |
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title | On-board LEDs |
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Temperatur Sensor
The temperature sensor ADT7410 (U16) is implemented on the TEI0022 board.
Quad SPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
Two 256 Mbit (32 MByte) Quad SPI Flash Memory (Micron MT25QL256ABA8E12, U6, U15) are provided for FPGA and HPS configuration file storage. After configuration process completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA or the HPS allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.
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EEPROM
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Clock Sources
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Programmable Clock Generator
There is a Silicon Labs I2C programmable quad PLL clock generator on-board (Si5338A, U3) to generate various reference clocks for the module.
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anchor | Table_OBP_PLL |
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title | Programmable quad PLL clock generator inputs and outputs |
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IN1
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IN3
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Reference input clock
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IN4
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IN5
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I²C interface muxed to Intel Cyclone V
Slave address: 0x70.
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I²C interface muxed to Intel Cyclone V
Slave address: 0x70.
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CLK0A/B
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SMA_CLK_OUT_p/n
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Clock to SMA connectors
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CLK1A/B
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Clock to Intel MAX10 bank 2
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CLK_B4A_p/n
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Clock to FPGA bank 4A
Power Monitoring
The TEI0022 uses a precision supply monitor (U54) for three voltages. Therefore if one of the voltages browns out it should be realized and handled.
Power and Power-On Sequence
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hidden | true |
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id | Comments |
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
- Power on-sequence
- Power distribution
- Voltage monitoring circuit
Note |
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For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" . |
Power Supply
The maximum power consumption of this board mainly depends on the design which is running on the FPGA. Intel provides a power estimator excel sheets to calculate power consumption.
Power Consumption
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anchor | Table_PWR_PC |
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title | Power Consumption |
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* TBD - To Be Determined
Power Distribution Dependencies
All on-board voltages of the TEI0022 are generated out of the extern applied 12 V power supply.
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Power-On Sequence
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Currently Offered Variants
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change list
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- Initial Document