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The Trenz Electronic TE0823 (3PIU1FA /3PIU1FL) is an industrial-grade MPSoC module integrating a low power Xilinx Zynq UltraScale+ ZU3CGMPSoC, 1 GByte LPDDR4 SDRAM, 128 MByte 8 GB eMMC chip, 2x 64 MB Flash memory for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking connections. The module is equipped with a Lattice Mach XO2 CPLD for system controlling. 3x Robust high-speed connectors provide a large number of inputs and outputs.
The highly integrated modules are All this on a tiny footprint, smaller than a credit card , at the most competitive price. Modules in and are offered in several variants at an affordable price-performance ratio. Modules with a 4 x 5 cm form factor are fully completely mechanically and largely electrically compatible among with each other.
All parts are at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Refer to http://trenz.org/te0823-info for the current online version of this manual and other available documentation.
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Note: 'description: Important components and connector or other Features of the module → please sort and indicate assembly options Key Features' must be split into 6 main groups for modules and mainboards: - SoC/FPGA
- Package: SFVC784
- Device: ZU2...ZU5*
- Engine: CG, EG, EV*
- Speed: -1LI, -2LE,*, **
- Temperature: I, E,*, **
- RAM/Storage
- Low Power DDR4 on PS
- Data width: 32bit
- Size: def. 2GB*
- Speed:***
- eMMC
- Data width: 8Bit
- size: def. 8GB *
- QSPI boot Flash in dual parallel mode (size depends on assembly version)
- Data width: 8bit
- size: def. 128MB *
- HyperRAM/Flash (optional, default not assembled)
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
- On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
- Interface
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, Sata, PCIe, DP)
- MIO for UART
- MIO for SD
- MIO for PJTAG
- JTAG
- Ctrl
- Power
- 3.3V-5V Main Input
- 3.3V Controller Input
- Variable Bank IO Power Input
- Dimension
- Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
Key Features' must be split into 6 main groups for carrier: - Modules
- TE0808, TE807, TE0803,...
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
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- SoC/FPGA
- Package: SFVC784, SFRC784
- Device: ZU2 ...ZU5, *
- Engine: EG, CG, EV, *
- Speed: -1, -1L, -2, -2L, 3, *, **
- Temperature: I, E, *, **
- RAM/Storage
- 2x DDR4 SDRAM,
- Data Width: 32 Bit
- Size: 16 Gb, *
- Speed: 3733 Mbps, ***
- 2x QSPI boot Flash in dual parallel mode
- Data Width: 8 Bit
- Size: 512 Mb Gb, *
- 1x e.MMC Memory
- Data Width: 8 Bit
- Size: 32 Gb, *
- MAC address serial EEPROM
- On Board
- Lattice MachXO2 CPLD
- Programmable Clock Generator
- Hi-speed USB2 ULPI Transceiver
- 4x LEDS
- Interface
- 1x GB/s serial GMII interface
- 1x Hi-speed USB2 ULPI transceiver with full OTG support
- 154 x High Performance (HP) und 96 x High Density (HD) I/Os
- 78 x PS MIOs
- 4 x serial PS GTR transceivers
- Power
- All power regulators on board
- Dimension
- Note
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
- Rugged for shock and high vibration
BlockDiagram
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anchor | Figure_OV_BD |
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title | TE0823 block diagram |
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| Figure_OV_BD |
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title | TE0823 block diagram |
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scroll-pdf | true |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-html | true |
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| scroll-ignore | draw.io Diagram |
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border | false |
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diagramName | TE0823_OV_BD |
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links | auto |
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tbstyle | hidden |
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lbox | true |
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diagramWidth | 641 |
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revision | 1316 |
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Main Components
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anchor | Table_OV_BP |
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title | Boot process. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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MODE Signal State | Boot Mode |
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LowHigh | QSPI* | HighLow | SD Card* |
*changable also with other CPLD Firmware:TE0823 CPLD |
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anchor | Table_OV_RST |
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title | Reset process. |
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orientation | portrait |
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sortDirection | ASC |
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sortEnabled | false |
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cellHighlighting | true |
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Signal | B2B | I/O | Note |
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ENRESIN | JM1JM2-2818 | InputCPLD Enable Pin |
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Signals, Interfaces and Pins
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The TE0821 is equipped with dual Flash Memory, U7, U17. Two quad SPI compatible serial bus flash MT25QU512ABB8E12-0SIT flash memory chips are provided for FPGA configuration file and data storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.
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anchor | Table_OBP_SPI |
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title | Quad SPI interface MIOs and pins |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortEnabled | false |
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MIO Pin | Schematic | U?? Pin | | Notes | QSPI, U7 | QSPI, U17Notes |
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nCS | MIO5 | MIO7 |
| CLK | MIO0 | MIO12 |
| DI/IO0 | MIO4 | MIO8 |
| DO/IO1 | MIO1 | MIO9 |
| nHOLD/IO3 | MIO3 | MIO11 |
| WP/IO2 | MIO2 | MIO10 |
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EEPROM
There is a 2Kb EEPROM provided on the module TE0821.
Scroll Title |
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anchor | Table_OBP_EEP |
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title | I2C EEPROM interface MIOs and pins |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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MIO Pin | Schematic | U?? Pin | Notes |
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MIO39 | I2C_SDA | SDA |
| MIO38 | I2C_SCL | SCL |
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anchor | Table_OBP_I2C_EEPROM |
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title | I2C address for EEPROM |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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MIO Pin | I2C Address | Designator | Notes |
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MIO38-MIO39 | 0x50 | U25 |
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LEDs
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anchor | Table_OBP_LED |
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title | On-board LEDs |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Color | Connected to | Active Level | Note |
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D1 | Red | DONE | Low |
| D2 | Green | USR_LED | High |
| D3 | Red | ERR_OUT | High |
| D4 | Green | ERR_STATUS | High |
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE0821 TE0823 SoM has dual 8 Gb volatile DDR4 a 1 GB volatile LPDDR4 SDRAM IC for storing user application code and data.
- Part number: K4A8G165WB-BIRC IS43LQ32256A
- Supply voltage: voltage: 1.7V ~ 1.2V95V
- Speed: 2400 3200 Mbps
- Temperature: -40 ~ 95 °C
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anchor | Figure_PWR_PD |
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title | Power Distribution |
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diagramName | TE0823_PWR_PD |
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simpleViewer | false |
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links | auto |
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tbstyle | hidden |
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lbox | true |
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diagramWidth | 640 |
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revision | 910 |
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Power-On Sequence
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- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
Include Page |
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| PD:6 x 6 SoM LSHM B2B ConnectorsPD: |
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| 6 x 6 SoM LSHM B2B Connectors |
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Include Page |
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| PD:4 x 5 SoM LSHM B2B ConnectorsPD: |
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| 4 x 5 SoM LSHM B2B Connectors |
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anchor | Table_TS_ROC |
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title | Recommended operating conditions. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Parameter | Min | Max | Units | Reference Document |
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VIN supply voltage | 3.3 | 6 | V | See TPS82085S datasheet | 3.3VIN supply voltage | 3.3 | 3.465 | V | See LCMXO2-256HC, Xilinx DS925 datasheet | PS I/O supply voltage, VCCO_PSIO | 1.710 | 3.465 | V | Xilinx document DS925 | PS I/O input voltage | –0.20 | VCCO_PSIO + 0.20 | V | Xilinx document DS925 | HP I/O banks supply voltage, VCCO | 0.950 | 1.9 | V | Xilinx document DS925 | HP I/O banks input voltage | -0.20 | VCCO + 0.20 | V | Xilinx document DS925 | Voltage on SC CPLD pins | -0.3 | 3.6 | V | Lattice Semiconductor MachXO2 datasheet | Operating Temperature Range | 0 | 85 | °C | Xilinx document DS925, extended grade Zynq temperarure range |
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title | Physical Dimension |
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diagramName | TE0823_TS_PD |
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revision | 34 |
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scroll-pdf | true |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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anchor | Figure_RV_HRN |
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title | Board hardware revision number. |
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scroll-pdf | true |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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border | false |
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diagramName | TE0823_RV_HRN |
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simpleViewer | false |
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links | auto |
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tbstyle | hidden |
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diagramDisplayName | |
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revision | 2 |
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anchor | Table_RH_DCH |
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title | Document change history. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Date | Revision | Contributor | Description |
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infoType | Modified date |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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infoType | Current version |
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prefix | v. |
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type | Flat |
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showVersions | false |
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infoType | Modified by |
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type | Flat |
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showVersions | false |
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| | 2021-08-23 | v.42 | Pedram Babakhani | | 2020-11-02 | v.40 | Pedram Babakhani | | -- | all | Page info |
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infoType | Modified users |
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type | Flat |
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