TE0823 TRM

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Overview

The Trenz Electronic TE0823 (3PIU1FA /3PIU1FL)  is an industrial-grade MPSoC module integrating a low power Xilinx Zynq UltraScale+ MPSoC, 1 GByte LPDDR4 SDRAM, 8 GB eMMC chip, 2x 64 MB Flash memory for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking connections.  The module is equipped with a Lattice Mach XO2 CPLD for system controlling. 3x Robust high-speed connectors provide a large number of inputs and outputs.

The highly integrated modules are smaller than a credit card and are offered in several variants at an affordable price-performance ratio. Modules with a 4 x 5 cm form factor are completely mechanically and largely electrically compatible with each other.

All parts are at least industrial temperature range. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Refer to http://trenz.org/te0823-info for the current online version of this manual and other available documentation.

Key Features

• SoC/FPGA
  
  • Package: SFVC784, SFRC784
  • Device: ZU2 ...ZU5, *
  • Engine:  EG, CG, EV, *
  • Speed: -1, -1L, -2, -2L, 3, *, **
  • Temperature: I, E, *, **
• RAM/Storage
  • 2x  DDR4 SDRAM,
    • Data Width: 32 Bit
    • Size: 16 Gb, *
    • Speed: 3733 Mbps, ***
  • 2x QSPI boot Flash in dual parallel mode
    • Data Width: 8 Bit
    • Size: 512 Mb Gb, *
  • 1x e.MMC Memory
    • Data Width: 8 Bit
    • Size: 32 Gb, *
  • MAC address serial EEPROM
• On Board
  
  • Lattice MachXO2 CPLD
  • Programmable Clock Generator
  • Hi-speed USB2 ULPI Transceiver
  • 4x LEDS
• Interface
  • 1x GB/s serial GMII interface
  • 1x Hi-speed USB2 ULPI transceiver with full OTG support
  • 154 x High Performance (HP) und 96 x High Density (HD) I/Os
  • 78 x PS MIOs
  • 4 x serial PS GTR transceivers
    • PCI Express interface version 2.1 compliant
    • SATA 3.1 specification compliant interface

    • DisplayPort source-only interface with video resolution up to 4k x 2k

    • USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
• Power
  • All power regulators on board
• Dimension
  • 40 x 50 mm
• Note
  • * depends on assembly version
  • ** also non low power assembly options possible
  • *** depends on used U+ Zynq and DDR4 combination
  • Rugged for shock and high vibration

Block Diagram

Main Components

1. Xilinx Zynq UltraScale+ XCZU3EG, U1
2. Red LED (ERR_OUT), D3
3. Green User LED, D2
4. Green LED (ERR_STATUS), D4
5. Red LED (DONE), D1
6. 10/100/1000 Mbps energy efficient ethernet transceiver, U8
7. 8Gb DDR4, U2-U3
8. 512 Mbit QSPI flash memory, U7-U17
9. B2B connector Samtec Razor Beam, JM1
10. B2B connector Samtec Razor Beam, JM3
11. Programmable clock generator, U10
12. USB2.0 Transceiver,  U18
13. B2B connector Samtec Razor Beam, JM2
14. 8 GByte eMMC memory, U6
15. Lattice Semiconductor MachXO2 System Controller CPLD, U21

Initial Delivery State

Configuration Signals

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

JTAG Interface

JTAG access to the Xilinx Zynq UltraScale+ is applicable by using Lattice MachXO CPLD  through B2B connector JM2.

MGT Lanes

There are 4x MGT Lanes connected to FPGA Bank 505-GTR.

Gigabit Ethernet

On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 chip. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an on-board 25MHz oscillator (U11), the 125MHz output clock is left unconnected.

System Controller CPLD

Special purpose pins are connected to System Controller CPLD and have following default configuration:

USB Interface

USB PHY is provided by Microchip USB3320. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V. Reference clock input for the USB PHY is supplied by the on-board 52.00 MHz oscillator (U14).

I2C Interface

On-board I²C devices are connected to MIO38 (SCL) and MIO39 (SDA) which are configured as I²C0 by default. Addresses for on-board I²C slave devices are listed in the table below:

MIO Pins

Test Points

On-board Peripherals

Quad SPI Flash Memory

The TE0821 is equipped with dual Flash Memory, U7, U17.  Two quad SPI compatible serial bus flash memory chips are provided for FPGA configuration file and data storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.

EEPROM

There is a 2Kb EEPROM provided on the module TE0821.

LEDs

DDR4 SDRAM

The TE0823 SoM has a 1 GB volatile LPDDR4 SDRAM IC for storing user application code and data.

• Part number: IS43LQ32256A
• Supply voltage: 1.7V ~ 1.95V
• Speed: 3200 Mbps
• Temperature: -40 ~ 95 °C

Gigabyte Ethernet

On-board Gigabit Ethernet PHY (U8) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the ZynqMP Ethernet3 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.00 MHz oscillator (U11).

Clock Sources

USB2.0 Transceiver

Hi-speed USB ULPI PHY (U18) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO52..63, bank 502. The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.00 MHz oscillator (U14).

eMMC Flash Memory

eMMC Flash memory device(U6) is connected to the ZynqMP PS MIO bank 500 pins MIO13..MIO23. eMMC chips IS21ES08G-JCLI (FLASH - NAND Speicher-IC (64 Gb x 1) MMC ) is used.

Programmable Clock Generator

There is a Silicon Labs I²C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I²C bus address 0x70 or 0x71. Default address is 0x70, IN4/I2C_LSB pin must be set to high for address 0x71.

A 25.00 MHz oscillator is connected to the pin IN3 and is used to generate the output clocks. The oscillator has its output enable pin permanently connected to 1.8V power rail, thus making output frequency available as soon as 1.8V is present. Three of the Si5338 clock outputs are connected to the FPGA. One is connected to a logic bank and the other two are connected to the GTR banks.

Once running, the frequency and other parameters can be changed by programming the device using the I²C bus connected between the FPGA (master) and clock generator (slave). For this, proper I²C bus logic has to be implemented in FPGA.

Power and Power-On Sequence

Power Supply

Power supply with minimum current capability of 2.5 A for system startup is recommended.

Power Consumption

* TBD - To Be Determined

Power Distribution Dependencies

Power-On Sequence

Power Rails

Bank Voltages

Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 40 mm × 50 mm.  Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: 8 mm.

PCB thickness: 1.7 mm.

Currently Offered Variants 

Revision History

Hardware Revision History

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

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