Page History

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Overview

The Trenz Electronic TEB0724-02 is a developement carrier board for the TE0724 and compatible modules. It facilitates easy access to all on the module available features. 

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Refer to http://trenz.org/teb0724-info for the current online version of this manual and other available documentation.

Key Features

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Overview

The Trenz Electronic TEB0724-02 is a developement carrier board for the TE0724 and compatible modules. It facilitates easy access to all on the module available features. 

Refer to http://trenz.org/teb0724-info for the current online version of this manual and other available documentation.

Key Features

• Samtec 160 pin board to board connector for 4,0 cm x 6,0 cm module
• 10x 2x6 Pin Pmods, (8 usable as dual Pmods, 1x single Pmod, 1x I²C compatible Pmod)
• MicroUSB to JTAG/UART bridge
• CAN screw terminal
• RJ45 Gigabit Ethernet MagJack connector
• 6x LED, 2x Push Buttons on FPGA
• 1 LED and 1 Push Button on PS
• Power and Reset Push Buttons
• On-board Power Protection Circuit and Power on LED
  
  

Block Diagram

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Block Diagram

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Main Components

Main Components

Table 1: TE0724-02 main components.

1. Module connector for 4,0x6.0 cm module
2. Pmods usabel as dual Pmods, J10, J11, J12, J13, J14, J15, J16, J17  
3. Pmod (single), J20  
4. I2C Pmod, J21
5. CAN screw terminal, J2
6. 5V 2.1mm input jack, J18
7. microUSB J4
8. USB to JTAG/UART bridge FT2232H, U1
9. Configuration EEPROM U3
10. RJ45 Gigabit Ehternet Jack, J3
11. Power Button, S1
12. Reset Button, S3
13. User Button PS, S5
14. User LED (green) PS, D8 
15. 2x User Button PL, S2, S4
16. 6x User LEDs (red) PL, D2-D7 
17. Power LED (green), D36
18. 2x10 Pin header for Boot and Programming options, J6
19. 2x6 Pin header for jumper setting of CAN bus termination resistors, J22
20. microSD Card Slot, J5
21. Dip switches for selecting B_VCCIO_35, S6
22. DCDC (B_VCCIO_35), U8
23. DCDC (B_3.3V), U7

Initial Delivery State

Not programmed.

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Storage device name

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Content

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Notes

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Configuration Signals

The boot device is

Boot Process

The boot device is selected by the mode jumpers on pin header J6. Placing a jumper at pin 13-14 sets Mode0 to low level. Mode1 is set to low level by jumper on over pin 15-16. Boot modes are further described at the corresponding section of the modules, e.g. Table 2, Boot mode selection of TE0724 TRM. Default with no jumpers is boot from SD-Card.

Signals, Interfaces and Pins

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Connections and Interfaces or B2B Pin's which are accessible by User
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Board to Board (B2B) I/Os

I/O signals connected to the B2B connector: 

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Table 3: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors.

The TEB0724 carrier board supplies the attached module with 5V DC. All power rails on the  module and the baseboard are generated from this at the module and routed back the carrier. For detailed information about the pin out, please refer to the Pin-out Tables. 

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JTAG Interface

There is no device with JTAG port on the baseboard. JTAG access to the module is provided through B2B connector J1. This is routed to the carriers USB to JTAG/UART bridge.

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JTAG Signal

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B2B Connector Pin

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Table 4: JTAG interface signals.

System Control  I/O Pins

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Table 5: System Control I/O pins.

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SD Card Interface

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Table 6: SD Card interface signals and connections.

Ethernet Interface

The TEB0724 Carrier Board has a RJ45 Gigabit Ethernet MagJack (J3) with two LEDs. On-board Ethernet MagJack pins are routed to B2B connector J1 via MDI. LEDs are also routed to the B2B connector.

Ethernet PHY connection

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J1-25

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Table 7: Ethernet MagJack

I2C Interface

On-board I²C bus is accaessable with the following pins:

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Table 8: I²C pins.

There are no I2C devices on the base board. Pullup resistors have to be provided by the module.

On-board Peripherals

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Pmods

The GPIOs of the 10 Pmods (J10 to J17, J20, J21) are connected with 100 Ohm differential routing to the B2B connector. J21 is a pure I²C compatible Pmod, without additional signals. The other 9 are GPIO Pmods where despite J20 all others can be used as dual Pmods. By default VCCIO_35 is NOT connected. Via pin header J19 the variable bank power VCCIO_35 for the Pmods J10, J11, J12, J13, J14, J16 can be selected. Respect power regulator limits!

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J1-46

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Table 9: Pmod connections.

USB to JTAG/UART bridge

The TEB0724 carrier board has on-board microUSB 2.0 (J4) high-speed to UART/FIFO IC FT2232H (U1) from FTDI. Channel A can be used as JTAG Interface (MPSSE) to program on module JTAG devices. Channel B can be used as UART Interface routed to via a level shifter to the 1.8V section of the B2B connector, usually connected to the PS of the SoM. There is also a 256-byte serial EEPROM connected to the FT2232H chip pre-programmed with license code to support Xilinx programming tools.

CAN Screw Terminal

The CAN bus is routed to screw terminal J2.

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Table 10: CAN bus connection.

Jumpers on J22-1 to J22-3 and J22-2 to J22-4 connect proper split termination resistors to the CAN bus.

Oscillators

The module has the following reference clock signals provided by on-board oscillators:

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Table 11: Reference clock signals.

On-board LEDs

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MIO user LED

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Table 12: On-board LEDs.

On-board Push Buttons

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S2

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PS MIO user button, pulled up, on push de-asserted

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

I/O signals connected to the B2B connector: 

microUSB JTAG/UART Interface

The microUSB connector provides JTAG access to the module through the carriers USB to JTAG/UART bridge, routed to B2B connector J1. The UART is routed via a levelshifter. There is no device with JTAG port on the baseboard.

SD Card Interface

Ethernet Interface

The TEB0724 Carrier Board has a RJ45 Gigabit Ethernet MagJack (J3) with two LEDs. On-board Ethernet MagJack pins are routed to B2B connector J1 via MDI. LEDs are also routed to the B2B connector.

Ethernet PHY connection

I2C Interface

On-board I²C bus is accaessable with the following pins:

There are no I2C devices on the base board. Pullup resistors have to be provided by the module.

Pmods

The GPIOs of the 10 Pmods (J10 to J17, J20, J21) are connected with 100 Ohm differential routing to the B2B connector. J21 is a pure I²C compatible Pmod, without additional signals. The other 9 are GPIO Pmods where despite J20 all others can be used as dual Pmods.

Via dip switches S6-1 to S6-3 the variable bank power B_VCCIO_35 for the Pmods J10, J11, J12, J13, J14, J16 can be selected. Respect power regulator limits!

CAN Screw Terminal

The CAN bus is routed to screw terminal J2.

Jumpers on J22-1 to J22-3 and J22-2 to J22-4 connect proper split termination resistors to the CAN bus.

Pin Header

Pin Header J6 provides access to power functions, bootmode selection and PMIC In-Circuit Programming (For initial PMIC In-Circuit Programming of the module, Diode D28 has to be removed).

Alternatively to selecting B_VCCIO_35 by using S6 dip switches, VCCIO_35 ( e.g. SoM TE0724, Bank 35) can be selected by removing R45 and adding a jumper on optional J19. In table 18 valid jumper positions are given. Voltages and maximum current ratings could be found in the corresponding TRM of the attached module, (e.g. TE0724 TRM#PowerRails ).

Optional fitted headers J7, J8 and J9 are to provide full access to the Pins at the B2B connector, especially for testing and extension purposes.  Description follows below.

PL Button and LED IOs are additionally routed to optionally assembled pin header J8.

Optional pin header J7 gives access to otherwise not used PS MIO IOs at a 3.3V bank.

Optional pin header J9 gives access to otherwise not used PS MIO IOs at a 1.8V bank.

On-board Peripherals

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USB to JTAG/UART bridge

The TEB0724 carrier board has on-board microUSB 2.0 (J4) high-speed to UART/FIFO IC FT2232H (U1) from FTDI. Channel A can be used as JTAG Interface (MPSSE) to program on module JTAG devices. Channel B can be used as UART Interface routed via a level shifter to the 1.8V section of the B2B connector, usually connected to the PS of the SoM. There is also a 256-byte serial EEPROM connected to the FT2232H chip pre-programmed with license code to support Xilinx programming tools.

Oscillators

The module has the following reference clock signals provided by on-board oscillators:

On-board LEDs

On-board Push Buttons

Dip-Switches

Dip-switch S6-1..3 are used to select the adjustable board power. Tabel 14 shows the signals, table 15 how to adjust the switches for corresponding B_VCCIO_35 Voltages.

Power and Power-On Sequence

Power Consumption

Power supply with minimum current capability of 3A for system startup is recommended.

The maximum power consumption depends on the attached module the design running on the module and additional peripherals.

Xilinx provide a power estimator excel sheets to calculate power consumption for FPGAs. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power Distribution Dependencies

User should also check related module documentation and Xilinx data sheet, respectively.

Power-On Sequence

The power-on sequence is solely controlled by the attached module. The baseboard DCDC regulators U7 and U8 are enabled by the 3.3V rail of the module. Optional sequenzing signals for integration of additional hardware are PWR_GPIO2 and PWR_GPIO4.

If the attached module uses an external bank power VCCIO_35, this has to be powered up after the modules SOCs powerrails are up and before any other signal is applied to the bank IOs. The 1.8V and 3.3V power rails are used for the SD Card level shifter U13. The datasheet states to first power up 1.8V and then 3.3V, this has to be taken into account when reconfiguring the power circuit of the attached SoM.

Power-Off is in reverse order. VCCIO_35 has to be disabled before the SoCs core voltages are turned off.

Power Rails

Some of the power rails are sourced by the attached module, see coresponding TRMs of this for further information (e.g. TE0724 TRM#PowerRails).

Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 105 mm × 100 mm.  Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: 4 mm.

• PCB thickness: 1.6 mm.

• Highest part on PCB: approx. 13.5 mm. Please download the step model for exact numbers.

Currently Offered Variants

Revision History

Hardware Revision History

Table 13: On-board Push Buttons.

Dip-Switches

Dip-switch S6-1..3 are used to select the adjustable board power. Tabel 14 shows the signals, table 15 how to adjust the switches for corresponding B_VCCIO_35 Voltages.

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S6-3

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Table 14: Dip-Switches.

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1.8V

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Table 15: Select B_VCCIO_35 via Dip-Switches.

Pin Header

Pin Header J6 provides access to power functions, bootmode selection and PMIC In-Circuit Programming.

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Table 16: Pin Header J6.

Alternatively to selecting B_VCCIO_35 by using S6 dip switches, VCCIO_35 ( e.g. SoM TE0724, Bank 35) can be selected by removing R45 and adding a jumper on optional J19. In table 18 valid jumper positions are given. Voltages and maximum current ratings could be found in the corresponding TRM of the attached module, (e.g. TE0724 TRM#PowerRails ).

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J19-5

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Table 17: Optional Pin Header J19.

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J19  1-3

VLDO1

3.3V

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J19  4-3

VLDO2

1,8V

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J19  5-3

VLDO34

2,5V

Table 18: J19 Jumper settings for VCCIO_35 voltage selection.

Optional fitted headers J7, J8 and J9 are to provide full access to the Pins at the B2B connector, especially for testing and extension purposes.  Description follows below.

PL Button and LED IOs are additionally routed to optionally assembled pin header J8.

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Table 19: Optional Pin Header J8.

Optional pin header J7 gives access to otherwise not used PS MIO IOs at a 3.3V bank.

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Table 20: Optional Pin Header J7.

Optional pin header J9 gives access to otherwise not used PS MIO IOs at a 1.8V bank.

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J1-42

Table 21: Optional Pin Header J9.

Power and Power-On Sequence

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Power Consumption

The maximum power consumption depends on the attached module the design running on the module and additional peripherals.

Xilinx provide a power estimator excel sheets to calculate power consumption for FPGAs. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

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Table 22: Typical power consumption.

 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of 3A for system startup is recommended.

Power Distribution Dependencies

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User should also check related module documentation and Xilinx data sheet, respectively.

Power-On Sequence

The power-on sequence is solely controlled by the attached module. The baseboard DCDC regulators U7 and U8 are enabled by the 3.3V rail of the module. Optional sequenzing signals for integration of additional hardware are PWR_GPIO2 and PWR_GPIO4. If the attached module uses the adjustable bank power VCCIO_35, this has to be powered up after the modules SOCs powerrails are up and before any other signal is applied to the bank IOs. The 1.8V and 3.3V power rails are used for the SD Card level shifter U13. The datasheet states to first power up 1.8V and then 3.3V, this has to be taken into account when reconfiguring the power circuit of the attached SoM.

Power-Off is in reverse order. VCCIO_35 has to be disabled before the SoCs core voltages are turned off.

Power Rails

Some of the power rails are sourced by the attached module, see coresponding TRMs of this for further information (e.g. TE0724 TRM#PowerRails).

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Power Rail Name

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B2B J1 Pins

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Direction on B2B

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1.8V

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VLDO1

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VBAT

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Table 23 : Board power rails.

Board to Board Connectors

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Variants Currently In Production

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German page

Technical Specifications

Absolute Maximum Ratings

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Parameter

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Units

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Reference Document

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VIN supply voltage

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V

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Storage temperature

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-30

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°C

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Table 24: Board absolute maximum ratings.

Recommended Operating Conditions

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Table 25: Board recommended operating conditions.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Extended grade: 0°C to +85°C.

Industrial grade: -40°C to +85°C.

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 105 mm × 100 mm.  Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: 4 mm.

• PCB thickness: 1.6 mm.

• Highest part on PCB: approx. 13.5 mm. Please download the step model for exact numbers.

All dimensions are given in millimeters.

Scroll Title
title Figure 4: Module physical dimensions drawing.
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Revision History

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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History