Page History
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PSON signal will be enabled/disabled after delay, when Power Button is pressed. Power Button is debounced.
Stage | Power Enable Signal | Enable Power domain | Note |
---|---|---|---|
1 | PSON | ATX PSON (12V from ATX power supply) | Signal will be enabled/disabled after delay, when Power Button is pressed.Power Button is debounced. |
2 | PWROK(ATX Power) | 5V_EN (5V) | Note 1: If S4-4 is on, 5V is always on. S4-4 must be on, if TEBF0808 is used with external 12V instead of ATX Power. |
2 | PWROK | MOD_EN (Module 3.3V), EN_LPD, EN_FPD, EN_PL | Module B2B connector Main Power and enables |
3 | PG_FPD | EN_DDR, EN_PLL_PWR, EN_PSGTR | Module periphery power |
3 | PG_PL | EN_GT_R, EN_GT_L | Module periphery power |
4 | PG_FPD and PG_PL | PER_EN(Periphery 3.3V), EN_1V8(Periphery 1.8V), PCI_SFP_EN (PCIe and SFP) | Carrier periphery power |
4 | PWROK and PG_FPD and PG_PL and PSON and Master CPLD status | FMC_EN (FMC VADJ) | FMC VADJ |
5 | PWROK and PG_FPD and PG_PL and PSON and POK_FMC(VADJ) | FMC_PG_C2M | FMC supply power status to FMC connector |
Note: Power Status is visible on LEDs, see LED section
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S5-1 | S5-2 | Description |
---|---|---|
ON | ON | Default, boot from SD/microSD or SPI Flash if no SD is detected |
OFF | ON | Boot mode PJTAG0from eMMC |
ON | OFF | Boot from eMMCmode PJTAG0 |
OFF | OFF | Boot mode main JTAG |
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RGPIO Pin from FPGA | Value |
---|---|
0 | PLL_RSTn |
1 | PERSTn |
2 | FMC_FAN_EN |
7 | LED_N |
8 | LED_P |
9 | HDLED_N |
10 | HDLED_P |
12-23 | unused |
24-27 | reserved |
28-31 | Interface detection |
LED
This Chapter need redesign for CPLD REV06
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LED2 D6 Green | RGPIO (5) when active else slow_blink when PSON is off else on | ||
---|---|---|---|
LED3 D7 Red | RGPIO (6) when active else not RST_BTN or mode_blink | ||
LED_N | RGPIO (7) when active else off | ||
LED_P | not RGPIO (8) when active else slow_blink when PSON is off else MIO40 | ||
HDLED_N | RGPIO (9) when active else off | ||
HDLED_P | not RGPIO (10) when active else SC0 | ||
XMOD_LED Red | Done Pin: ON is not programmed, OFF programmed |
*slow_blink: ~0,7 Hz
*mode_blink:
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(near FAN1 connector on PCB) | ||
---|---|---|
Power Flags | Blink Sequence | Comment |
PWROK | ******** | ATX Power failed or PCB is powered off |
PG_LPD | *****ooo | Module Low Power Domain failed |
PG_FPD | ****oooo | Module Full Power Domain failed |
PG_PL | ***ooooo | Module PL Power Domain failed |
POK_1V8 or POK_FMC | **oooooo | Carrier 1V8 or FMC VADJ Power Domain failed |
PG_DDR='0' or PG_GT_L='0' or PG_GT_R='0' or PG_PSGT='0' or PG_PLL='0' | *ooooooo | Module DDR, PL GT, PS GT or PLL Power Domain failed |
OFF | All Ready |
LED3 D7 Red (near FAN1 connector on PCB) | ||
---|---|---|
Bode Mode | Blink Sequence | Comment |
Error | ******** | ERROR |
JTAG | *****ooo | JTAG |
PJTAG0 | ****oooo | Boot Mode is set to PJTAG0 |
eMMC | ***ooooo | Boot Mode is set to eMMC |
SPI Boot | **oooooo | Boot Mode is set to QSPI |
SD Boot | *ooooooo | Boot Mode is set to SD |
ON | Reset is on |
XMOD LED Red (XMOD1 on J12 with green dot) | ||
---|---|---|
Status | Blink Sequence | Comment |
PS_INIT_B | ******** | Indicates the PS is not initialized after a power-on reset (POR). |
PS_ERROR_OUT | *****ooo | The PS_ERROR_OUT signal is asserted for accidental loss of power, an error, or an exception in the PMU. |
DONE | ON or OFF | Indicates the PL configuration is completed (LED is OFF). |
LED_P/N (BLUE Power LED on enclosure) | ||
---|---|---|
Status/ User | Blink Sequence | Comment |
Power | ******** (slow blink) | Indicate board is powered off. |
RGPIO controlled | User Defined | RGPIO 14 and 15, if RGPIO is active. |
MIO40 | User Defined | MIO40, if RGPIO is deactivated |
HDLED_P/N (Red HD LED on enclosure) | ||
---|---|---|
Status/ User | Blink Sequence | Comment |
PS_INIT_B | ******** | Indicates the PS is initialized after a power-on reset (POR). |
PS_ERROR_OUT | *****ooo | The PS_ERROR_OUT signal is asserted for accidental loss of power, an error, or an exception in the PMU. |
ERR_STAT | ****oooo | The PS_ERROR_STATUS indicates a secure lockdown state. Alternatively, it can be used by the PMU firmware to indicate system status. |
RGPIO controlled | User Defined | RGPIO 16 and 17, if RGPIO is active |
SC0 | User Defined | SC0 (PL IO), if RGPIO is deactivated |
Blink Frequency:
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Blink Sequence | Comment |
---|
******** | ~5,8 Hz |
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*****ooo | ~0,7 Hz, duty cycle 5/8 |
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****oooo | ~0,7 Hz, duty cycle 4/8 |
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***ooooo | ~0,7 Hz, duty cycle 3/8 |
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**oooooo | ~0,7 Hz, duty cycle 2/8 |
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*ooooooo | ~0,7 Hz, duty cycle 1/8 |
Appx. A: Change History
Revision Changes
CPLD REV04 REV05 to REV05REV06
LED Status changes of LED D2 D3 and HD_LED, XMOD LED
extended Power Management
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Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||||
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| REV06 | REV02, REV03, REV04 |
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2017-11-15 | v.38 | REV06 | REV02, REV03, REV04 | John Hartfiel |
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2017-10-18 | v.36 | REV06 | REV02, REV03, REV04 | John Hartfiel |
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2017-06-20 | v.29 | REV05 | REV02, REV03, REV04 | John Hartfiel |
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2017-06-09 | v.28 | REV05 | REV02, REV03, REV04 | John Hartfiel |
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2017-06-08 | v.23 | REV05 | REV02, REV03, REV04 | John Hartfiel | document
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2017-05-08 | v.22 | REV05 | REV02, REV03, REV04 | John Hartfiel |
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2017-02-08 | v.19 | REV04 | REV02, REV03, REV04 | John Hartfiel |
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2016-04-11 | v.1 | --- |
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All |
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