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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Important General Note:
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Table template:
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| Description | 2020
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Release Notes and Know Issues
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Requirements
Software
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Hardware
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
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Design supports following carriers:
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*used as reference |
Additional HW Requirements:
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*used as reference |
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For general structure and usage of the reference design, see Project Delivery - Xilinx devices
Design Sources
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Additional Sources
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Prebuilt
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Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Design Flow
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
- Xilinx Development Tools#XilinxSoftware-BasicUserGuides
- Vivado Projects - TE Reference Design
- Project Delivery.
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
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Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Code Block language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):
- Press 0 and enter to start "Module Selection Guide"
- Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note Note: Select correct one, see also Vivado Board Part Flow
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
Code Block language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>") TE::hw_build_design -export_prebuilt
Info Using Vivado GUI is the same, except file export to prebuilt folder.
- Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
- use TE Template from "<project folder>\os\petalinux"
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The build images are located in the "<plnx-proj-root>/images/linux" directory
Configure the boot.scr file as needed, see Distro Boot with Boot.scr
- Generate Programming Files with Vitis (recommended)
- Copy PetaLinux build image files to prebuilt folder
copy u-boot.elf, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
Info "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"
Page properties hidden true id Comments This step depends on Xilinx Device/Hardware
for Zynq-7000 series
- copy u-boot.elf, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for ZynqMP
- copy u-boot.elf, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for
Microblaze
- ...
- Generate Programming Files with Vitis
Code Block language py theme Midnight title run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv") TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)
Note TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis
- Copy PetaLinux build image files to prebuilt folder
- Generate Programming Files with Petalinux (alternative), see PetaLinux KICKstart
Launch
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Programming
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Check Module and Carrier TRMs for proper HW configuration before you try any designtry any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select create and open delivery binary folder
Info Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated
QSPI-Boot mode
Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.
- Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Code Block language py theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flash) TE::pr_program_flash -swapp u-boot TE::pr_program_flash -swapp hello_teb0912 (optional)
Note To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup
- Copy image.ub and boot.scr on SD or USB
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Set Boot Mode to QSPI-Boot and insert SD or USB.
- Depends on Carrier, see carrier TRM.
SD-Boot mode
- Copy image.ub, boot.src and Boot.bin on SD
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
Select SD Card as Boot Mode (or QSPI - depending on step 1)
Info Note: See TRM of the Carrier, which is used.
Tip Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
The boot options described above describe the common boot processes for this hardware; other boot options are possible.
For more information see Distro Boot with Boot.scr- (Optional) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
- (Optional) Connect DisplayPort Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)(Optional) Connect Network Cable
Power On PCB
Expand title boot process 1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,
3. U-boot loads Linux Linux (image.ub) from SD/QSPI/... into DDR
Page properties hidden true id Comments This step depends on Xilinx Device/Hardware
for Zynq-7000 series
1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
for ZynqMP???
1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,
2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
for Microblaze with Linux
1. FPGA Loads Bitfile from Flash,
2. MCS Firmware configure SI5338 and starts Microblaze, (only if mcs is available)
3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while),
43. U-boot loads Linux (image.ub) from SD/QSPI/... QSPI Flash into DDR
for native FPGA
...
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
select COM Port
Info Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Linux Console:
Code Block language bash theme Midnight # password disabled petalinux login: root Password: root
Info Note: Wait until Linux boot finished
You can use Linux shell now.
Code Block language bash theme Midnight i2cdetect -y -r 0 (check I2C 1 Bus) dmesg | grep rtc (RTC check) udhcpc (ETH0/1 check) lspci (PCIe check)
Option Features
- Webserver to get access to ZynqMP
- insert IP on web browser to start web interface
- init.sh scripts
- add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")
- This Script file is responsible to read temperature of six temperature sensors on the board. For more information refer to TEB0912 CPLD.
- add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")
- Webserver to get access to ZynqMP
Vivado HW Manager
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Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)
- Control:
- User LED Control (D16, D15)
- Monitoring:
- MGT CLK Measurement:
- Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder). Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz
- Default B229_CLK1: 78,8MHz, B128_CLK1: 150MHz, B129_CLK1: 175MHz, B130_CLK1: 200MHz, B228_CLK1: 125MHz, B23ß_CLK1: 100MHz
- B128_CLK_P, B131_CLK_P: 125MHz
- B129_CL_P, B130_CLK_P: 312,5MHz
- B224_CLK1 - B231_CLK1: 125MHz
- B65_HP_CLK_P: 200MHz
- MGT CLK Measurement:
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Constrains
Basic module constrains
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] |
Design specific constrain
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# AB34 MGT_128_CLK_P # AB35 MGT_128_CLK_N # W32 MGT_129_CLK_P # W33 MGT_129_CLK_N # R32 MGT_130_CLK_P # R33 MGT_130_CLK_N # L32 MGT_131_CLK_P # L33 MGT_131_CLK_N set_property PACKAGE_PIN AB34 [get_ports {CLK_IN_D_128_131_clk_p[0]}] set_property PACKAGE_PIN W32 [get_ports {CLK_IN_D_128_131_clk_p[1]}] set_property PACKAGE_PIN R32 [get_ports {CLK_IN_D_128_131_clk_p[2]}] set_property PACKAGE_PIN L32 [get_ports {CLK_IN_D_128_131_clk_p[3]}] # AB11 MGT_228_CLK_N # AB12 MGT_228_CLK_P # Y11 MGT_229_CLK_N # Y12 MGT_229_CLK_P # V11 MGT_230_CLK_N # V12 MGT_230_CLK_P # T11 MGT_231_CLK_N # T12 MGT_231_CLK_P set_property PACKAGE_PIN AB12 [get_ports {CLK_IN_D_228_231_clk_p[0]}] set_property PACKAGE_PIN Y12 [get_ports {CLK_IN_D_228_231_clk_p[1]}] set_property PACKAGE_PIN V12 [get_ports {CLK_IN_D_228_231_clk_p[2]}] set_property PACKAGE_PIN T12 [get_ports {CLK_IN_D_228_231_clk_p[3]}] # AK11 MGT_224_CLK_N # AK12 MGT_224_CLK_P # AH11 MGT_225_CLK_N # AH12 MGT_225_CLK_P # AF11 MGT_226_CLK_N # AF12 MGT_226_CLK_P # AD11 MGT_227_CLK_N # AD12 MGT_227_CLK_P set_property PACKAGE_PIN AK12 [get_ports {CLK_IN_D_224_227_clk_p[0]}] set_property PACKAGE_PIN AH12 [get_ports {CLK_IN_D_224_227_clk_p[1]}] set_property PACKAGE_PIN AF12 [get_ports {CLK_IN_D_224_227_clk_p[2]}] set_property PACKAGE_PIN AD12 [get_ports {CLK_IN_D_224_227_clk_p[3]}] # B65 CLK set_property PACKAGE_PIN AR24 [get_ports {CLK_IN_D_B65_clk_p[0]}] set_property IOSTANDARD LVDS [get_ports {CLK_IN_D_B65_clk_p[0]}] #get_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN D3 } [get_ports {+3.3V_ETH_PHY_EN}] #removed on REV02 --> use unused pullup for rev01 #set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN C1 } [get_ports {+3.3V_M2_KeyE_EN}] #removed on REV02 --> use unused pullup for rev01 #set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN G10 } [get_ports {ssd1_perstn[0]}] set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN B6 } [get_ports {LED[0]}] set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN B5 } [get_ports {LED[1]}] set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN A5 } [get_ports {LED[2]}] set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN A4 } [get_ports {LED[3]}] #set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN G13 } [get_ports {M2M_SLEEP[0]}] #set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN F13 PULLUP TRUE } [get_ports {ssd1_wake[0]}] #removed on REV02 --> use unused pullup for rev01 # # B10 FF10_MPRS # C10 FF01_MPRS # C11 FF00_MPRS # D11 FF31_MPRS # D12 FF30_MPRS # E10 FF20_MPRS # E11 FF11_MPRS # E12 FF21_MPRS # J12 FFA_SDA # J14 FFA_SCL # K10 FFD_MPRS # K11 FFD_MSEL # K12 FFC_MPRS # K14 FFA_INTL # L10 FFD_INTL # L12 FFC_MSEL # L13 FFA_MPRS # L14 FFA_MSEL # M10 FFD_SDA # M11 FFB_SDA # M13 FFB_SCL # N10 FFD_SCL # N11 FF_AB_RSTL # N12 FF_CD_RSTL # N13 FFB_MSEL # N14 FFB_INTL # P12 FFC_INTL # P13 FFC_SCL # P14 FFB_MPRS # R14 FFC_SDA # # E3 PEX_FATAL_ERRORn REV02 only # E4 PEX_GPIO3 REV02 only # E5 PEX_LANE_GOOD2n REV02 only # F4 PEX_LANE_GOOD1n REV02 only # F5 PEX_LANE_GOOD0n REV02 only # # F6 DSPLL1_RST_N # F7 DSPLL0_RST_N # # G11 W_DISABLE1n REV01 other name # G12 W_DISABLE2n REV01 other name # G13 M2M_SLEEP REV02 only # # F10 SSD1_CLKRQ REV01 only # F13 SSD1_WAKE REV01 only # G10 SSD1_PERSTn REV01 only # G13 M2M_SLEEP REV01 other nameSSD1_SLEEP # set_property -dict { IOSTANDARD LVCMOS18 PACKAGE_PIN AK23 } [get_ports {BUTTON[0]}] set_property -dict { IOSTANDARD LVCMOS18 PACKAGE_PIN AL23 } [get_ports {BUTTON[1]}] set_property -dict { IOSTANDARD LVCMOS18 PACKAGE_PIN AJ24 } [get_ports {BUTTON[2]}] set_property -dict { IOSTANDARD LVCMOS18 PACKAGE_PIN AK24 } [get_ports {BUTTON[3]}] set_property -dict { IOSTANDARD DIFF_SSTL12_DCI PACKAGE_PIN G26 } [get_ports {diff_clock_rtl_clk_p}] set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN N24 } [get_ports {ddr4_act_n}] set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN J27 } [get_ports {ddr4_adr[0]}] set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN J24 } [get_ports {ddr4_adr[1]}] set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN F27 } [get_ports {ddr4_adr[2]}] set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN E26 } [get_ports {ddr4_adr[3]}] set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN M25 } [get_ports {ddr4_adr[4]}] set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN D26 } [get_ports {ddr4_adr[5]}] set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN K27 } [get_ports {ddr4_adr[6]}] set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN E27 } [get_ports {ddr4_adr[7]}] set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN K26 } [get_ports {ddr4_adr[8]}] set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN H26 } [get_ports {ddr4_adr[9]}] set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN L24 } [get_ports {ddr4_adr[10]}] set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN F28 } [get_ports {ddr4_adr[11]}] set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN J23 } [get_ports {ddr4_adr[12]}] set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN J26 } [get_ports {ddr4_adr[13]}] set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN L23 } [get_ports {ddr4_adr[14]}] set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN K24 } [get_ports {ddr4_adr[15]}] set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN H23 } [get_ports {ddr4_adr[16]}] ## /* dummy for ddr4-ram */ set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN G25 } [get_ports {ddr4_adr17[0]}] set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN N26 } [get_ports {ddr4_ba[0]}] set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN G23 } [get_ports {ddr4_ba[1]}] set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN M23 } [get_ports {ddr4_bg[0]}] #set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN P23 } [get_ports {ddr4_bg[1]}] ## /* dummy for ddr4-ram */ set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN P23 } [get_ports {ddr4_bg1[0]}] set_property -dict { IOSTANDARD DIFF_SSTL12_DCI PACKAGE_PIN F25 F25 } [get_ports {ddr4_ck_t[0]}] set_property -dict { IOSTANDARD DIFF_SSTL12_DCI PACKAGE_PIN E25 } [get_ports {ddr4_ck_c[0]}] set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN L25 } [get_ports {ddr4_cke[0]}] set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN N23 } [get_ports {ddr4_cs_n[0]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN P18 } [get_ports {ddr4_dm_n[0]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN K19 } [get_ports {ddr4_dm_n[1]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN D19 } [get_ports {ddr4_dm_n[2]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN G22 } [get_ports {ddr4_dm_n[3]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN K29 } [get_ports {ddr4_dm_n[4]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN E29 } [get_ports {ddr4_dm_n[5]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN C36 } [get_ports {ddr4_dm_n[6]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN E32 } [get_ports {ddr4_dm_n[7]}] set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN N19 } [get_ports {ddr4_dqs_c[0]}] set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN J22 } [get_ports {ddr4_dqs_c[1]}] set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN B21 } [get_ports {ddr4_dqs_c[2]}] set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN E20 } [get_ports {ddr4_dqs_c[3]}] set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN F30 } [get_ports {ddr4_dqs_c[4]}] set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN A32 } [get_ports {ddr4_dqs_c[5]}] set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN A40 } [get_ports {ddr4_dqs_c[6]}] set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN C34 } [get_ports {ddr4_dqs_c[7]}] set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN N20 } [get_ports {ddr4_dqs_t[0]}] set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN K22 } [get_ports {ddr4_dqs_t[1]}] set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN C21 } [get_ports {ddr4_dqs_t[2]}] set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN F20 } [get_ports {ddr4_dqs_t[3]}] set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN G30 } [get_ports {ddr4_dqs_t[4]}] set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN B31 } [get_ports {ddr4_dqs_t[5]}] set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN A39 } [get_ports {ddr4_dqs_t[6]}] set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN D34 } [get_ports {ddr4_dqs_t[7]}] set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN H24 } [get_ports {ddr4_odt[0]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN N25 } [get_ports {ddr4_reset_n}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN N21 } [get_ports {ddr4_dq[0]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN M18 } [get_ports {ddr4_dq[1]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN M21 } [get_ports {ddr4_dq[2]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN M20 } [get_ports {ddr4_dq[3]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN P21 } [get_ports {ddr4_dq[4]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN L18 } [get_ports {ddr4_dq[5]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN M22 } [get_ports {ddr4_dq[6]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN L19 } [get_ports {ddr4_dq[7]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN H19 } [get_ports {ddr4_dq[8]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN L20 } [get_ports {ddr4_dq[9]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN H20 } [get_ports {ddr4_dq[10]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN K21 } [get_ports {ddr4_dq[11]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN G20 } [get_ports {ddr4_dq[12]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN K20 } [get_ports {ddr4_dq[13]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN H21 } [get_ports {ddr4_dq[14]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN J21 } [get_ports {ddr4_dq[15]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B22 } [get_ports {ddr4_dq[16]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN C20 } [get_ports {ddr4_dq[17]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A22 } [get_ports {ddr4_dq[18]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A19 } [get_ports {ddr4_dq[19]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B23 } [get_ports {ddr4_dq[20]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B20 } [get_ports {ddr4_dq[21]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A23 } [get_ports {ddr4_dq[22]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A20 } [get_ports {ddr4_dq[23]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN F22 } [get_ports {ddr4_dq[24]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN E19 } [get_ports {ddr4_dq[25]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN E22 } [get_ports {ddr4_dq[26]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN D21 } [get_ports {ddr4_dq[27]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN F23 } [get_ports {ddr4_dq[28]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN F19 } [get_ports {ddr4_dq[29]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN D22 } [get_ports {ddr4_dq[30]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN E21 } [get_ports {ddr4_dq[31]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN F31 } [get_ports {ddr4_dq[32]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN J28 } [get_ports {ddr4_dq[33]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN J30 } [get_ports {ddr4_dq[34]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN H28 } [get_ports {ddr4_dq[35]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN F32 } [get_ports {ddr4_dq[36]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN G28 } [get_ports {ddr4_dq[37]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN H30 } [get_ports {ddr4_dq[38]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN F29 } [get_ports {ddr4_dq[39]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN E31 } [get_ports {ddr4_dq[40]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN C30 } [get_ports {ddr4_dq[41]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN C31 } [get_ports {ddr4_dq[42]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B30 } [get_ports {ddr4_dq[43]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN D31 } [get_ports {ddr4_dq[44]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN C29 } [get_ports {ddr4_dq[45]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A30 } [get_ports {ddr4_dq[46]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A29 } [get_ports {ddr4_dq[47]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN C42 } [get_ports {ddr4_dq[48]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B36 } [get_ports {ddr4_dq[49]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B40 } [get_ports {ddr4_dq[50]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B37 } [get_ports {ddr4_dq[51]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B42 } [get_ports {ddr4_dq[52]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A37 } [get_ports {ddr4_dq[53]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B41 } [get_ports {ddr4_dq[54]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A38 } [get_ports {ddr4_dq[55]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B35 } [get_ports {ddr4_dq[56]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B32 } [get_ports {ddr4_dq[57]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A33 } [get_ports {ddr4_dq[58]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN D33 } [get_ports {ddr4_dq[59]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A35 } [get_ports {ddr4_dq[60]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A34 } [get_ports {ddr4_dq[61]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN C33 } [get_ports {ddr4_dq[62]}] set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B33 } [get_ports {ddr4_dq[63]}] set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN J9 } [get_ports {IIC_0_scl_io}] set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN H9 } [get_ports {IIC_0_sda_io}] #create_clock -name c0_sys_clk -period 4.998 [get_ports diff_clock_rtl_clk_p] |
Software Design - Vitis
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Application
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---------------------------------------------------------- FPGA Example ----------------------------------------------------------FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 20202022.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 20202022.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: ---------------------------------------------------------- fsblTE modified 20202022.2 FSBL General:
Module Specific:
fsbl_flashTE modified 2020.2 FSBL General:
---------------------------------------------------------- ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 20202022.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2020.2 FSBL General:
Module Specific:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: ---------------------------------------------------------- hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
zynqmp_fsbl
TE modified 20202022.2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
- General Changes:
- Display FSBL Banner and Device Name
Module Specific:
- Add Files: all TE Files start with te_*
- Si5395 Configuration
- PCIe and eth reset
zynqmp_fsbl_flash
TE modified 2020.2 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
- _*
- Si5395 DSPLL0 (U64) configuration
- Si5395 DSPLL1 (U65) configuration
- PCIe and eth reset
zynqmp_pmufw
Xilinx default PMU firmware.
----------------------------------------------------------
General Example:
hello_teb0912
Hello TEB0912 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Software Design - PetaLinux
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For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
--get-hw-description
Changes:
- add new flash partition for bootscr and sizing
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0x3000000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_SIZE=0x2000000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x40000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME="bootscr"
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_SIZE=0x80000
- Identification
- CONFIG_SUBSYSTEM_HOSTNAME="Trenz"
- CONFIG_SUBSYSTEM_PRODUCT="TEB0912"
U-Boot
Start with petalinux-config -c u-boot
Changes:
- MAC from eeprom together with uboot and device tree settings:
- CONFIG_ENV_OVERWRITE=y
- CONFIG_ZYNQ_MAC_IN_EEPROM is not set
- CONFIG_NET_RANDOM_ETHADDR is not set
- Boot Modes:_IS_NOWHERE=y#
- CONFIG_QSPI_BOOT=y
- CONFIG_SD_BOOT=y
- CONFIG_ENV_IS_IN_FAT is not set
- CONFIG_ENV_IS_IN_NAND is not set
- CONFIG_ENV_IS_IN_SPI_FLASH is not
- set
- CONFIG_SYS_REDUNDAND_ENVIRONMENT is not set
- CONFIG_BOOT_SCRIPT_OFFSET=0x5040000
- Identification
- CONFIG_IDENT_STRING=" TEB0912"
Change platform-top.h:
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Device Tree
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/include/ "system-conf.dtsi" /*-------------------------- QSPI -------------------------*/ &qspi { #address-cells = <1>; #size-cells }; /* I2C Bus on PL for CPLD I2C controller */ &axi_iic_0 { iexp@20 { // GPIO in CPLD #gpio-cells = <2>= <0>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; }; }; /*------------------ SD1 with level shifter ---------------*/ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; no-1-8-v; //compatible = "ti,pcf8574" disable-wp; }; &pinctrl0 { status = "okay"; reg = <0x20>; pinctrl_sdhci1_default: sdhci1-default { gpio-controller;mux { groups = "sdio1_0_grp"; function = }"sdio1"; }; /* I2C Bus on PS MIO */ &i2c1 { }; i2cswitch@75conf { /* u35 */ compatiblegroups = "nxp,pca9544sdio1_0_grp"; #address-cells slew-rate = <1>; #size-cells = <0>; reg io-standard = <0x70><1>; i2c@0 { /* DSPLL0*/ bias-disable; }; /* #address-cells = <1>;mux-cd { #size-cells = <0>groups = "sdio1_cd_0_grp"; regfunction = <0>"sdio1_cd"; }; i2c@1 { /* DSPLL1*/conf-cd { groups = "sdio1_cd_0_grp"; #address-cells = <1>; bias-high-impedance; bias-pull-up; #size-cells = <0>; slew-rate = <1>; regio-standard = <1>; }; i2c@2 { /* J34*/mux-wp { #address-cells = <1>groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; #size-cells = <0>}; conf-wp { reg groups = <2>"sdio1_wp_0_grp"; }; i2c@3 { /* J34*/ bias-high-impedance; bias-pull-up; #addressslew-cellsrate = <1>; io-standard = <1>; #size-cells = <0>}; */ }; }; /*------------------------- ETH reg = <3>; PHY -----------------------*/ &gem2 { status }= "okay"; phy-handle = }<ðernet_phy2>; }; /* QSPI */ &qspi { nvmem-cells = <ð2_addr>; #addressnvmem-cell-cellsnames = <1>"mac-address"; mdio { #size-cells = <0>; status = "okay"; ethernet_phy1: ethernet-phy@0 { flash0: flash@0 { //compatible = "jedecmarvell,spi-nor88e1510"; reg = <0x0> <0>; }; #address-cells = <1>; ethernet_phy2: ethernet-phy@1 { #size-cells = <1>; }; }; /* SD1 with level shifter */ &sdhci1 { //compatible = "marvell,88e1510"; pinctrl-namesreg = "default"<1>; pinctrl-0 = <&pinctrl_sdhci1_default> }; no-1-8-v }; }; &pinctrl0gem3 { status = "okay"; pinctrl_sdhci1_default: sdhci1-default {phy-handle = <ðernet_phy1>; nvmem-cells = <ð1_addr>; mux { nvmem-cell-names = "mac-address"; groupsphy-mode = "sdio1_0_grprgmii-id"; }; /*-------------------- I2C Bus on function = "sdio1"; }; PL ----------------------*/ /* for CPLD I2C controller */ &axi_iic_0 { confiexp@20 {// GPIO in CPLD groups#gpio-cells = "sdio1_0_grp"<2>; slew-rate//compatible = <1>"ti,pcf8574"; io-standardreg = <1><0x20>; biasgpio-disablecontroller; }; /* mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd}; }; /*----------------- I2C Bus on PS MIO 34,35 ---------------*/ /* on MIO */ &i2c0 { eeprom51: eeprom@51 { compatible = groups = "sdio1_cd_0_grp"microchip,24aa025", "atmel,24c02"; reg bias-high-impedance= <0x51>; bias-pull-up; #address-cells = <1>; slew#size-ratecells = <1>; eth2_addr: eth-mac-addr@FA { io-standard reg = <1><0xFA 0x06>; }; }; mux-wp { eeprom52: eeprom@52 { groupscompatible = "sdio1_wp_0_grpmicrochip,24aa025", "atmel,24c02"; reg function = "sdio1_wp"<0x52>; }; conf-wp {#address-cells = <1>; groups#size-cells = "sdio1_wp_0_grp"<1>; bias-high-impedance;eth1_addr: eth-mac-addr@FA { reg bias-pull-up= <0xFA 0x06>; slew-rate = <1>}; }; io-standard = <1>; eeprom53: eeprom@53 { }compatible = "microchip,24aa025", "atmel,24c02"; */ reg = <0x53>; }; }; /* ETH PHY */ eeprom56: eeprom@56 { /* Note: gem1 on REV01 */ &gem2 { compatible status = "okay= "microchip,24lc128", "atmel,24c128"; phy-mode = "rgmii-id"; phy-handlereg = <ðernet_phy1>;<0x56>; ethernet_phy0: ethernet-phy@0 { }; rtc@6F { compatible = "marvell,88e1510"; // Real Time Clock regcompatible = <0>"isl12022"; reg = <0x6F>; #address-cells = <0x1>}; }; &rtc { status = #size-cells = <0x1>; }; ethernet_phy1: ethernet-phy@1 { "disabled"; }; /*----------------- I2C Bus on PS MIO 28,29 ---------------*/ &i2c1 { i2cswitch@75 { // u35 compatible = "marvellnxp,88e1510pca9544"; reg #address-cells = <1>; #address#size-cells = <0x1><0>; reg = <0x70>; #size-cells = <0x1> i2c-mux-idle-disconnect; }; }; &gem3i2c@0 { // DSPLL0 status = "okay"; phy-modereg = "rgmii-id"<0>; phy-handle = <ðernet_phy0>; }; /* USB REV01 only */ i2c@1 { //* &dwc3_0 { DSPLL1 status = "okay"; dr_modereg = "host"<1>; maximum-speed = "high-speed"}; /delete-property/phy-names; i2c@2 { /delete-property/phys;/ J34 /delete-property/snps,usb3_lpm_capable; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; }; reg = <2>; &usb0 {}; status = "okay"; i2c@3 { /delete-property/ clocks;J34 /delete-property/ clock-names; clocksreg = <0x3 0x20><3>; clock-names = "bus_clk"}; }; }; */ |
Must be add manually, see template
Kernel
Start with petalinux-config -c kernel
Changes:
- Only needed to fix JTAG Debug issue:# CONFIG_CPU_IDLE is not set
- # CONFIG_CPU_FREQ is not set
- Support PCIe memory cardCONFIG_EDAC_CORTEX_ARM64=y
- CONFIG_NVME_CORE=y
- CONFIG_BLK_DEV_NVME=y
- # CONFIG_NVME_MULTIPATH is not set
- # CONFIG_NVME_HWMON is not set
- CONFIG_NVME_TARGET=y
- # CONFIG_NVME_TARGET_
- PASSTHRU is not set
- # CONFIG_NVME_TARGET_
- LOOP is not set
- # CONFIG_
- CONFIG_NVM_PBLK=y
- NVME_TARGET_FC is not set
- # CONFIG_NVME_TARGET_TCP is not set
Rootfs
Start with petalinux-config -c rootfs
Changes:
- For web server app:
- CONFIG_
- busybox-
- httpd=y
- For additional test tools only:
- CONFIG_
- i2c-
- tools=y
- CONFIG_packagegroup-petalinux-utils=y (util
- -linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
- For auto login:
- CONFIG_auto-login=y
- CONFIG_ADD_EXTRA_USERS="root:root;petalinux:;"
FSBL patch (alternative for vitis fsbl trenz patch)
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw"
Applications
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"
startup
Script App to load init.sh from SD Card if available.
webfwu
Webserver application suitable for Zynq ZynqMP access. Need busybox-httpd
Additional Software
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SI5395 of carrier board DSPLL0 (U64)
File location "<project folder>\misc\PLL\Si5395-*_DSPLL0_*.slabtimeproj"
General documentation how you work with this project will be available on Si5395
SI5395 of carrier board DSPLL1 (U65)
File location "<project folder>\misc\PLLSI\Si5395-*_DSPLL1_*.slabtimeproj"
General documentation how you work with this project will be available on Si5395
App. A: Change History and Legal Notices
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Document Change History
To get content of older revision go to "Change History" of this page and select older document revision number.
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Legal Notices
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