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Overview
The Trenz Electronic TE0xxx-xx ... is an industrial-grade ... module ... based on Xilinx ..TEM0005-02 is a low-cost module with Microsemi SmartFusion2 SoC and 32 MByte flash memory for configuration and operation. SmartFusion2 combines a 166 MHz Cortex-M3 MCU with 256 KByte Flash and 80 KByte SRAM as well as 12 kLUT FPGA Core Logic.
Refer to http://trenz.org/tem0005-info for the current online version of this manual and other available documentation.
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Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options Key Features' must be split into 6 main groups for modules and mainboards: - SoC/FPGA
- Package: SFVC784
- Device: ZU2...ZU5*
- Engine: CG, EG, EV*
- Speed: -1LI, -2LE,*, **
- Temperature: I, E,*, **
- RAM/Storage
- Low Power DDR4 on PS
- Data width: 32bit
- Size: def. 2GB*
- Speed:***
- eMMC
- Data width: 8Bit
- size: def. 8GB *
- QSPI boot Flash in dual parallel mode (size depends on assembly version)
- Data width: 8bit
- size: def. 128MB *
- HyperRAM/Flash (optional, default not assembled)
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
- On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
- Interface
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, Sata, PCIe, DP)
- MIO for UART
- MIO for SD
- MIO for PJTAG
- JTAG
- Ctrl
- Power
- 3.3V-5V Main Input
- 3.3V Controller Input
- Variable Bank IO Power Input
- Dimension
- Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
Key Features' must be split into 6 main groups for carrier: - Modules
- TE0808, TE807, TE0803,...
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
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- <Replace for module use "SoC/FPGA" for Carrier "Modules">
- Package: VFG400
- Device: M2S010, M2S050 *
- Engine: 166Mhz 32Bit ARM Cortex-M3
- Speed: Standard
- Temperature: C, I*
- ...
- RAM/Storage
- On Board
- Interface
- Power
- Dimension
- Low Power DDR3
- Data width: 16bit
- Size: def. 2Gb
- SPI Flash
- 2Kb EEPROM
- On Board
- Crypto Authentication IC
- Voltage monitor IC
- 10/100 Mbps PHY Ethernet
- Interface
- Power
- 3.3V supplied from carrier
- Dimension
- Notes
- * depends on assembly version
Notes
Block Diagram
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add drawIO object here.
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| Scroll Title |
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| anchor | Figure_OV_BD |
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| title | TEM0005 block diagram |
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| Scroll Ignore |
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drawio | border | false| scroll-office | true |
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| scroll-chm | true |
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| scroll-docbook | true |
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| scroll-eclipsehelp | true |
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| scroll-epub | true |
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| scroll-html | true |
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| | | diagramName | TEM0005_OV_BD |
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| simpleViewer | false |
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width | | links | auto |
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tbstyle | | draw.io Diagram |
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| border | false |
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| diagramName | TEM0005_OV_BD |
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| simpleViewer | false |
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| width | 639 |
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| links | auto |
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| tbstyle |
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| hidden | | diagramDisplayName | |
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| lbox | true |
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| diagramWidth | 641 |
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Main Components
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| Scroll Title |
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| anchor | Figure_OV_MC |
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| title | TEM0005 main components |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| diagramName | TEM0005_OV_MC |
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| simpleViewer | false |
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| width | 600 |
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| links | auto |
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| tbstyle | hidden |
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| diagramDisplayName | |
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| lbox | true |
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| diagramWidth | 641 |
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| revision | 320 |
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Initial Delivery State
- Microsemi SmartFusion2 SoC, U2
- Dual DCDC Regulator, U7
- EEPROM, U4
- 10/100 Mb Ethernet, U1
- QSPI Flash, U3
- Authentication IC, U6
- DDR3 Memory, U5
- B2B Connector, J1
Initial Delivery State
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Notes : Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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| Scroll Title |
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| anchor | Table_OV_IDS |
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| title | Initial delivery state of programmable devices on the module |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Storage device name | Content | Notes |
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Quad SPI Flash | Not Programmed |
| | EEPROM | Not Programmed |
| | CryptoAuthentication | Not ProgrammedSystem Controller CPLD |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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| Scroll Title |
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| anchor | Table_OV_BPRST |
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| title | Boot Reset process. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Scroll Title |
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| anchor | Table_OV_RST |
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| title | Reset process. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Signal | B2B | I/O | Note |
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| B2B | I/O | Note |
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RESET
| J1-11 |
| Active low reset |
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Signals, Signals, Interfaces and Pins
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Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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FPGA bank number and number of I/O signals connected to the B2B connector:, J1.
| Scroll Title |
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| anchor | Table_SIP_B2B |
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| title | General PL I/O to B2B connectors information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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B2B Connector| Interface | I/O Signal Count | Voltage Level | Notes |
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JTAG access to the TExxxx SoM through B2B connector JMX.
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| anchor | Table_SIP_JTG |
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| title | JTAG pins connection |
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JTAG Signal
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B2B Connector
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MIO Pins
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.
Example:
| Bank 1 | GPIO | 8x Single Ended | 3.3V |
| | UART | 4x Single Ended | 3.3V |
| | I2C | 2x Single Ended | 3.3V |
| | GOLDEN | 1x Single Ended | 3.3V |
| | Bank 2 | ULPI/I/O | 12x Single Ended | 3.3V |
| | I2C | 2x Single Ended | 3.3V |
| | GPIO | 10x Single Ended | 3.3V |
| | SC SPI | 4x Single Ended | 3.3V |
| | SPI1 | 7x Single Ended | 3.3V |
| | Bank 3 | JTAG | 5x Single Ended | 3.3V |
| | Reset | 1x Single Ended | 3.3V |
| | Bank 4 | I/O | 24x Single Ended/12 LVDS pairs | 3.3V |
| | Bank 6 | I/O | 28x Single Ended/14 LVDS pairs | VDDI6 | max 2.5V | | Bank 7 | I/O | 4x Single Ended | 3.3V |
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JTAG Interface
JTAG access to the TEM0005 SoM through B2B connector J1.
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SPI_CS , SPI_DQ0... SPI_DQ3
SPI_SCK
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| Scroll Title |
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| anchor | Table_SIP_MIOsJTG |
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| title | MIOs JTAG pins connection |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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JTAG Signal | B2B Connector |
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| TMS | J1-14 | | TDI | J1-8 | | TDO | J1-10 | | TCK | J1-12 | | TRST | J1-7 |
MIO Pin | Connected to | B2B | Notes
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Test Points
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example: | Test Point | Signal | B2B | Notes |
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| 10 | PWR_PL_OK | J2-120 |
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| Scroll Title |
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| anchor | Table_SIP_TPs |
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| title | Test Points Information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Test Point | Signal | Connected to | Notes |
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| TP1 | CLKOUT | Regulator, U7 |
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On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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| Scroll Title |
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| anchor | Table_OBP |
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| title | On board peripherals |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Chip/Interface | Designator | Notes |
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| 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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(Quad) SPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
The TEM0005 is equipped with a (Q)SPI flash memory, U3 provided in order to store data and configuration.
| Scroll Title |
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| anchor | Table_OBP_SPI |
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| title | Quad SPI interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Schematic | U?? Pin | Notes |
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| | sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic | U3 Pin | Connected to | Notes |
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| SPI0_SS0 | nCE | FPGA Bank 2 |
| | SPI0_CLK | SCK | FPGA Bank 2 |
| | SPI0_SDO | SI/IO0 | FPGA Bank 2 |
| | SPI0_SDI | SO/IO0 | FPGA Bank 2 |
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EEPROM
The TEM0005 is equipped with an EEPROM IC, U4. The I2C signals are connected to authentication IC as well.
| Scroll Title |
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| anchor | Table_OBP_RTCEEP |
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| title | I2C EEPROM interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Scroll Title |
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| anchor | Table_OBP_I2C_RTC |
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| title | I2C Address for RTC |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | I2C Address | Designator | Notes |
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| Scroll Title |
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| anchor | Table_OBP_EEPI2C_EEPROM |
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| title | I2C address for EEPROM interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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MIO Pin| Schematic | U?? Pin | Notes | | I2C Address | Designator | Notes |
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| SCL/SDA | 0x70 | U4 |
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Authentication IC
There is an Authentication IC ATECC608A provided on TEM0005, The IC is connected to I2C0 bus.
| Scroll Title |
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| anchor | Table_OBP_I2C_EEPROMAuth |
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| title | I2C address for EEPROMAuthentication IC information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | I2C Address | Designator | Notes |
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| Pin | Schematic | Notes |
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| SCL | I2C0_SCL | Serial Clock | | SDA | I2C1_SCL | Serial Data |
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| Scroll Title |
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| anchor | Table_OBP_I2C_LEDAuthentication IC |
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| title | On-board LEDsI2C address for Authentication IC |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Pin | I2C Address | Designator | Notes |
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Color | Connected to | Active Level | Note | |
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| SCL/SDA | 0xC0 | U6 | This is the default value, which can be changed, see device datasheet. |
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DDR3L SDRAM
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE???? TEM0005 SoM has ??? GByte volatile DDR3 2 Gb volatile DDR3L SDRAM IC for storing user application code and data.
- Part number: IS43TR16128CL-125KBLI
- Supply voltage: 1.5 V
- Speed:
- NOR Flash
- Temperature:
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- Temperature: -40 to 95 °C
Ethernet Transceiver
On board 10/100 Mbps Ethernet Transceiver U1 is provided on the module TEM0005.
| Scroll Title |
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| anchor | Table_OBP_ETH |
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| title | Ethernet PHY to Zynq SoC connections |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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U?? | U1 Pin | Signal Name | Connected |
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toSignal Description | Note | |
CAN Transceiver
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| anchor | Table_OBP_CAN |
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| title | CAN Tranciever interface MIOs |
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| anchor | Table_OBP_CLK |
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| title | Osillators |
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Programmable Clock Generator
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| to | Note |
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| RXM/RXP | ETH1_RX | B2B, J1 |
| | TXM/TXP | ETH1_TX | B2B, J1 |
| | LED0/NWAYEN | ETH1_LED0 | B2B, J1 |
| | LED1/SPEED | ETH1_LED1 | B2B, J1 |
| | MDIO | ETH1_MDIO | FPGA Bank 7, U2 |
| | MDC | ETH1_MDC | FPGA Bank 7, U2 |
| | REXT | - | GND |
| | INTRP | ETH1_INTRP | FPGA Bank 7, U2 |
| | XO/XI | - | Crystal Oscillator, Y3 |
| | nRST | ETH1_RST | FPGA Bank 7, U2 |
| | CONFIG0...2 | ETH1_COL/CRC/RXDV | FPGA Bank 7, U2 |
| | TXC | ETH1_TXC | FPGA Bank 7, U2 |
| | TXEN | ETH1_TXEN | FPGA Bank 7, U2 |
| | TXD0...3 | ETH1_TXD0...3 | FPGA Bank 7, U2 |
| | RXD0...3 | ETH1_RXD0...3 | FPGA Bank 7, U2 |
| | RXC | ETH1_RXC | FPGA Bank 7, U2 |
| | RXCER | ETH1_RXCER | FPGA Bank 7, U2 |
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Clock Sources
| Scroll Title |
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| anchor | Table_OBP_PCLKCLK |
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| title | Programmable Clock Generator Inputs and OutputsOsillators |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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U?? Pin
| Signal | Connected to | Direction | Note |
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IN0 | IN1 | IN2 | IN3 | XAXB | SCLK | SDA | OUT0 | OUT1 | OUT2 | OUT3 | OUT4 | OUT5 | OUT6 | OUT7 | OUT8/OUT9 |
Power and Power-On Sequence
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
- Power on-sequence
- Power distribution
- Voltage monitoring circuit
| Note |
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For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" . |
| Designator | Description | Frequency | Note |
|---|
| Y3 | Crystal Oscillator | 25 MHz | Connected to ETH PHY |
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Power and Power-On Sequence
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
Power supply with minimum current capability of 1.5 A for system startup is recommended.
Power Consumption
| Scroll Title |
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| anchor | Table_PWR_PC |
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| title | Power Consumption |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Power Input Pin | Typical Current |
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| VIN | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
Power Supply
Power supply with minimum current capability of xx A for system startup is recommended.
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| Scroll Title |
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| anchor | TableFigure_PWR_PCPD |
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| title | Power ConsumptionDistribution |
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tablelayout |
| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Power Input Pin | Typical Current |
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| VIN | TBD* |
* TBD - To Be Determined
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| ignore |
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| draw.io Diagram |
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| border | false |
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| |
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| diagramName | TEM0005_PWR_PD |
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| simpleViewer | false |
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| width | 639 |
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| links | auto |
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| tbstyle | hidden |
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| diagramDisplayName | |
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| lbox | true |
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| diagramWidth | 640 |
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| revision | 5 |
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| Scroll Only |
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 Image Added
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Power-On Sequence
| Scroll Title |
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| anchor | Figure_PWR_PDPS |
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| title | Power DistributionSequency |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| |
|---|
| diagramName | TEM0005_PWR_PDPS |
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| simpleViewer | false |
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| width | 639 |
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| links | auto |
|---|
| tbstyle | hidden |
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| diagramDisplayName | |
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| lbox | true |
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| diagramWidth | 641 |
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| revision | 3 |
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| Scroll Only |
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Image Removed |
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 Image Added
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Voltage Monitor Circuit
The TEM0005 is equipped with a voltage monitoring IC, U8. Reset Logic Output (nRST) asserts low when any of the V1, V2, or ADJ inputs are below their reset thresholds.
| Scroll Title |
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| anchor | Figure_PWR_PSVMC |
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| title | Power SequencyVoltage Monitor Circuit |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| |
|---|
| diagramName | TEM0005_PWR_PSVMC |
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| simpleViewer | false |
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| width | 639 |
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| links | auto |
|---|
| tbstyle | hidden |
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| diagramDisplayName | |
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| lbox | true |
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| diagramWidth | 641642 |
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| revision | 14 |
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| Scroll Only |
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Image Removed |
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 Image Added
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Power Rails
| Scroll Title |
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| anchor | FigureTable_PWR_VMC |
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| title | Voltage Monitor Circuit |
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| | Scroll Ignore |
|---|
Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
| Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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| PR | | title | Module power rails. |
|---|
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| Scroll Table Layout |
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| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Power Rail Name | B2B Connector J1 Pin | Direction | Notes |
|---|
| 3.3V | 1, 2, 3, 4 | Input |
| | VDDI6 | 22 | Input |
|
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Bank Voltages
| Scroll Title |
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| anchor | Table_PWR_PRBV |
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| title | Module power railsZynq SoC bank voltages. |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
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| cellHighlighting | true |
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|
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| Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes |
|---|
Bank Voltages
| Schematic Name | | Notes |
|---|
| Bank0 | 1.5V | 1.5V |
| | Bank1 | 3.3V | 3.3V |
| | Bank2 | 3.3V | 3.3V |
| | Bank3 | 3.3V | 3.3V |
| | Bank4 | 3.3V | 3.3V |
| | Bank5 | 3.3V | 3.3V |
| | Bank6 | VDDI6 | max. 2.5V | supplied by carrier | | Bank7 | 3.3V | 3.3V |
|
| Scroll Title |
|---|
| anchor | Table_PWR_BV |
|---|
| title | Zynq SoC bank voltages. |
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|
| Scroll Table Layout |
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|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
style | widths | | sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
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Board to Board Connectors
| Page properties |
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|
- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
| Include Page |
|---|
| 6 x 6 SoM LSHM B2B Connectors |
|---|
| PD:6 x 6 SoM LSHM B2B ConnectorsPD:6 x 6 SoM LSHM |
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|
|
| Include Page |
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| DRAFT:3.1 x 5.6 SoM ST5/SS5 B2B Connectors |
|---|
| DRAFT:3.1 x 5.6 SoM ST5/SS5 B2B Connectors |
|---|
|
Technical Specifications
Absolute Maximum Ratings
| Scroll Title |
|---|
| anchor | Table_TS_AMR |
|---|
| title | PS absolute maximum ratings |
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|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
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| cellHighlighting | true |
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|
| Symbols | Description | Min | Max | Unit |
|---|
| VIN | Input Supply Voltage | -0.3 | 3.63 | V | V | V | V | | STG_T | Storage Temperature | -45 | 125 | °C | V | V | V | V |
|
Recommended Operating Conditions
...
| Scroll Title |
|---|
| anchor | Table_TS_ROC |
|---|
| title | Recommended operating conditions. |
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|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Parameter | Min | Max | Units | Reference Document | | Max | Units | Reference Document |
|---|
| VIN | 3.15 | 3.45 | V | See the carrier datasheets. | | OPT_T | 0 /-40 | 85 | °C | See Microsemi Smartfusion2 datasheet. Depends on assembly version | V | See ???? datasheets. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | °C | See Xilinx ???? datasheet. | °C | See Xilinx ???? datasheet. |
|
Physical Dimensions
Module size: ?? 56 mm × ?? 31 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ? 4 mm.
PCB thickness: ?? 1.6 mm.
| Page properties |
|---|
|
In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM. For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below: https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF
|
...
| Scroll Title |
|---|
| anchor | Figure_TS_PD |
|---|
| title | Physical Dimension |
|---|
|
| Scroll Ignore |
|---|
| draw.io Diagram |
|---|
| border | false |
|---|
| |
|---|
| diagramName | TEM0005_TS_PD |
|---|
| simpleViewer | false |
|---|
| width | 639 |
|---|
| links | auto |
|---|
| tbstyle | hidden |
|---|
| diagramDisplayName | |
|---|
| lbox | true |
|---|
| diagramWidth | 641 |
|---|
| revision | 13 |
|---|
|
|
| Scroll Only |
|---|
| scroll-pdf | true |
|---|
| scroll-office | true |
|---|
| scroll-chm | true |
|---|
| scroll-docbook | true |
|---|
| scroll-eclipsehelp | true |
|---|
| scroll-epub | true |
|---|
| scroll-html | true |
|---|
| 
|
|
...
| Scroll Title |
|---|
| anchor | Table_RH_HRH |
|---|
| title | Hardware Revision History |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Date | Revision | Changes | Documentation Link |
|---|
| 2019-10-01 | REV01 | | REV01 | | 2020-05-20 | REV02 | - Support M2S050 ->added R29,R30, C24..C26,C31
- Added resistor R32
- Full upd LIB
| REV02 |
|
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
| Scroll Title |
|---|
| anchor | Figure_RV_HRN |
|---|
| title | Board hardware revision number. |
|---|
|
| Scroll Ignore |
|---|
| draw.io Diagram |
|---|
| border | false |
|---|
| |
|---|
| diagramName | TEM0005_RV_HRN |
|---|
| simpleViewer | false |
|---|
| width | 200 |
|---|
| links | auto |
|---|
| tbstyle | hidden |
|---|
| diagramDisplayName | |
|---|
| lbox | true |
|---|
| diagramWidth | 641175 |
|---|
| revision | 56 |
|---|
|
|
| Scroll Only |
|---|
 Image Removed Image Added
|
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Document Change History
...
| Scroll Title |
|---|
| anchor | Table_RH_DCH |
|---|
| title | Document change history. |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Date | Revision | Contributor | Description |
|---|
| Page info |
|---|
| infoType | Modified date |
|---|
| dateFormat | yyyy-MM-dd |
|---|
| type | Flat |
|---|
|
| | Page info |
|---|
| infoType | Current version |
|---|
| prefix | v. |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
|
| | Page info |
|---|
| infoType | Modified by |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
|
| | -- | all | | Page info |
|---|
| infoType | Modified users |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
|
| |
|
...