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Table of Contents
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The Carrier Board provides soldering-pads for VG96 connectors as place-holders to get access to the PL-IO-banks and other functional units of the mounted SoM.
Additional assembly options are available for cost or performance optimization upon request.
Figure 1: TEB0729-02 03 block diagram.
Figure 2: TEB0729-02 03 main components (picture shows PCB REV02).
Storage device name | Content | Notes |
---|---|---|
Configuration EEPROM, U1 | Empty | Not programmed |
Configuration EEPROM, U2 | Empty | Not programmed |
Table 1: Initial delivery state of programmable devices on the module.
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The TEB0729 Carrier Board's Board-to-Board Connectors (B2B) have the same pin-assignment as the mounted Zynq SoM due to its hermaphroditic structure. By this connectors, the MIO- and PL-IO-bank's pins and further interfaces of the Zynq SoM can be accessed. A large quantity of these I/O's are also usable as as LVDS-pairs. The connectors provide also VCCIO voltages to operate the I/O's properly.
Following table gives a summary of the available I/O's, interfaces and LVDS-pairs of the B2B connectors JB1 and JB2:
VG96 B2B Connector Designator | Interfaces | Count of IO's | Count of LVDS-pairs | Available VCCIO's | Interfaces | Notes |
---|---|---|---|---|---|---|
JB1 | 72 | 48 | 1.8V, 2.5V | User IO | 24 single ended | - |
48 single ended or 24 differential- | - | |||||
JB2 | User IO | 54 single ended | - | |||
10 single ended or 5 differential | - | |||||
I²C | 2 | - | ||||
SD IO | 7 | - | ||||
UART | 2 | - | ||||
USB2.0 | 6 | - | 64 | 5 | VCCIO_13, VCCIO_33 3.3V | I²C, SD IO, UART, USB2.0, |
2x 10/100-BaseT Ethernet, | 12 | - | ||||
GbE MDI and SGMII, | 14 | - | ||||
JTAG The 5 LVDS-pairs on connector JB2 have The I²C, SD IO and the UART interface pins are connected |
Table 2: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors.
4 | - |
Table 2: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors.
The TEB0729 Carrier Board has soldering pads provides as place-holders to mount VG96 connectors J8 and J9 to get access the PL-IO-bank's pins and further interfaces of the Zynq SoM. With mounted VG96 connectors, SoM's IO's are available to the user, a large quantity of these I/O's are also usable as LVDS-pairs.
On the VG96 connector J9 are signals assigned to control the SoM and the interfaces of the SoM's Zynq chip device and of its on-module peripherals:
Following table gives a summary of the pin-assignment, available interfaces and functional IO's of the VG96 connectors J8 and J9:
VG96 Connector | Control Signals and Interfaces | Count of IO's | Count of LVDS-pairs | Interfaces | SoM Control Signals | Notes |
---|---|---|---|---|---|---|
J8 | 72 | 48 | - | - | - | |
Notes | ||||||
J8 | User IO | 24 single ended | - | |||
48 single ended or 24 differential | - | |||||
J9 | User IO | 54 single ended | - | |||
10 single ended or 5 differential | - | J9 | 64 | 5 | I²C||
'NRST_IN' , (pin J9-A29 | Drive to ground (Push Button S1, JB3-11 (G) on XMOD header) to reset the SoM. 1) | 'NRST_OUT', ), 'RST_STATUS' (pin J9-B30Incoming reset signal from SoM's watchdog (implemented on SoM's SC CPLD). 1)) | 2 | These pins are dedicated to the specific Reset-functionality of the TE0729 SoM. | ||
'BOARD_STAT' , (pin J9-B32) | 1 | -Frequently flipping signal indicating running SoM. Routed also to XMOD Header, pin JB3-9 (E). | ||||
'BOOT_MODE1' , (pin J9-C31 | Bootmode pin 1, use in conjunction with Bootmode pin 2. | ), 'BOOT_MODE2' , (pin J9-C32)Bootmode pin 2, use in conjunction with Bootmode pin 1. | 2 | Binary bootmode code of SoM, also connected to DIP S2 | ||
I²C | 2 | I²C1 interface of module | ||||
GbE SGMII | 4 | SGMII interface of on-module GbE PHY |
Table 3: General overview of PL I/O signals, SoM's interfaces and control signals connected to the VG96 connectors. 1) Use TE0729 SC CPLD firmware 'SC729_rev02org.jed' for correct functionality with HW modification.
JTAG access to the mounted SoM is provided through B2B connector JB2 and is also routed to the XMOD header JB3. With the TE0790 XMOD USB2.0 to JTAG adapter, the Zynq chip device on the mounted SoM can be programed via USB2.0 interface.
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Table 4: JTAG interface signals.
UART interface is available on B2B connector JB2. With the TE0790 XMOD USB2.0 adapter, the UART signals can be converted to USB2.0 interface signals:
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Table 5: UART interface signals.
Two I²C interfaces are provided on B2B connector JB2. I²C0 interface is connected to the Configuration EEPROMs U1 and U2 and is dedicated to these on-board peripherals. Interface I²C1 is routed to the VG96 connector J9 and is available to the user for general purposes:
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Table 6: I²C interface signals.
The SD IO interface of the SoM's Zynq chip device (MIO-bank) is routed to the on-board MicroSD Card socket J1. By this interface, the Zynq chip device can be booted from an inserted MicroSD Card:
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Table 7: SD IO interface signals.
The TEB0729 Carrier Board is equipped with a Micro USB2.0 B (receptacle) socket J11 with board-revision TEB0729-0203B, USB2.0 Type A socket is fitted on board-revision TEB0729-0203A.
The differential data signals of the USB2.0 socket are routed to the B2B connector JB2, where they can be accessed by the USB2.0 transceiver of the mounted SoM. The USB2.0 connector can be used for Device mode, OTG Mode or Host Modes. For USB Host mode, the Carrier Board is additionally equipped with a power distribution switch U3 to provide the USB2.0 interface with the USB supply voltage USB-VBUS with nominal value of 5V. OTG mode is not available with USB2.0 Type A socket.
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Table 8: USB2.0 interface signals and connections.
The TEB0729 Carrier Board is fitted with one RJ-45 Gigabit Ethernet Magnetic jack J3. The MegJack has two integrated LEDs (both green), its signals are routed as MDI (Media Dependent Interface) to the B2B connector JB2, where they can be accessed by the GbE PHY transceiver of the mounted SoM:
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Table 10: GbE SGMII signals and connections.
The TEB0729 Carrier Board is also fitted with two additional RJ-45 MegJacks providing 10/100-BaseT Ethernet interfaces. This interfaces are routed to the B2B connector JB2
10/100-BaseT PHY Signal Schematic Name | B2B | Connected to | Notes | ||||
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ETH1_RX_P | JB2-26 | J4-3 | - | ||||
ETH1_RX_N | JB2-28 | J4-6 | - | ||||
ETH1_TX_P | JB2-20 | J4-1 | - | ||||
ETH1_TX_N | JB2-22 | J4-2 | - | ETH1_CTREF | JB2-30 | J4-4, J4-5 | Centre Tap Reference point |
ETH1_LED0 | JB2-34 | Yellow MegJack J4 LED | - | ||||
ETH1_LED1 | JB2-32 | Green MegJack J4 LED | - | ||||
ETH2_RX_P | JB2-8 | J5-3 | - | ||||
ETH2_RX_N | JB2-10 | J5-6 | - | ||||
ETH2_TX_P | JB2-2 | J5-1 | - | ||||
ETH2_TX_N | JB2-4 | J5-2- | ETH2_CTREF | JB2-18 | J5-4, J5-5 | Centre Tap Reference point | |
ETH2_LED0 | JB2-16 | Yellow MegJack J5 LED | - | ||||
ETH2_LED1 | JB2-14 | Green MegJack J5 LED | - |
Table 11: 10/100-BaseT Ethernet interfaces signals and connections.
The JTAG interface of the mounted SoM can be accessed via header JB3, which has a 'XMOD FTDI JTAG Adapter'-compatible pin-assignment. So in use with the XMOD-FT2232H adapter-board TE0790 the mounted SoM can be programmed via USB interface. The TE0790 board provides also an UART interface to the Zynq SoM which can be accessed by the USB2.0 interface of the adapter-board while the signals between these serial interfaces will be converted. The adapter-board offers also two GPIO's, one with an indication LED (pin JB3-9 (E)) and another one with a low-active push button (pin JB3-11 (G)).
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JB3 pin | Signal Schematic Net Name | B2B | Note |
---|---|---|---|
C (pin 4) | TCK | JB2-119 | - |
D (pin 8) | TDO | JB2-117 | - |
F (pin 10) | TDI | JB2-115 | - |
H (pin 12) | TMS | JB2-113 | - |
A (pin 3) | USART0_TX | JB2-96 | - |
B (pin 7) | USART0_RX | JB2-94 | - |
E (pin 9) | BOARD_STAT | JB2-112 | also connected to VG96 connector pin J9-B32 |
G (pin 11) 2) | NRST_IN | JB2-89 | also connected to VG96 connector pin J9-A29 |
Table 12: XMOD header signals and connections. 2) Pin connected to push button S1 on XMOD FTDI JTAG Adapter
When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO will be sourced by the Carrier Board. Set the DIP-switch with the setting:
XMOD DIP-switches | Position |
---|---|
Switch 1 | ON |
Switch 2 | OFF |
Switch 3 | OFF |
Switch 4 | ON |
Table 13: XMOD adapter board DIP-switch positions for voltage configuration.
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Use Xilinx compatible TE0790 adapter board (designation TE0790-xx with out 'L') to program the Zynq device. The TE0790 adapter board's CPLD have to be configured with the Standard variant of the firmware. Refer to the TE0790 Resources Site for further information and firmware download. |
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The TEB0729 Carrier Board is equipped with two Configuration EEPROMs U1 and U2 from Microchip.
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The Configuration EEPROMs are connected to the I²C0 interface of the Zynq's MIO-bank via B2B connector JB2.
Table below describes DIP-switch S2 settings for configuration of the mounted SoM:
DIP-switches S2 | Signal Schematic Net Name | Function | Note |
---|---|---|---|
S2-1 | JTAGSEL | Select Zynq chip device or SC CPLD programming of mounted SoM: OFF: Zynq chip programming.device in JTAG chain | Refer also to the TE0729 SC CPLD documentation for detailed information about JTAG update. |
S2-2 | BOOT_MODE1 | Select first bit of boot mode code | Refer to TE0729 TRM and SC CPLD documentation for detailed information about boot modes. |
S2-3 | BOOT_MODE2 | Select second bit boot mode code | |
S2-4 | x | x | not used |
Table 1314: DIP-Switch S2 SoM configuration settings.
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Boot Mode | S2-2 | S2-3 |
---|---|---|
JTAG | ON | ON |
SD | OFF | OFF |
QSPI | ON | OFF |
Table 15: Boot Modes configuration via DIP-switch S2 with default TE0729 CPLD Firmware
The Carrier Board VCCIO for the PL IO-banks of the mounted SoM are selectable by the jumpers J6 and J7.
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VCCIO vs. Voltage Levels | VCCIO_13 | VCCIO_33 | Note |
---|---|---|---|
1.8V | J7:pins 1-2 | J6: pins 1-2 | - |
2.5V | J7: pins 3-4 | J6: pins 3-4 | - |
3.3V | J7: pins 5-6 | J6: pins 5-6 | - |
Table 1416: VCCIO jumper settings.
The buffer voltage of the SoM's RTC can be supplied through the header J2. Refer to the SoM's TRM for recommended voltage range and absolute maximum ratings.
The Carrier Board's push button S1 is connected to the 'NRST_IN' signal, the function of the button is to trigger a reset of the mounted SoM by driving the reset-signal 'NRST_IN' to ground.
LED | Color | Connected to | Description and Notes |
---|---|---|---|
D1 | Red | 'MIO9', pin JB2- 88 | user LED |
Table 1517: On-board LEDs.
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The maximum power consumption of the Carrier Board depends mainly on the mounted SoM's FPGA design running on the Zynq chipdevice.
Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.
Power Input | Typical Current |
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5VIN | TBD* |
Table 1618: Typical power consumption.
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To avoid any damage to the module, check for stabilized on-board voltages and VCCIO's before put voltages on PL I/O-banks and interfaces. All I/Os should be tri-stated during power-on sequence. |
The Carrier Board needs one single power supply voltage with a nominal value of 5V. Following diagram shows the distribution of the input voltage '5VIN' to the on-board components on the mounted SoM:
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Figure 3: Board power distribution diagram.
The voltage direction of the power rails is directed at on-board connectors' view:
Module Connector (Module Connector (B2B) Designator | VCC / VCCIO | Direction | Pins | Notes |
---|---|---|---|---|
JB1 | VIN33 | Out | Pin 1, 2, 3, 4, 5, 6 | 3.3V module supply voltage |
VCCIO_13 | Out | Pin 101, 102 | PL IO-bank VCCIO | |
VCCIO_33 | Out | Pin 29, 30 | PL IO-bank VCCIO | |
3.3V | In | Pin 65, 66 | voltage output from module | |
JB2 | 1.8V | In | Pin 49 | voltage output from module |
2.5V | In | Pin 13 | voltage output from module | |
USB-VBUS | Out | Pin 107 | USB Host supply voltage | |
VBAT_IN | Out | Pin 118 | RTC buffer voltage |
Table 1719: Power pin description of B2B Module Connector.
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Jumper / Header Designator | VCC / VCCIO | Direction | Pins | Notes |
---|---|---|---|---|
J6 | VCCIO_33 | OutIn | Pin 2, 4, 6 | - |
1.8V | InOut | 5 | - | |
2.5V | InOut | 3 | - | |
3.3V | InOut | 1 | - | |
J7 | VCCIO_13 | OutIn | Pin 2, 4, 6 | - |
1.8V | InOut | 5 | - | |
2.5V | InOUt | 3 | - | |
3.3V | InOut | 1 | - |
Table 1820: Power Pin description of VCCIO selection jumper pin header.
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Main Power Jack and Pins Designator | VCC / VCCIO | Direction | Pins | Notes |
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J12 | 5VIN | In | -1 | - |
J9 | 5VIN | In / Out | Pin A1, A2 | also usable as '5VIN' power supply to the Carrier Board as alternative to J12 |
J2 | VBAT_IN | In | Pin 1 | Attention: Pin 2 connected to ground. VBAT_IN voltage on this pin cause short-circuit. |
Table 1921: Main Power jack and pins description.
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Peripheral Socket Designator | VCC / VCCIO | Direction | Pins | Notes |
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J10 / J11 | USB-VBUS | In / Out | Pin 1 | Direction depends on USB2.0 Type A socket / Micro USB2.0 B socketmode |
J1 | VIN33 | Out | Pin 4 | MikroSD Card socket VDD |
Table 2022: Power pin description of peripheral connector.
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XMOD Header Designator | VCC / VCCIO | Direction | Pins | Notes |
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JB3 | 3.3V | - | Pin 5 | not connected |
VIO | Out | Pin 6 | connected to VIN33 |
Table 21: Power pin description of XMOD/JTAG Connector.
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Notes | ||||
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JB3 | 3.3V | - | 5 | not connected |
VIO | Out | 6 | connected to VIN33 |
Table 23: Power pin description of XMOD/JTAG Connector.
The TE0729 module has two 120-pin double-row REF-189019-02 connectors on the bottom side which are compatible with Samtec BSE-060-01-L-D-A connectors. Mating connectors on the baseboard are REF-189019-01, which are compatible with Samtec BTE-060-01-L-D-A connectors.
Order | REF Number | Samtec Number | Type | Mated Height | Data sheet | Comment |
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- | REF-189019-02 | BTE-060-01-L-D-A-K-TR | Module connector | 5 mm | http://suddendocs.samtec.com/catalog_english/bte.pdf | Standard connector used on module |
26663 | REF-189019-01 | BSE-060-01-L-D-A-TR | Baseboard connector | 5 mm | http://suddendocs.samtec.com/catalog_english/bse.pdf | Standard connector used on board |
Table 24: B2B Connectors.
Connector Specifications | Value |
---|---|
Insulator material | Liquid crystal polymer |
Stacking height | 5 mm |
Contact material | Phosphor-bronze |
Plating | Au or Sn over 50 μ" (1.27 μm) Ni |
Current rating | 2 A per pin (1 pin powered per row) |
Operating temperature range | -55 °C to +125 °C |
Voltage rating | 225 VAC with 5 mm stack height |
Max cycles | 100 |
RoHS compliant | Yes |
Table 25: B2B Connector specifications.
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Module Variant | Operating Temperature | USB Socket | Temperature Range |
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TEB0729-0203-A | -40°C to +125°C | USB2.0 Type A socket fitted | Industrial |
TEB0729-0203-B | -40°C to +125°C | Micro USB2.0 B socket fitted | Industrial |
Table 2226: Module Board variants.
Parameter | Min | Max | Units | Reference Document |
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5VIN supply voltage | -0.3 | 7 | V | MP5010A, EN6347QI data sheet |
Storage temperature | -65 | 150 | °C | - |
Table 2327: Module absolute maximum ratings.
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
5VIN supply voltage | 4.75 | 5.25 | V | USB2.0 specification concerning 'VBUS' voltage |
Operating temperature | -40 | 125 | °C | - |
Table 2428: Module recommended operating conditions.
Industrial grade: -40°C to +85°C.
The TEB0729 Carrier Board itself is capable to be operated at industrial grade temperature range.
Please check the operating temperature range of the mounted SoM, which determine the relevant operating temperature range of the overall system.
Board size: 107.70 mm × 100 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm.
PCB thickness: ca. 1.65mm.
Highest part on the PCB is the Ethernet RJ-45 jack, which has an approximately 17 mm overall height. Please download the step model for exact numbers.
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Figure 4: Board physical dimensions drawing.
Date | Revision | Notes | PCN | Documentation Link | |||
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- | 01 | First Production Release | - | TEB0729-01 | |||
Documentation Link | |||||||
- | 01 |
| - | TEB0729-01 | |||
- | 02 |
| - | TEB0729-02 | |||
- | 03 |
| - | 02 | Second Production Release | - | TEB0729-0203 |
Table 2529: Module hardware revision history.
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Figure 5: Module hardware revision number.
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Date | Revision | Contributors | Description | ||||||||
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| Ali Naseri |
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2017-10-27 | v.14 | Ali Naseri |
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Table 2630: Document change history.
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