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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware |
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Table of contents
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Overview
Firmware for PCB-Master CPLD with designator U5: LCMX02-1200HC.
Feature Summary
- Power Management
- Reset Management
- LED Control
- FAN Control
- I2C MUX
Firmware Revision and supported PCB Revision
See Document Change History
Product Specification
Port Description
Name / opt. VHD Name | Direction | Pin | Description | |
---|---|---|---|---|
200MHZCLK_EN | out | 30 | ||
BUTTON | in | 77 | Reset Button | |
CPLD_JTAG_TCK | 91 | not accessible as IO | ||
CPLD_JTAG_TDI | 94 | not accessible as IO | ||
CPLD_JTAG_TDO | 95 | not accessible as IO | ||
CPLD_JTAG_TMS | 90 | not accessible as IO | ||
DDR3_SCL | inout | 43/ currently_not_used | I2C connected to FPGA | |
DDR3_SDA | inout | 42/ currently_not_used | I2C connected to FPGA | |
DONE | in | 18 | FPGA Done | |
EN_1V8 | out | 58 | Power Enable | |
EN_3V3FMC | out | 60 | Power Enable | |
EN_FMC_VADJ | out | 51 | Power Enable | |
F1PWM | out | 98 | FAN | |
F1SENSE | in | 99 | FAN / currently_not_used | |
FEX_DIR | 19 | / currently_not_used | ||
FEX0 | out | 12/ currently_not_used | PERST from PCIe slot | |
FEX1 | 15 | / currently_not_used | ||
FEX10 | 4 | / currently_not_used | ||
FEX11 | in | 10/ | currently_not_usedUser LED | |
FEX2 | 13 | / currently_not_used | ||
FEX3 | 9 | / currently_not_used | ||
FEX4 | 3 | / currently_not_used | ||
FEX5 | 7 | / currently_not_used | ||
FEX6 | 24 | / currently_not_used | ||
FEX7 | 17 | / currently_not_used | ||
FEX8 | 21 | / currently_not_used | ||
FEX9 | 25 | / currently_not_used | ||
FMC_PG_C2M | 69 | / currently_not_used | ||
FMC_PG_M2C | 68 | / currently_not_used | ||
FMC_PRSNT_M2C_L | 70 | / currently_not_used | ||
FMC_SCL | 49/ currently_not_used | I2C connected to FPGA | ||
FMC_SDA | 48/ currently_not_used | I2C connected to FPGA | ||
FMC_TCK | 27 | / currently_not_used | ||
FMC_TDI | 31 | / currently_not_used | ||
FMC_TDO | 32 | / currently_not_used | ||
FMC_TMS | 28 | / currently_not_used | ||
FMC_TRST | 36 | / currently_not_used | ||
FPGA_IIC_OE | 14/ | currently_not_usedI2C FPGA | ||
FPGA_IIC_SCL | 1/ | currently_not_usedI2C FPGA | ||
FPGA_IIC_SDA | 16/ | currently_not_usedI2C FPGA | ||
LED1 | out | 76 | Status LED D1 (green) | |
LTM_1V_IO0 | 86 | Power Good | ||
LTM_1V_IO1 | 88 | Power Good | ||
LTM_1V5_4V_IO0 | 85 | Power Good | ||
LTM_1V5_4V_IO1 | 83 | Power Good | ||
LTM_1V5_RUN | 74 | / currently_not_used | ||
LTM_4V_RUN | 75 | / currently_not_used | ||
LTM_SCL | 67/ currently_not_used | I2C connected to FPGA | ||
LTM_SDA | 66/ currently_not_used | I2C connected to FPGA | ||
LTM1_ALERT | 65 | / currently_not_used | ||
LTM2_ALERT | 64 | / currently_not_used | ||
PCIE_RSTB | outin | 37 | PERST from PCIe Resetcard edge connector | |
PG_1V8 | in | 59 | Power Good | |
PG_3V3 | in | 61 | Power Good | |
PG_FMC_VADJ | in | 52 | Power Good | |
PLL_SCL | inout | 2/ | currently_not_usedI2C SI5338 | |
PLL_SDA | inout | 8/ | currently_not_usedI2C SI5338 | |
PROGRAM_B | out | 20 | FPGA PROG_B | |
VID0_FMC_VADJ | out | 53 | FMC EN5365QI power selection pin | |
VID1_FMC_VADJ | out | 54 | FMC EN5365QI power selection pin | |
VID2_FMC_VADJ | out | 57 | FMC EN5365QI power selection pin |
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Functional Description
JTAG
CPLD JTAG is always enabled.
Power
Power sequence on will be executed over 4 States:
- State 1 IDLE: Wait until LTM_1V_IO0 (1V), LTM_1V_IO1 (1V) and LTM_1V5_4V_IO1 (4V) is available.
- State 2 PS1: Enables 1V8, 3V3FMC and VADJ. Wait until PG_1V8 (1.8V), PG_3V3 (3.3V) and PG_FMC_VADJ (FMC VADJ) is available.
- State 3 PS2: Wait until LTM_1V5_4V_IO0 (1.5V) is available
- State 4 RDY: All power on
Sstate State machine restart power sequencing, if on of the power good signal are lost.
FMC VADJ is set to 1.8V.
Reset
PCIE_RSTB is low until power up sequencing is ready.
PROGRAM_B is controlled by push button after power up sequencing is ready.
CLK
200MHz CLK is enabled after power up.
Si55338 configuration is not implemented.
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I2C
Connect SI5338, LTM and FMC, SODIMM I2C and internal FAN Control to FPGA I2C Bus.
FAN1
I2C Baseaddress: 0x74 (changeable with Firmware update). I2C with 8Bit Register Address with 8Bit Data. I2C CLK currently 20 MHz supported.
Write Access:
Register Address | Name | Description |
---|---|---|
0 | FAN CTRL | Enable FAN1 (Bit7) |
1 | FAN1 PWM | FAN1 PWM (0%-100%, Default 80%) |
Read Access:
Register Address | Name | Description |
---|---|---|
0 | FAN CTRL | FAN Control register |
1 | FAN1 RPS | FAN1 Revolutions per second |
Button
Button is debounced and controls PROG_B signal from FPGA.
LED
LED is used as Status LED for power management and programming. Status depends on blink sequence.
Status | Blink sequence | Comment | ||
---|---|---|---|---|
Error - Power IDLE state | ******** | ~5,8 Hz,Reset or Main Power Problem | ||
Error - Power PS1 state | *****ooo | ~0,7 Hz, duty cycle 5/8Periphery Power Problem (1.8V, 3.3V, FMC VADJ) | ||
Error - Power PS2 state | ****oooo~0,7 Hz, duty cycle 4/8 | DDR Bank Power Problem (1.5V) | ||
Power Ready, FPGA not programmed | ***ooooo | ~0,7 Hz, duty cycle 3/8 | ||
-- | **oooooo | ~0,7 Hz, duty cycle 2/8, currently not used | ||
-- | *ooooooo | ~0,7 Hz, duty cycle 1/8, currently not used | ||
User Mode | user defined | Power Power Ready, FPGa programmed | constant on |
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FPGA programmed, LED is accessible over FEX11 |
Appx. A: Change History and Legal Notices
Revision Changes
CPLD REV01 to REV02
- BUGFIX: PCIe Reset
- USER LED accessible
- I2C for SI5338, LTM, FMC, SODIMM
- Add FAN Control over I2C
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | |||||||||||||||||||||||||
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| current-version |
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Page info modified-user modified-user
- REV02 finished
Firmware Releases(2017-11-28)
- REV01 finished
v.1
Page info created-user created-user
- Initial release
Page info modified-users modified-users
Appx. A: Legal Notices
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