Page History

Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"

Notes :

• short description of the design

• Short Link of "Scroll only" macro:

  • Use short link the Wiki Resource page, for example: http://trenz.org/te0720-info

  • List of available short links: https://wiki.trenz-electronic.de/display/CONTI/Redirects

Notes :

• Add basic key futures, which can be tested with the design

• Vitis/Vivado 20202022.2
• PetaLinux
• SD
• 2x ETH
• CAN
• USB
• I2C
• RTC
• FMeter
• PCIe
• LED
• Modified FSBL for SI5395 programming
• Special FSBL for QSPI programming

Notes :

• add every update file on the download
• add design changes on description

• add known Design issues and general notes for the current revision
• do not delete known issue, add fixed version time stamp if issue fixed

Notes :

• list of software which was used to generate the design

Notes :

• list of hardware which was used to generate the design
• mark the module and carrier board, which was used tested with an ^*

^*used as reference

^*used as reference

Notes :

• content of the zip file

Notes :

• prebuilt files
• Template Table:

  • 
    

    Scroll Title
    anchor Table_PF title-alignment center title Prebuilt files
    Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true File File-Extension Description BIF-File *.bif File with description to generate Bin-File BIN-File *.bin Flash Configuration File with Boot-Image (Zynq-FPGAs) BIT-File *.bit FPGA (PL Part) Configuration File Boot SourceScript-File *.scr Distro Boot Script file DebugProbes-File *.ltx Definition File for Vivado/Vivado Labtools Debugging Interface Debian SD-Image *.img Debian Image for SD-Card Diverse Reports --- Report files in different formats Device Tree *.dts Device tree (2 possible, one for u-boot and one for linux) Hardware-Platform-Description-File *.xsa Exported Vivado hardware description file for Vitis and PetaLinux LabTools Project-File *.lpr Vivado Labtools Project File MCS-File *.mcs Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) MMI-File *.mmi File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) OS-Image *.ub Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) Software-Application-File *.elf Software Application for Zynq or MicroBlaze Processor Systems SREC-File *.srec Converted Software Application for MicroBlaze Processor Systems

    
    

• Important set new Vivado version link on every Design update of new vivado version!
• Set Link to download folder (Remove ../de/.. ../en/.. from url) for example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0712/Reference_Design/2018.2/test_board

• Basic Design Steps

• Add/ Remove project specific description

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

Note:

• Programming and Startup procedure

Check Module and Carrier TRMs for proper HW configuration before you try any designtry any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Note:

• Add picture of HW Manager

• add notes for the signal either groups or topics, for example:
  

  Control:

  • add controllable IOs with short notes..

  Monitoring:

  • add short notes for signals which will be monitored only
  • SI5338 CLKs:
    • Set radix from VIO signals to unsigned integer. Note: Frequency Counter is inaccurate and displayed unit is Hz
    • expected CLK Frequency...
      

Image RemovedImage Added

Note:

• Description of Block Design, Constrains... BD Pictures from Export...

Note:

• optional for Zynq / ZynqMP only

• add basic PS configuration

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

#   AB34	 MGT_128_CLK_P                                                   
#   AB35	 MGT_128_CLK_N                                                   
#    W32	 MGT_129_CLK_P                                                   
#    W33	 MGT_129_CLK_N                                                   
#    R32	 MGT_130_CLK_P                                                   
#    R33	 MGT_130_CLK_N                                                   
#    L32	 MGT_131_CLK_P                                                   
#    L33	 MGT_131_CLK_N                                                   
set_property PACKAGE_PIN AB34 [get_ports {CLK_IN_D_128_131_clk_p[0]}]
set_property PACKAGE_PIN W32 [get_ports {CLK_IN_D_128_131_clk_p[1]}]
set_property PACKAGE_PIN R32 [get_ports {CLK_IN_D_128_131_clk_p[2]}]
set_property PACKAGE_PIN L32 [get_ports {CLK_IN_D_128_131_clk_p[3]}]

#   AB11	 MGT_228_CLK_N                                                   
#   AB12	 MGT_228_CLK_P                                                   
#    Y11	 MGT_229_CLK_N                                                   
#    Y12	 MGT_229_CLK_P                                                   
#    V11	 MGT_230_CLK_N                                                   
#    V12	 MGT_230_CLK_P                                                   
#    T11	 MGT_231_CLK_N                                                   
#    T12	 MGT_231_CLK_P                                                   
set_property PACKAGE_PIN AB12 [get_ports {CLK_IN_D_228_231_clk_p[0]}]
set_property PACKAGE_PIN Y12 [get_ports {CLK_IN_D_228_231_clk_p[1]}]
set_property PACKAGE_PIN V12 [get_ports {CLK_IN_D_228_231_clk_p[2]}]
set_property PACKAGE_PIN T12 [get_ports {CLK_IN_D_228_231_clk_p[3]}]

#   AK11	 MGT_224_CLK_N                                                   
#   AK12	 MGT_224_CLK_P                                                   
#   AH11	 MGT_225_CLK_N                                                   
#   AH12	 MGT_225_CLK_P                                                   
#   AF11	 MGT_226_CLK_N                                                   
#   AF12	 MGT_226_CLK_P                                                   
#   AD11	 MGT_227_CLK_N                                                   
#   AD12	 MGT_227_CLK_P                                                   
set_property PACKAGE_PIN AK12 [get_ports {CLK_IN_D_224_227_clk_p[0]}]
set_property PACKAGE_PIN AH12 [get_ports {CLK_IN_D_224_227_clk_p[1]}]
set_property PACKAGE_PIN AF12 [get_ports {CLK_IN_D_224_227_clk_p[2]}]
set_property PACKAGE_PIN AD12 [get_ports {CLK_IN_D_224_227_clk_p[3]}]

#   B65 CLK
set_property PACKAGE_PIN AR24 [get_ports {CLK_IN_D_B65_clk_p[0]}]
set_property IOSTANDARD LVDS [get_ports {CLK_IN_D_B65_clk_p[0]}]


#get_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN D3                  } [get_ports {+3.3V_ETH_PHY_EN}]   #removed on REV02 --> use unused pullup for rev01
#set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN C1                  } [get_ports {+3.3V_M2_KeyE_EN}]   #removed on REV02 --> use unused pullup for rev01
#set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN G10                 } [get_ports {ssd1_perstn[0]}]
set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN B6                  } [get_ports {LED[0]}]
set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN B5                  } [get_ports {LED[1]}]
set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN A5                  } [get_ports {LED[2]}]
set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN A4                  } [get_ports {LED[3]}]
#set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN G13                 } [get_ports {M2M_SLEEP[0]}]  
#set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN F13 PULLUP TRUE     } [get_ports {ssd1_wake[0]}]  #removed on REV02 --> use unused pullup for rev01
#
#    B10	 FF10_MPRS                                                       
#    C10	 FF01_MPRS                                                       
#    C11	 FF00_MPRS                                                       
#    D11	 FF31_MPRS                                                       
#    D12	 FF30_MPRS                                                       
#    E10	 FF20_MPRS                                                       
#    E11	 FF11_MPRS                                                       
#    E12	 FF21_MPRS                                                       
#    J12	 FFA_SDA                                                         
#    J14	 FFA_SCL                                                         
#    K10	 FFD_MPRS                                                        
#    K11	 FFD_MSEL                                                        
#    K12	 FFC_MPRS                                                        
#    K14	 FFA_INTL                                                        
#    L10	 FFD_INTL                                                        
#    L12	 FFC_MSEL                                                        
#    L13	 FFA_MPRS                                                        
#    L14	 FFA_MSEL                                                        
#    M10	 FFD_SDA                                                         
#    M11	 FFB_SDA                                                         
#    M13	 FFB_SCL                                                         
#    N10	 FFD_SCL                                                         
#    N11	 FF_AB_RSTL                                                      
#    N12	 FF_CD_RSTL                                                      
#    N13	 FFB_MSEL                                                        
#    N14	 FFB_INTL                                                        
#    P12	 FFC_INTL                                                        
#    P13	 FFC_SCL                                                         
#    P14	 FFB_MPRS                                                        
#    R14	 FFC_SDA                                                         
#
#     E3	 PEX_FATAL_ERRORn      REV02 only                                          
#     E4	 PEX_GPIO3             REV02 only                                          
#     E5	 PEX_LANE_GOOD2n       REV02 only                                          
#     F4	 PEX_LANE_GOOD1n       REV02 only                                          
#     F5	 PEX_LANE_GOOD0n       REV02 only                                          
#
#     F6	 DSPLL1_RST_N                                                    
#     F7	 DSPLL0_RST_N                                                    
#
#    G11	 W_DISABLE1n         REV01 other name                                                      
#    G12	 W_DISABLE2n         REV01 other name                                            
#    G13   M2M_SLEEP           REV02 only
#
#    F10	 SSD1_CLKRQ          REV01 only                                            
#    F13	 SSD1_WAKE           REV01 only                                            
#    G10	 SSD1_PERSTn         REV01 only                                            
#    G13	 M2M_SLEEP           REV01 other nameSSD1_SLEEP                                                      
#


set_property -dict { IOSTANDARD LVCMOS18 PACKAGE_PIN AK23                } [get_ports {BUTTON[0]}]
set_property -dict { IOSTANDARD LVCMOS18 PACKAGE_PIN AL23                } [get_ports {BUTTON[1]}]
set_property -dict { IOSTANDARD LVCMOS18 PACKAGE_PIN AJ24                } [get_ports {BUTTON[2]}]
set_property -dict { IOSTANDARD LVCMOS18 PACKAGE_PIN AK24                } [get_ports {BUTTON[3]}]

set_property -dict { IOSTANDARD DIFF_SSTL12_DCI  PACKAGE_PIN G26          } [get_ports {diff_clock_rtl_clk_p}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN N24                } [get_ports {ddr4_act_n}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN J27                } [get_ports {ddr4_adr[0]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN J24                } [get_ports {ddr4_adr[1]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN F27                } [get_ports {ddr4_adr[2]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN E26                } [get_ports {ddr4_adr[3]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN M25                } [get_ports {ddr4_adr[4]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN D26                } [get_ports {ddr4_adr[5]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN K27                } [get_ports {ddr4_adr[6]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN E27                } [get_ports {ddr4_adr[7]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN K26                } [get_ports {ddr4_adr[8]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN H26                } [get_ports {ddr4_adr[9]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN L24                } [get_ports {ddr4_adr[10]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN F28                } [get_ports {ddr4_adr[11]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN J23                } [get_ports {ddr4_adr[12]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN J26                } [get_ports {ddr4_adr[13]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN L23                } [get_ports {ddr4_adr[14]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN K24                } [get_ports {ddr4_adr[15]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN H23                } [get_ports {ddr4_adr[16]}]

## /* dummy for ddr4-ram */
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN G25                } [get_ports {ddr4_adr17[0]}] 


set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN N26                } [get_ports {ddr4_ba[0]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN G23                } [get_ports {ddr4_ba[1]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN M23                } [get_ports {ddr4_bg[0]}]
#set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN P23                } [get_ports {ddr4_bg[1]}]   

## /* dummy for ddr4-ram */
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN P23                } [get_ports {ddr4_bg1[0]}]   

set_property -dict { IOSTANDARD DIFF_SSTL12_DCI PACKAGE_PIN F25      F25          } [get_ports {ddr4_ck_t[0]}]
set_property -dict { IOSTANDARD DIFF_SSTL12_DCI PACKAGE_PIN E25                } [get_ports {ddr4_ck_c[0]}]

set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN L25                } [get_ports {ddr4_cke[0]}]
set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN N23                } [get_ports {ddr4_cs_n[0]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN P18                } [get_ports {ddr4_dm_n[0]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN K19                } [get_ports {ddr4_dm_n[1]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN D19                } [get_ports {ddr4_dm_n[2]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN G22                } [get_ports {ddr4_dm_n[3]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN K29                } [get_ports {ddr4_dm_n[4]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN E29                } [get_ports {ddr4_dm_n[5]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN C36                } [get_ports {ddr4_dm_n[6]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN E32                } [get_ports {ddr4_dm_n[7]}]

set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN N19                } [get_ports {ddr4_dqs_c[0]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN J22                } [get_ports {ddr4_dqs_c[1]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN B21                } [get_ports {ddr4_dqs_c[2]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN E20                } [get_ports {ddr4_dqs_c[3]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN F30                } [get_ports {ddr4_dqs_c[4]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN A32                } [get_ports {ddr4_dqs_c[5]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN A40                } [get_ports {ddr4_dqs_c[6]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN C34                } [get_ports {ddr4_dqs_c[7]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN N20                } [get_ports {ddr4_dqs_t[0]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN K22                } [get_ports {ddr4_dqs_t[1]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN C21                } [get_ports {ddr4_dqs_t[2]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN F20                } [get_ports {ddr4_dqs_t[3]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN G30                } [get_ports {ddr4_dqs_t[4]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN B31                } [get_ports {ddr4_dqs_t[5]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN A39                } [get_ports {ddr4_dqs_t[6]}]
set_property -dict { IOSTANDARD DIFF_POD12_DCI PACKAGE_PIN D34                } [get_ports {ddr4_dqs_t[7]}]

set_property -dict { IOSTANDARD SSTL12_DCI PACKAGE_PIN H24                } [get_ports {ddr4_odt[0]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN N25                } [get_ports {ddr4_reset_n}]

set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN N21                } [get_ports {ddr4_dq[0]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN M18                } [get_ports {ddr4_dq[1]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN M21                } [get_ports {ddr4_dq[2]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN M20                } [get_ports {ddr4_dq[3]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN P21                } [get_ports {ddr4_dq[4]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN L18                } [get_ports {ddr4_dq[5]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN M22                } [get_ports {ddr4_dq[6]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN L19                } [get_ports {ddr4_dq[7]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN H19                } [get_ports {ddr4_dq[8]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN L20                } [get_ports {ddr4_dq[9]}]

set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN H20                } [get_ports {ddr4_dq[10]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN K21                } [get_ports {ddr4_dq[11]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN G20                } [get_ports {ddr4_dq[12]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN K20                } [get_ports {ddr4_dq[13]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN H21                } [get_ports {ddr4_dq[14]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN J21                } [get_ports {ddr4_dq[15]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B22                } [get_ports {ddr4_dq[16]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN C20                } [get_ports {ddr4_dq[17]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A22                } [get_ports {ddr4_dq[18]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A19                } [get_ports {ddr4_dq[19]}]

set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B23                } [get_ports {ddr4_dq[20]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B20                } [get_ports {ddr4_dq[21]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A23                } [get_ports {ddr4_dq[22]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A20                } [get_ports {ddr4_dq[23]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN F22                } [get_ports {ddr4_dq[24]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN E19                } [get_ports {ddr4_dq[25]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN E22                } [get_ports {ddr4_dq[26]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN D21                } [get_ports {ddr4_dq[27]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN F23                } [get_ports {ddr4_dq[28]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN F19                } [get_ports {ddr4_dq[29]}]

set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN D22                } [get_ports {ddr4_dq[30]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN E21                } [get_ports {ddr4_dq[31]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN F31                } [get_ports {ddr4_dq[32]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN J28                } [get_ports {ddr4_dq[33]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN J30                } [get_ports {ddr4_dq[34]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN H28                } [get_ports {ddr4_dq[35]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN F32                } [get_ports {ddr4_dq[36]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN G28                } [get_ports {ddr4_dq[37]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN H30                } [get_ports {ddr4_dq[38]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN F29                } [get_ports {ddr4_dq[39]}]

set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN E31                } [get_ports {ddr4_dq[40]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN C30                } [get_ports {ddr4_dq[41]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN C31                } [get_ports {ddr4_dq[42]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B30                } [get_ports {ddr4_dq[43]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN D31                } [get_ports {ddr4_dq[44]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN C29                } [get_ports {ddr4_dq[45]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A30                } [get_ports {ddr4_dq[46]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A29                } [get_ports {ddr4_dq[47]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN C42                } [get_ports {ddr4_dq[48]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B36                } [get_ports {ddr4_dq[49]}]

set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B40                } [get_ports {ddr4_dq[50]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B37                } [get_ports {ddr4_dq[51]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B42                } [get_ports {ddr4_dq[52]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A37                } [get_ports {ddr4_dq[53]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B41                } [get_ports {ddr4_dq[54]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A38                } [get_ports {ddr4_dq[55]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B35                } [get_ports {ddr4_dq[56]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B32                } [get_ports {ddr4_dq[57]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A33                } [get_ports {ddr4_dq[58]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN D33                } [get_ports {ddr4_dq[59]}]

set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A35                } [get_ports {ddr4_dq[60]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN A34                } [get_ports {ddr4_dq[61]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN C33                } [get_ports {ddr4_dq[62]}]
set_property -dict { IOSTANDARD POD12_DCI PACKAGE_PIN B33                } [get_ports {ddr4_dq[63]}]

set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN J9                  } [get_ports {IIC_0_scl_io}]
set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN H9                  } [get_ports {IIC_0_sda_io}]


#create_clock -name c0_sys_clk -period 4.998 [get_ports diff_clock_rtl_clk_p] 

• optional chapter separate

• sections for different apps

• optional chapter separate

• sections for linux

• Add "No changes." or "Activate: and add List"

/include/ "system-conf.dtsi"

/*-------------------------- QSPI -------------------------*/
&qspi {
    #address-cells = <1>;
    #size-cells 
};
 
 
/* I2C Bus on PL for CPLD I2C controller */
&axi_iic_0 {
        iexp@20 {       // GPIO in CPLD
            #gpio-cells = <2>= <0>;
    status = "okay";
    flash0: flash@0 {

        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;

    };
};


/*------------------ SD1 with level shifter ---------------*/
&sdhci1 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_sdhci1_default>;
    no-1-8-v;
  //compatible = "ti,pcf8574" disable-wp;
};
  
&pinctrl0 {
    status = "okay";
   reg = <0x20>; pinctrl_sdhci1_default: sdhci1-default {
            gpio-controller;mux {
            groups = "sdio1_0_grp";
       
     function =  }"sdio1";
};
 
 
/* I2C Bus on PS MIO */
&i2c1 {
 
};
  
        i2cswitch@75conf {
 /*  u35 */
        compatiblegroups = "nxp,pca9544sdio1_0_grp";
         #address-cells   slew-rate = <1>;
        #size-cells = <0>;
        reg io-standard = <0x70><1>;
 
        i2c@0 { /* DSPLL0*/ bias-disable;
        };
/*
            #address-cells = <1>;mux-cd {
                    #size-cells = <0>groups = "sdio1_cd_0_grp";
                    regfunction = <0>"sdio1_cd";
        };
  
      i2c@1 { /* DSPLL1*/conf-cd {
            groups = "sdio1_cd_0_grp";
      #address-cells = <1>;
    bias-high-impedance;
            bias-pull-up;
    #size-cells = <0>;
      slew-rate = <1>;
            regio-standard = <1>;
        };
  
      i2c@2 { /* J34*/mux-wp {
                    #address-cells = <1>groups = "sdio1_wp_0_grp";
            function = "sdio1_wp";
      #size-cells = <0>};
  
        conf-wp {
         reg   groups = <2>"sdio1_wp_0_grp";
        };
        i2c@3 { /* J34*/
bias-high-impedance;
            bias-pull-up;
            #addressslew-cellsrate = <1>;
            io-standard = <1>;
      #size-cells = <0>};
*/
          
    };
};
  
 
/*------------------------- ETH  reg = <3>;
   PHY -----------------------*/
  
  
&gem2 {
    status }= "okay";
    phy-handle = }<&ethernet_phy2>;
};
    
  
/* QSPI */
  
&qspi { nvmem-cells = <&eth2_addr>;
    #addressnvmem-cell-cellsnames = <1>"mac-address";

    mdio {
 #size-cells  = <0>;
     status = "okay"; ethernet_phy1: ethernet-phy@0 {
    flash0: flash@0 {
          //compatible = "jedecmarvell,spi-nor88e1510";
          reg = <0x0> <0>;
      };
  
      #address-cells = <1>;
ethernet_phy2: ethernet-phy@1 {
      
   #size-cells = <1>;
    };
};
 
  
/* SD1 with level shifter */

&sdhci1 {
 //compatible = "marvell,88e1510";
          pinctrl-namesreg = "default"<1>;
    pinctrl-0 = <&pinctrl_sdhci1_default> };
    no-1-8-v
    };
};
  
  
&pinctrl0gem3 {
    status = "okay";
    pinctrl_sdhci1_default: sdhci1-default {phy-handle = <&ethernet_phy1>;

    nvmem-cells = <&eth1_addr>;
  mux {
 nvmem-cell-names = "mac-address";
    
     groupsphy-mode = "sdio1_0_grprgmii-id";
};
  
      
/*-------------------- I2C Bus on function = "sdio1";
        };
 PL ----------------------*/
/* for CPLD I2C controller */
&axi_iic_0 {
        confiexp@20 {// GPIO in CPLD
            groups#gpio-cells = "sdio1_0_grp"<2>;
            slew-rate//compatible = <1>"ti,pcf8574";
            io-standardreg = <1><0x20>;
            biasgpio-disablecontroller;
        };
/* 
        mux-cd {
    
        groups = "sdio1_cd_0_grp";
            function = "sdio1_cd";
        };
 
        conf-cd};
};


/*----------------- I2C Bus on PS MIO 34,35 ---------------*/
/* on MIO */
&i2c0 {
    eeprom51: eeprom@51 {
        compatible =   groups = "sdio1_cd_0_grp"microchip,24aa025", "atmel,24c02";
        reg    bias-high-impedance= <0x51>;
      
      bias-pull-up;
  #address-cells = <1>;
        slew#size-ratecells = <1>;
        eth2_addr: eth-mac-addr@FA {
  io-standard        reg = <1><0xFA 0x06>;
        };
  
    };
    mux-wp {

    eeprom52: eeprom@52 {
        groupscompatible = "sdio1_wp_0_grpmicrochip,24aa025", "atmel,24c02";
        reg    function = "sdio1_wp"<0x52>;
        };
 
        conf-wp {#address-cells = <1>;
            groups#size-cells = "sdio1_wp_0_grp"<1>;
            bias-high-impedance;eth1_addr: eth-mac-addr@FA {
          reg  bias-pull-up= <0xFA 0x06>;
        
    slew-rate   = <1>};
    };
    
    io-standard = <1>;
eeprom53: eeprom@53 {
         }compatible = "microchip,24aa025", "atmel,24c02";
*/ 
       reg = 
<0x53>;    }; 
    };
 

     
 
/* ETH PHY */
 
eeprom56: 
eeprom@56 {
/* Note: gem1 on REV01 */
 
&gem2 {
   compatible status = "okay= "microchip,24lc128", "atmel,24c128";
    phy-mode = "rgmii-id";
     phy-handlereg = <&ethernet_phy1>;<0x56>;     
    ethernet_phy0: ethernet-phy@0 {
};
    
    rtc@6F {     compatible = "marvell,88e1510";
     // Real Time Clock
        regcompatible = <0>"isl12022";
        reg = <0x6F>;
  #address-cells = <0x1>};
    
};

&rtc {
    status =  #size-cells = <0x1>;
    };
    ethernet_phy1: ethernet-phy@1 {
  "disabled";
};


/*----------------- I2C Bus on PS MIO 28,29 ---------------*/
&i2c1 {
    i2cswitch@75 { // u35
         compatible = "marvellnxp,88e1510pca9544";
           reg #address-cells = <1>;
           #address#size-cells = <0x1><0>;
        reg = <0x70>;
     #size-cells  = <0x1> i2c-mux-idle-disconnect;
      };
};
 
 
&gem3i2c@0 { // DSPLL0
      status = "okay";
    phy-modereg = "rgmii-id"<0>;
      phy-handle = <&ethernet_phy0>;
};
 
 
 
/* USB  REV01 only */
i2c@1 { 
//*
&dwc3_0 {
 DSPLL1
      status = "okay";
    dr_modereg = "host"<1>;
      maximum-speed = "high-speed"};
    /delete-property/phy-names;
    i2c@2 { /delete-property/phys;/ J34
    /delete-property/snps,usb3_lpm_capable;
     snps,dis_u2_susphy_quirk;
    snps,dis_u3_susphy_quirk;
};
reg = <2>;
       
&usb0 {};
    status = "okay";
  i2c@3 { /delete-property/ clocks;J34
    /delete-property/ clock-names;
        clocksreg = <0x3 0x20><3>;
    clock-names   = "bus_clk"};
    };
}; */        

• Add description for other Software, for example SI CLK Builder ...
• SI5338 and SI5345 also Link to:
  • Si5345
  • Si5338

• Note this list must be only updated, if the document is online on public doc!
• It's semi automatically, so do following
  

  • Add new row below first

  • Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

  • Metadata is only used of compatibility of older exports