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The Trenz Electronic TE0823 -01-3PIU1FL is (3PIU1FA /3PIU1FL) is an industrial-grade MPSoC module integrating a low power Xilinx Zynq UltraScale+ ZU3CGMPSoC, 1 GByte LPDDR4 SDRAM, 128 MByte , 8 GB eMMC chip, 2x 64 MB Flash memory for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking connections.. The module is equipped with a Lattice Mach XO2 CPLD for system controlling. 3x Robust high-speed connectors provide a large number of inputs and outputs.
The highly integrated modules are All this on a tiny footprint, smaller than a credit card , at the most competitive price. Modules in and are offered in several variants at an affordable price-performance ratio. Modules with a 4 x 5 cm form factor are fully completely mechanically and largely electrically compatible among with each other.
All parts are at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Refer to http://trenz.org/te0823-info for the current online version of this manual and other available documentation.
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Note: 'description: Important components and connector or other Features of the module → please sort and indicate assembly options Key Features' must be split into 6 main groups for modules and mainboards: - SoC/FPGA
- Package: SFVC784
- Device: ZU2...ZU5*
- Engine: CG, EG, EV*
- Speed: -1LI, -2LE,*, **
- Temperature: I, E,*, **
- RAM/Storage
- Low Power DDR4 on PS
- Data width: 32bit
- Size: def. 2GB*
- Speed:***
- eMMC
- Data width: 8Bit
- size: def. 8GB *
- QSPI boot Flash in dual parallel mode (size depends on assembly version)
- Data width: 8bit
- size: def. 128MB *
- HyperRAM/Flash (optional, default not assembled)
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
- On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
- Interface
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, Sata, PCIe, DP)
- MIO for UART
- MIO for SD
- MIO for PJTAG
- JTAG
- Ctrl
- Power
- 3.3V-5V Main Input
- 3.3V Controller Input
- Variable Bank IO Power Input
- Dimension
- Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
Key Features' must be split into 6 main groups for carrier: - Modules
- TE0808, TE807, TE0803,...
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
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- SoC/FPGAXilinx Zynq UltraScale+ XCZU3CG-L1SFVC784I
- Application Processor: Dual-core ARM Cortex-A53 MPCore
- Real-Time Processor: Dual-core ARM Cortex-R5 MPCore
Package: SFVC784, SFRC784
- Device: ZU3ZU2 ...ZU5, *
- Engine: EG, CG, EV, *
- Speed: -1LI (also non-low power assembly options possible)1, -1L, -2, -2L, 3, *, **
- Temperature: I, E, *, **Temperature range: industrial
RAM/Storage- Low power DDR4 on PS with 32 bit data width
- 2x DDR4 SDRAM,
- Data Width: 32 Bit
- Size: 16 Gb, *
- Speed: 3733 Mbps, ***
- 2x 128 MByte QSPI boot Flash in dual parallel mode
- Data Width: 8 Bit
- Size: 512 Mb Gb, *
- 1x 8 GByte e.MMC memory with 8 bit data widthMemory
- Data Width: 8 Bit
- Size: 32 Gb, *
- MAC address serial EEPROM with EUI-48 node identity
On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY
- MachXO2 CPLD
- Programmable Clock Generator
- Hi-speed USB2 ULPI Transceiver
- 4x LEDS
Interface- 1x GB/s serial GMII interface
- 1x Hi-speed USB2 ULPI transceiver with full OTG support
Interface- 132 x HP PL 154 x High Performance (HP) und 96 x High Density (HD) I/Os (3 banks)
- ETH
- USB
- 78 x PS MIOs
- 4 x serial PS GTR transceivers
- PCI Express interface version 2.1 compliant
- SATA 3.1 specification compliant interface
DisplayPort
4 GTR (for USB3, SATA, PCIe, DP)
Four high-speed serial I/O (HSSIO) interfaces supporting following protocols: - 14 x PS MIOs
- MIO for UART
- thereof 6 MIO for SD card interface (default configuration)
- MIO for PJTAG
- JTAG
- Ctrl
Power- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, SATA, PCIe, DP)
Four high-speed serial I/O (HSSIO) interfaces supporting following protocols: - 14 x PS MIOs
- MIO for UART
- thereof 6 MIO for SD card interface (default configuration)
- MIO for PJTAG
- JTAG
- Ctrl
DimensionNotes- Rugged for shock and high vibration
- Evenly spread supply pins for good signal integrity
- Plug-on module with 2 x 100 pin and 1 x 60 pin Razor Beam High-Speed hermaphroditic Terminal/Socket Strips (low profile, 2,5 mm)
Block Diagram
- Power
- All power regulators on board
- Dimension
- Note
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
- Rugged for shock and high vibration
BlockDiagram
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anchor | Figure_OV_BD |
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title | TE0823 block diagram |
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Main Components
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- Xilinx Zynq UltraScale+ XCZU3EG, U1
- Red LED (ERR_OUT), D3
- Green User LED, D2
- Green LED (ERR_STATUS), D4
- Red LED (DONE), D1
- 10/100/1000 Mbps energy efficient ethernet transceiver, U8
- 8Gb DDR4, U2-U3
- 512 Mbit QSPI flash memory, U7-U17
- B2B connector Samtec Razor Beam, JM1
- B2B connector Samtec Razor Beam, JM3
- Programmable clock generator, U10
- USB2.0 Transceiver, U18
- B2B connector Samtec Razor Beam, JM3
- B2B connector Samtec Razor Beam, JM2
- JM2
- 8 GByte 8 GByte eMMC memory, U6
- Lattice Semiconductor MachXO2 System Controller CPLD, U21
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title | Initial delivery state of programmable devices on the module |
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Storage device name | Content | Notes | Quad SPI Flash |
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QSPI Flash Memory | Not programmed |
| eMMC Memory | Not programmed |
| Programmable Clock Generator | Not programmed |
| CPLD (LCMXO2-256HC) | SC0820-02 QSPI Firmware | EEPROM | System Controller CPLD |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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title | Boot process. |
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MODE Signal State | Boot Mode |
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High | QSPI* | Low | SD Card* |
*changable also with other CPLD Firmware:TE0823 CPLD |
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anchor | Table_OV_RST |
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title | Reset process. |
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Signal | B2B | I/O | Note |
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RESIN | JM2-18 | Input |
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Signals, Interfaces and Pins
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title | General PL I/O to B2B connectors information |
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FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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JTAG access to the TExxxx SoM through B2B connector JMX.
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anchor | Table_SIP_JTG |
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title | JTAG pins connection |
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24 | HD | JM2 | 24x I/O, 12x LVDS Pairs | Variable | Max voltage 3.3V | 25 | HD | JM1 | 24x I/O, 12x LVDS Pairs | Variable | Max voltage 3.3V | 26 | HD | JM1 | 24x I/O, 12x LVDS Pairs | Variable | Max voltage 3.3V | 44 | HD | JM2 | 24x I/O, 12x LVDS Pairs | Variable | Max voltage 3.3V | 65 | HP | JM2 | 18x I/O, 9x LVDS Pairs | Variable | Max voltage 1.8V | 65 | HP | JM3 | 16x I/O, 8x LVDS Pairs | Variable | Max voltage 1.8V | 505 | GTR | JM3 | 16x I/O, 8x LVDS Pairs | - | 4x lanes | 505 | GTR CLK | JM3 | 1x Diff Clock | - |
| 501 | MIO | JM1 | 15 I/O | 3.3V |
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JTAG Interface
JTAG access to the Xilinx Zynq UltraScale+ is applicable by using Lattice MachXO CPLD through B2B connector JM2.
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JTAG Signal
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B2B Connector
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MIO Pins
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.
Example:
MIO Pin | Connected to | B2B | Notes |
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MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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anchor | Table_SIP_MIOsJTG |
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title | MIOs JTAG pins connection |
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MIO Pin | Connected toJTAG Signal | B2B Connector | Notes |
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Test Points
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.
Example:
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TMS | JM2-93 |
| TDI | JM2-95 |
| TDO | JM2-97 |
| TCK | JM2-99 |
| JTAGEN | JM1-89 | Pulled Low: Xilinx Zynq UltraScale+ MPSoC Pulled High: Lattice MachXO CPLD |
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MGT Lanes
There are 4x MGT Lanes connected to FPGA Bank 505-GTR.
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anchor | Table_SIP_TPsMGT |
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title | Test Points InformationMGT Lanes connection |
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Test PointSignalConnected toNotes | |
On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
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anchor | Table_OBP |
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title | On board peripherals |
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Quad SPI Flash Memory
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Notes :
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Note |
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0 | - B505_RX0_P
- B505_RX0_N
- B505_TX0_P
- B505_TX0_N
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| 1 | - B505_RX1_P
- B505_RX1_N
- B505_TX1_P
- B505_TX1_N
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| 2 | - B505_RX2_P
- B505_RX2_N
- B505_TX2_P
- B505_TX2_N
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| 3 | - B505_RX2_P
- B505_RX2_N
- B505_TX2_P
- B505_TX2_N
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Gigabit Ethernet
On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 chip. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an on-board 25MHz oscillator (U11), the 125MHz output clock is left unconnected.
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anchor | Table_SIP_ETH |
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title | GigaBit Ethernet connection |
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Pin | Schematic | Connected to | Note |
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MDIP0...3 | PHY_MDI0...3 | B2B, JM1 |
| MDC | ETH_MDC | MIO76 |
| MDIO | ETH_MDIO | MIO77 |
| S_IN | S_IN | B2B, JM3 |
| S_OUT | S_OUT | B2B, JM3 |
| TXD0..3 | ETH_TXD0...3 | MIO65...68 |
| TX_CTRL | ETH_TXCTL | MIO69 |
| TX_CLK | ETH_TXCK | MIO64 |
| RXD0...3 | ETH_RXD0...3 | MIO71...74 |
| RX_CTRL | ETH_RXCTL | MIO75 |
| RX_CLK | ETH_RXCK | MIO70 |
| LED0...2 | PHY_LED0...2 | FPGA Bank 66 |
| RESETn | ETH_RST | MIO24 |
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System Controller CPLD
Special purpose pins are connected to System Controller CPLD and have following default configuration:
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anchor | Table_SIP_CPLD |
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title | System Controller CPLD special purpose pins |
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Pin Name | Mode | Function | Default Configuration |
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EN1 | Input | Power Enable | No hard wired function on PCB. When forced low, PGOOD goes low without effect on power management | PGOOD | Output | Power Good | Only indirect used for power status, see CPLD description | NOSEQ | - | - | No used for Power sequencing, see CPLD description | RESIN | Input | Reset | Active low reset, gated to POR_B | JTAGEN | Input | JTAG Select | Low for normal operation, high for CPLD JTAG access |
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USB Interface
USB PHY is provided by Microchip USB3320. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V. Reference clock input for the USB PHY is supplied by the on-board 52.00 MHz oscillator (U14).
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anchor | Table_SIP_USB |
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title | General overview of the USB PHY signals |
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PHY Pin | ZYNQ Pin | B2B Name | Notes |
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ULPI | MIO52..63 | - | Zynq USB0 MIO pins are connected to the USB PHY. | REFCLK | - | - | 52.000000 MHz from on-board oscillator (U14). | REFSEL[0..2] | - | - | Reference clock frequency select, all set to GND selects 52.000000 MHz. | RESETB | MIO25 | - | Active low reset. | CLKOUT | MIO52 | - | Connected to 1.8V, selects reference clock operation mode. | DP, DM | - | OTG_D_P, OTG_D_N | USB data lines routed to B2B connector JM3 pins 47 and 49. | CPEN | - | VBUS_V_EN | External USB power switch active high enable signal, routed to JM3 pin 17. | VBUS | - | USB_VBUS | Connect to USB VBUS via a series of resistors, see reference schematics, routed to JM3 pin 55. | ID | - | OTG_ID | For an A-device connect to ground, for a B-device left floating. routed from JM3 pin 23. |
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I2C Interface
On-board I2C devices are connected to MIO38 (SCL) and MIO39 (SDA) which are configured as I2C0 by default. Addresses for on-board I2C slave devices are listed in the table below:
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anchor | Table_SIP_I2C |
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title | Address table of the I2C bus slave devices |
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I2C Device | I2C Address | Notes |
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Si5338A PLL | 0x70 | - | EEPROM | 0x50 | - |
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MIO Pins
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: MIO Pin | Connected to | B2B | Notes |
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MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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anchor | Table_SIP_MIOs |
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title | MIOs pins |
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orientation | portrait |
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MIO Pin | Connected to | B2B | Notes |
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0...5 | QSPI Flash, U7 | - | SPI Flash | 7...12 | QSPI Flash, U17 | - | SPI Flash | 13...23 | eMMC, U6 |
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| 24 | ETH Transceiver, U8 | - | ETH_RST | 25 | USB2.0 Transceiver, U18 | - | OTG_RST | 26...33 | User MIO | JM1 |
| 34...37 | N.C | - | N.C | 38...39 | EEPROM, U25 | - | I2C_SDA/SCL | 40...45 | N.C |
| N.C | 46...51 | SD Card | JM1 |
| 52...63 | USB2.0 Transceiver, U18 | - |
| 63...77 | Ethernet Transceiver, U8 | - |
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Test Points
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example: Test Point | Signal | B2B | Notes |
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10 | PWR_PL_OK | J2-120 |
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anchor | Table_SIP_TPs |
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title | Test Points Information |
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orientation | portrait |
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sortDirection | ASC |
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Test Point | Signal | Connected to | Notes |
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1 | PS_LP0V85 | Regulator, U12 |
| 2 | SRST_B | FPGA Bank 503, U1H | PSCONFIG | 3 | PS_AVCC | Regulator, U9 |
| 4 | +1.1V_LPDDR4 | Regulator, U15 |
| 5 | PS_AVTT | Regulator, U13 |
| 6 | - | - |
| 7 | PS_FP0V85 | Regulator, U26 |
| 8 | PS_LP0V85 | Voltage Regulator, U12 |
| 9 | POR_B | Voltage Regulator, U19 |
| 10 | PS_PLL | Voltage Regulator, U23 |
| 11 | PL_VCCINT | Voltage Regulator, U5 |
| 12...15 | - | - |
| 16 | PL_VCU | Voltage Regulator, U24 |
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On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
Scroll Title |
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anchor | Table_OBP |
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title | On board peripherals |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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Quad SPI Flash Memory
The TE0821 is equipped with dual Flash Memory, U7, U17. Two quad SPI compatible serial bus flash memory chips are provided for FPGA configuration file and data storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
Scroll Title |
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anchor | Table_OBP_SPI |
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title | Quad SPI interface MIOs and pins |
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orientation | portrait |
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Pin | Schematic | Notes |
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QSPI, U7 | QSPI, U17 |
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nCS | MIO5 | MIO7 |
| CLK | MIO0 | MIO12 |
| DI/IO0 | MIO4 | MIO8 |
| DO/IO1 | MIO1 | MIO9 |
| nHOLD/IO3 | MIO3 | MIO11 |
| WP/IO2 | MIO2 | MIO10 |
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EEPROM
There is a 2Kb EEPROM provided on the module TE0821.
Scroll Title |
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anchor | Table_OBP_EEP |
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title | I2C EEPROM interface MIOs and pins |
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MIO Pin | Schematic | U?? Pin | Notes |
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MIO39 | I2C_SDA | SDA |
| MIO38 | I2C_SCL | SCL |
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anchor | Table_OBP_I2C_EEPROM |
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title | I2C address for EEPROM |
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orientation | portrait |
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sortDirection | ASC |
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MIO Pin | I2C Address | Designator | Notes |
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MIO38-MIO39 | 0x50 | U25 |
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LEDs
Scroll Title |
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anchor | Table_OBP_LED |
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title | On-board LEDs |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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cellHighlighting | true |
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Designator | Color | Connected to | Active Level | Note |
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D1 | Red | DONE | Low |
| D2 | Green | USR_LED | High |
| D3 | Red | ERR_OUT | High |
| D4 | Green | ERR_STATUS | High |
|
|
DDR4 SDRAM
Page properties |
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|
Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE0823 SoM has a 1 GB volatile LPDDR4 SDRAM IC for storing user application code and data.
- Part number: IS43LQ32256A
- Supply voltage: 1.7V ~ 1.95V
- Speed: 3200 Mbps
- Temperature: -40 ~ 95 °C
Gigabyte Ethernet
On-board Gigabit Ethernet PHY (U8) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the ZynqMP Ethernet3 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.00 MHz oscillator (U11).
Scroll Title |
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anchor | Table_OBP_ETH |
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title | Ethernet PHY to Zynq SoC connections |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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U8 Pin | Schematic | Connected to | Note |
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MDIP0...3 | PHY_MDI0...3 | B2B, JM1 |
| MDC | ETH_MDC | MIO76 |
| MDIO | ETH_MDIO | MIO77 |
| S_IN | S_IN | B2B, JM3 |
| S_OUT | S_OUT | B2B, JM3 |
| TXD0..3 | ETH_TXD0...3 | MIO65...68 |
| TX_CTRL | ETH_TXCTL | MIO69 |
| TX_CLK | ETH_TXCK | MIO64 |
| RXD0...3 | ETH_RXD0...3 | MIO71...74 |
| RX_CTRL | ETH_RXCTL | MIO75 |
| RX_CLK | ETH_RXCK | MIO70 |
| LED0...2 | PHY_LED0...2 | FPGA Bank 66 |
| RESETn | ETH_RST | MIO24 |
|
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Clock Sources
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anchor | Table_OBP_CLK |
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title | Osillators |
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orientation | portrait |
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sortDirection | ASC |
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Designator | Description | Frequency | Note |
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U11 | MEMS Oscillator | 25 MHz |
| U14 | MEMS Oscillator | 52 MHz |
| U32 | MEMS Oscillator | 80 MHz |
|
|
USB2.0 Transceiver
Hi-speed USB ULPI PHY (U18) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO52..63, bank 502. The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.00 MHz oscillator (U14).
eMMC Flash Memory
eMMC Flash memory device(U6) is connected to the ZynqMP PS MIO bank 500 pins MIO13..MIO23. eMMC chips IS21ES08G-JCLI (FLASH - NAND Speicher-IC (64 Gb x 1) MMC ) is used.
Programmable Clock Generator
There is a Silicon Labs I2C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I2C bus address 0x70 or 0x71. Default address is 0x70, IN4/I2C_LSB pin must be set to high for address 0x71.
A 25.00 MHz oscillator is connected to the pin IN3 and is used to generate the output clocks. The oscillator has its output enable pin permanently connected to 1.8V power rail, thus making output frequency available as soon as 1.8V is present. Three of the Si5338 clock outputs are connected to the FPGA. One is connected to a logic bank and the other two are connected to the GTR banks.
Once running, the frequency and other parameters can be changed by programming the device using the I2C bus connected between the FPGA (master) and clock generator (slave). For this, proper I2C bus logic has to be implemented in FPGA.
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anchor | Table_OBP_SPIPCLK |
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title | Quad SPI interface MIOs and pinsProgrammable Clock Generator Inputs and Outputs |
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MIO Schematic | U?? Pin | Notes | |
EEPROM
...
anchor | Table_OBP_EEP |
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title | I2C EEPROM interface MIOs and pins |
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Signal | Connected to | Direction | Note |
---|
IN0..1 | CLK_IN | JM3 | IN |
| IN2 | CLK_25M | Oscillator, U11 | IN |
| SCL | I2C_SCL | EEPROM,U25 | INOUT |
| SDA | I2C_SDA | EEPROM,U25 | INOUT |
| CLK0 | CLK0 | JM3 | OUT |
| CLK1 | B505_CLK3 | FPGA Bank 505 | IN |
| CLK2 | B505_CLK1 | FPGA Bank 505 | IN |
| CLK3 | CLK3_N |
| IN |
|
|
Power and Power-On Sequence
Page properties |
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|
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
|
Power Supply
Power supply with minimum current capability of 2.5 A for system startup is recommended.
Power Consumption
...
anchor | Table_OBP_I2C_EEPROM |
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title | I2C address for EEPROM |
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...
LEDs
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anchor | Table_OBPPWR_LEDPC |
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title | On-board LEDsPower Consumption |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Color | Connected to | Active Level | Note |
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DDR3 SDRAM
Page properties |
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|
Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.
- Part number:
- Supply voltage:
- Speed:
- NOR Flash
- Temperature:
...
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Power Input Pin | Typical Current |
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VIN | TBD* |
|
* TBD - To Be Determined
Power Distribution Dependencies
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anchor | TableFigure_OBPPWR_ETHPD |
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title | Ethernet PHY to Zynq SoC connectionsPower Distribution |
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tablelayoutorientationportrait |
sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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U?? Pin | Signal Name | Connected to | Signal Description | Note |
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diagramName | TE0823_PWR_PD |
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lbox | true |
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diagramWidth | 640 |
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revision | 10 |
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Power-On Sequence
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anchor | TableFigure_OBP_CLK |
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title | Osillators |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Description | Frequency | Note |
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MHz | MHz | KHz |
Programmable Clock Generator
...
PWR_PS | title | Power Sequency |
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draw.io Diagram |
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border | false |
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diagramName | TE0823_PWR_PS |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramDisplayName | |
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lbox | true |
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diagramWidth | 640 |
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revision | 6 |
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Power Rails
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anchor | Table_OBPPWR_PCLKPR |
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title | Programmable Clock Generator Inputs and OutputsModule power rails. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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cellHighlighting | true |
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|
U?? Pin
| Signal | Connected to | Direction | Note |
---|
IN0 | IN1 | IN2 | IN3 | XAXB | SCLK | SDA | OUT0 | OUT1 | OUT2 | OUT3 | OUT4 | OUT5 | OUT6 | OUT7 | OUT8/OUT9 |
Power and Power-On Sequence
...
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
- Power on-sequence
- Power distribution
- Voltage monitoring circuit
Note |
---|
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" . |
| ASC |
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repeatTableHeaders | default |
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widths | |
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cellHighlighting | true |
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Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes |
---|
VIN | 1, 3, 5 | 2, 4, 6, 8 | Input | Supply voltage from the carrier board |
| 3.3V | - | 10, 12 | Output | Internal 3.3V voltage level |
| 3.3VIN | 13, 15 | - | Input | Supply voltage from the carrier board |
| 1.8V | 39 | - | Output | Internal 1.8V voltage level |
| JTAG VREF | - | 91 | Output | JTAG reference voltage. Attention: Net name on schematic is "3.3VIN" |
| VCCO_64 | - | 7, 9 | Input | High performance I/O bank voltage |
| VCCO_65 | - | 5 | Input | High performance I/O bank voltage |
| VCCO_66 | 9, 11 | - | Input | High performance I/O bank voltage |
|
|
Bank Voltages
Power Supply
Power supply with minimum current capability of xx A for system startup is recommended.
...
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anchor | Table_PWR_PCBV |
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title | Power ConsumptionZynq SoC bank voltages. |
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orientation | portrait |
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repeatTableHeaders | default |
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style | |
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cellHighlighting | true |
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|
Power Input Pin | Typical Current |
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VIN | TBD* |
* TBD - To Be Determined
Power Distribution Dependencies
...
anchor | Figure_PWR_PD |
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title | Power Distribution |
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| Schematic Name | | Notes |
---|
24 HD | VCCO_HD24_24 | Variable | Max voltage 3.3V | 25 HD |
| Variable | Max voltage 3.3V | 26 HD | VCCO_HD25_26 | Variable | Max voltage 3.3V | 44 HD | VCCO_HD24_44 | Variable | Max voltage 3.3V | 65 HP | VCCO_65 | Variable | Max voltage 1.8V | 66 HP | VCCO_66 | 1.8V |
| 500 PSMIO | VCCO_PSIO0_500 | 1.8V |
| 501 PSMIO | VCCO_PSIO1_501 | 3.3V |
| 502 PSMIO | VCCO_PSIO2_502 | 1.8V |
| 503 PSCONFIG | VCCO_PSIO3_503 | 1.8V |
| 504 PSDDR | DDR_1V2 | 1.2V |
|
|
Board to Board Connectors
Page properties |
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|
- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
Include Page |
---|
| 6 x 6 SoM LSHM B2B Connectors |
---|
| 6 x 6 SoM LSHM B2B Connectors |
---|
|
|
Include Page |
---|
| 4 x 5 SoM LSHM B2B Connectors |
---|
| 4 x 5 SoM LSHM B2B Connectors |
---|
|
Technical Specifications
Absolute Maximum Ratings
...
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Image Removed |
Power-On Sequence
...
anchor | Figure_PWR_PS |
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title | Power Sequency |
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...
Scroll Only |
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Image Removed |
Power Rails
Scroll Title |
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anchor | Table_PWRTS_PRAMR |
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title | Module power rails.PS absolute maximum ratings |
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|
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortEnabled | false |
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cellHighlighting | true |
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|
Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes |
---|
Bank Voltages
...
anchor | Table_PWR_BV |
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title | Zynq SoC bank voltages. |
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...
...
...
...
Symbols | Description | Min | Max | Unit |
---|
VIN supply voltage | -0.3 | 7 | V | See EN6347QI and TPS82085SIL datasheets | 3.3VIN supply voltage | -0.1 | 3.630 | V | Xilinx DS925 and TPS27082L datasheet | PS I/O supply voltage, VCCO_PSIO | -0.5 | 3.630 | V | Xilinx document DS925 | PS I/O input voltage | -0.5 | VCCO_PSIO + 0.55 | V | Xilinx document DS925 | HP I/O bank supply voltage, VCCO | -0.5 | 2.0 | V | Xilinx document DS925 | HP I/O bank input voltage | -0.55 | VCCO + 0.55 | V | Xilinx document DS925 | PS GTR reference clocks absolute input voltage | -0.5 | 1.1 | V | Xilinx document DS925 | PS GTR absolute input voltage | -0.5 | 1.1 | V | Xilinx document DS925 | Voltage on SC CPLD pins | -0.5 | 3.75 | V | Lattice Semiconductor MachXO2 datasheet | Storage temperature | -40 | +85 | °C | See eMMC datasheet |
|
Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
use "include page" macro and link to the general B2B connector page of the module series,
...
Technical Specifications
...
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anchor | Table_TS_AMRROC |
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title | PS absolute maximum ratingsRecommended operating conditions. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortEnabled | false |
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cellHighlighting | true |
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SymbolsDescription | Unit | Units | Reference Document |
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VIN supply voltage | 3.3 | 6 |
V | V | VV | |
Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
See TPS82085S datasheet | 3.3VIN supply voltage | 3.3 | 3.465 | V | See LCMXO2-256HC, Xilinx DS925 datasheet | PS I/O supply voltage, VCCO_PSIO | 1.710 | 3.465 | V | Xilinx document DS925 | PS I/O input voltage | –0.20 | VCCO_PSIO + 0.20 | V | Xilinx document DS925 | HP I/O banks supply voltage, VCCO | 0.950 | 1.9 | V | Xilinx document DS925 | HP I/O banks input voltage | -0.20 | VCCO + 0.20 | V | Xilinx document DS925 | Voltage on SC CPLD pins | -0.3 | 3.6 | V | Lattice Semiconductor MachXO2 datasheet | Operating Temperature Range | 0 | 85 | °C | Xilinx document DS925, extended grade Zynq temperarure range |
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anchor | Table_TS_ROC |
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title | Recommended operating conditions. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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cellHighlighting | true |
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Parameter | Min | Max | Units | Reference Document |
---|
V | See ???? datasheets. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | °C | See Xilinx ???? datasheet. | °C | See Xilinx ???? datasheet. |
Physical Dimensions
Module size: ?? 40 mm × ?? 50 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ? 8 mm.
PCB thickness: ?? 1.7 mm.
Page properties |
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|
In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM. For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below: https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF
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...
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anchor | Figure_TS_PD |
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title | Physical Dimension |
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draw.io Diagram |
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border | truefalse |
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diagramName | TE0823_TS_PD |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramDisplayName | top | |
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lbox | true |
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diagramWidth | 641542 |
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revision | 14 |
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scroll-pdf | true |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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anchor | Table_RH_HRH |
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title | Hardware Revision History |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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cellHighlighting | true |
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Date | Revision | Changes | Documentation Link |
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2018-09-25 | REV01 | Initial Release | REV01 |
|
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
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anchor | Figure_RV_HRN |
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title | Board hardware revision number. |
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scroll-pdf | true |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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| draw.io Diagram |
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border | truefalse |
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diagramName | TE0823_RV_HRN |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hiddentop |
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diagramDisplayName | |
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lbox | true |
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diagramWidth | 254170 |
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revision | 12 |
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Document Change History
...
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anchor | Table_RH_DCH |
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title | Document change history. |
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orientation | portrait |
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Date | Revision | Contributor | Description |
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Page info |
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infoType | Modified date |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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infoType | Current version |
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prefix | v. |
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type | Flat |
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showVersions | false |
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| Page info |
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infoType | Modified by |
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type | Flat |
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showVersions | false |
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| | 2021-08-23 | v.42 | Pedram Babakhani | | 2020-11-02 | v.40 | Pedram Babakhani | | -- | all | Page info |
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infoType | Modified users |
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