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Refer to httpshttp://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/carrier_boards/TEBF0808/REV04 for downloadableorg/tebf0808-info for the current online version of this manual and additionalother technicalavailable documentation of the product.

The Trenz Electronic TEBF0808 carrier board is a baseboard for the Xilinx Zynq Ultrascale+ MPSoC modules TE0808 and TE0803, which exposes the module's B2B connector pins to accessible connectors and provides a whole range of on-board components to test and evaluate the Zynq Ultrascale+ SoMs and for developing purposes. The carrier board has a Mini-ITX form factor making it capable to be fitted into a PC enclosure. On the PC enclosure's rear and front panel, MGT interfaces and connectors are accessible, for the front panel elements there are also Intel-PC compatible headers available.

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Mini-ITX form factor, PC enclosure compatible
ATX-24 power supply connector
Optional 12V standard power plug
Headers
- Intel 10-pin HDA Audio
- Intel 9-pin Power-/Reset-Button, Power-/HD-LED
- PC-BEEPER
On-board Power- / Reset-Switches
2x Configuration 4-bit DIP-switches
2x Optional 4-wire PWM fan connectors
PCIe Slot - one PCIe lane (16 lane connector)
CAN FD Transceiver (10 Pin IDC connector and 6-pin header)
4x On-board configuration EEPROMs (1x Microchip 24LC128-I/ST, 3x Microchip 24AA025E48T-I/OT)
Dual SFP+ Connector (2x1 Cage)
1x DisplayPort (single lane)
1x SATA Connector
2x USB3.0 A Connector (Superspeed Host Port (Highspeed at USB2.0))
1x USB3.0 on-board connector with two ports
FMC HPC Slot (FMC_VADJ max. VCCIO)
FMC Fan
Gigabit Ethernet RGMII PHY with RJ45 MegJackMagJack
All carrier board peripherals' I²C interfaces muxed to MPSoC's I²C interface
Quad programmable PLL clock generator SI5338A
2x SMA coaxial connectors for clock signals
MicroSD- / MMC-Card Socket (bootable)
32 Gbit (4 GByte) on-board eMMC flash (8 banks a 4 Gbit)
2x System Controller CPLDs Lattice MachXO2 1200 HC
1x Samtec FireFly (4 GT lanes bidirectional)
1x Samtec FireFly connector for reverse loopback
2x JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for programming MPSoC and SC CPLDs
20-pin ARM JTAG Connector (PS JTAG0)
3x PMOD connector (GPIO's and I²C interface to SC CPLDs and MPSoC module)
On-board DC-DC PowerSoCs

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On-board Peripheral	B2B	MPSoC Unit / SoM peripheral	Description	TRM Section
FMC HPC J5, 24 LVDS pairs (48 I/O's)	J1	PL Bank (FMC_VADJ)	PL I/O-bank pins, differential pairs	FMC HPC Connector
FMC HPC J5, GTH Interface	J1	MGT Bank	10 MGT Lanes	FMC HPC Connector
SFP+ 2x1 Cage J14	J1	MGT Bank	2 MGT Lanes to dual SFP+ Connector	MGT Interfaces SFP+ and FireFly
SMA Coax J33	J1	On-module PLL	SMA Coaxial Connector to on-module PLL Clock Input pin	Programmable PLL Clock Generator
FMC HPC J5 10 LVDS pairs (20 I/O's) 1 LVDS Clock to PL Bank 2 MGT Clocks to MGT Banks	J2	PL Bank (FMC_VADJ) MGT Bank	PL I/O-bank pins, differential pairs 1 clock capable PL bank pin-pair 2 MGT clock input pin-pairs	FMC HPC Connector Programmable PLL Clock Generator
24-bit Audio Codec U3	J3	PL Bank (1.8 V)	PL I/O-bank pins to on-board 24-bit Audio Codec	Intel-PC Compatible Headers and FAN Connectors 24-bit Audio Codec
10 I/O's to SC CPLD U17	J3	PL Bank (1.8 V)	PL I/O-bank pins to on-board System Controller CPLD U17	System Controller CPDLsCPLDs
8 I/O's to SC CPLD U39	J3	PL Bank (1.8 V)	PL I/O-bank pins to on-board System Controller CPLD U39	System Controller CPDLsCPLDs
SDIO Interface, SD- / MMC-Card Mux	J3	PS MIO	SDIO interface connected to SD- / MMC-Card socket	MIO Bank Interfaces SDIO Port Expander
Board Peripheral's I²C Interfaces muxed to MPSoC I²C	J3	PS MIO	MPSoC I²C interface configured as master connected to on-board slaves	MIO Bank Interfaces 8-Channel I²C Switches
4 MIO to SC CPLD U17	J3	PS MIO	Functionality depending on MPSoC and CPLD firmware	System Controller CPDLsCPLDs
15 MIO to SC CPLD U39	J3	PS MIO	Functionality depending on MPSoC and CPLD firmware	System Controller CPDLs
Ethernet PHY RGMII	J3	PS MIO	Ethernet PHY U12 connected per RGMII	MIO Bank Interfaces Gigabit Ethernet PHY
eMMC Flash	J3	PS MIO	eMMC Flash memory interface on PS bank	MIO Bank Interfaces eMMC Memory
USB2.0 PHY ULPI	J2	PS MIO	USB2.0 PHY U9 connected per ULPI	MIO Bank Interfaces High-speed USB ULPI PHY
SAMTEC FireFly Connector J6/J15	J2	MGT Bank	MGT Lanes to Samtec FireFly connector	MGT Interfaces SFP+ and FireFly
JTAG Interface via XMOD Header J12	J2	PS Config	MPSoC USB programmable JTAG interface	MIO Bank Interfaces JTAG Interface
USB3.0 Lane	J2	PSGT	USB3.0 PS MGT Lane	MIO Bank Interfaces PS GT Bank Interfaces
4-port USB3.0 Hub	-	-	USB3.0 (2.0 compatible) Hub with 4 ports	MIO Bank Interfaces 4-port USB3.0 Hub
USB3.0 / RJ45 GbE Connector J7, USB3.0 Connector J8	-	-	2-port USB3.0 / RJ45 GbE Connector (stacked)	MIO Bank Interfaces
25 SoM Control Signals to SC CPLDs U17 / U39	J2	On-module DC-DC converter, PLL clock generator	Control Signals, e.g. "Enable"- / "Power Good"- signals of DC-DC-converter and further on-module peripherals	Power-On Sequence Diagram Programmable PLL Clock Generator
150 MHz Osci Clock Input	J2	-	150 MHz SATA interface MGT clock	Oscillators
Signals DONE, INIT_B, SRST_B, ... to SC CPLD U39	J2	PS Config	MPSoC control signal for PS- / PL configuration	System Controller CPDLsCPLDs
SATA Connector J31 PCIe Connector J1 DisplayPort J13	J2	PSGT	Connectors of the MGT based data interfaces	PS GT Bank Interfaces
PLL Clock Output to PCIe Interface On-board PLL U35 MGT Bank (B2B J3)	J2	On-module PLL clock generator	Reference clock signals of the on-module programmable PLL clock generator	Programmable PLL Clock Generator
4 I/O's to PMOD P2 via IC U33	J4	PL Bank (FMC_VADJ)	PL user I/O's accessible on PMOD connector P2	CAN FD Interface and PMOD Connectors
3 I/O's to SC CPLD U17 via IC U32	J4	PL Bank (FMC_VADJ)	PL user I/O's routed to System Controller CPLD U17	System Controller CPDLsCPLDs
FMC HPC J5 46 LVDS pairs (92 I/O's) 1 LVDS Clock to PL Bank	J4	PL Bank (FMC_VADJ)	PL I/O-bank pins, differential pairs 1 clock capable PL bank pin-pair	FMC HPC Connector Programmable PLL Clock Generator

...

The MGT-banks have also clock input-pins which are exposed to the FMC connector. Following MGT-lanes are available on the FMC connectors J5:

4 lanes, pins J5-A10, J5-A11, pins J5-A30, J5-A31, pins J5-A6, J5-A7, pins J5-A26, J5-A27, pins J5-A2, J5-A3, pins J5-A22, J5-A23, pins J5-C6, J5-C7 J5C2 J5-C3

B2B	Count Schematic Names of the MGT LanesSignals	Schematic Names / B2B Connector Pins	MGT Bank's Reference Clock Inputs from FMC Connector	J1	Pins
B228_RX3_P, B228_RX3_N	B228_TX3_P, B228_TX3_N	B228_RX2_P, B228_RX2_N	B228_TX2_P, B228_TX2_N	B228_RX1_P, B228_RX1_N	B228_TX1_P, B228_TX1_N	B228_RX0_P, B228_RX0_N	B228_TX0_P, B228_TX0_N	pins J1-51, J1-53 pins	J1-	50,	1 MGT clock (B228_CLK0) from FMC connector J5 (pins J5-D4, J5-D5) to MPSoC's MGT bank
J1	4 lanes	B229_RX3_P, B229_RX3_N, pins J5-B12, J5-B13 B229_TX3_P, B229_TX3_N, pins J5-B32, J5-B33 B229_RX2_P, B229_RX2_N, pins J5-B16, J5-B17 B229_TX2_P, B229_TX2_N, pins J5-B36, J5-B37 B229_RX1_P, B229_RX1_N, pins J5-A18, J5-A19 B229_TX1_P, B229_TX1_N, pins J5-A38, J5-A39 B229_RX0_P, B229_RX0_N, pins J5-A14, J5-A15 B229_TX0_P, B229_TX0_N, pins J5-A34, J5-A35	1 MGT clock (B229_CLK0) from FMC connector J5 (pins J5-B20, J5-B21) to MPSoC's MGT bank
J1	2 lanes	B230_RX1_P, B230_RX1_N, pins J5-B4, J5-B5 B230_TX1_P, B230_TX1_N, pins J5-B24, J5-B25 B230_RX0_P, B230_RX0_N, pins J5-B8, J5-B9 B230_TX0_P, B230_TX0_N, pins J5-B28, J5-B29	-

...

The FMC connector provides pins for reference clock output to the Mezzanine module and clock input to PL banks of the MPSoC:

...

The FMC connector provides further interfaces like JTAG and I²C interfaces:

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FMC_TCK, pin J5-D29

FMC_TMS, pin J5-D33

FMC_TDI, pin J5-D30

FMC_TDO, pin J5- D31

...

VCCIO: 3V3SB

TRST_L, pin J5-D34 pulled-up to 3V3_PER

...

FMC_SCL, pin J5-C30

FMC_SDA, pin J5-C31

...

I²C-lines pulled-up to 3V3_PER

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FMC_PRSNT_M2C, pin J5-H2

FMC_PG_C2M, pin J5-D1 (3V3_PER pull-up)

FMC_PG_M2C, pin J5-F1 (3V3_PER pull-up)

FMC_CLK_DIR, pin J5-B1 (pulled-down to GND)

...

I²C I/O Expander U38

SC CPLD U39, bank 0

I²C I/O Expander U38

SC CPLD U17, bank 1

...

'PG' = 'Power Good'-signal

'C2M' = carrier to (Mezzanine) module

'M2C' = (Mezzanine) module to carrier

J1-52

pins J1-57, J1-59
pins J1-56, J1-58

pins J1-63, J1-65
pins J1-62, J1-64

pins J1-69, J1-71
pins J1-68, J1-70

pins J5-A10, J5-A11
pins J5-A30, J5-A31

pins J5-A6, J5-A7
pins J5-A26, J5-A27

pins J5-A2, J5-A3
pins J5-A22, J5-A23

pins J5-C6, J5-C7
pins J5-C2, J5-C3

B229_RX3_P, B229_RX3_N
B229_TX3_P, B229_TX3_N

B229_RX2_P, B229_RX2_N
B229_TX2_P, B229_TX2_N

B229_RX1_P, B229_RX1_N
B229_TX1_P, B229_TX1_N

B229_RX0_P, B229_RX0_N
B229_TX0_P, B229_TX0_N

pins J1-27, J1-29
pins J1-26, J1-28

pins J1-33, J1-35
pins J1-32, J1-34

pins J1-39, J1-41
pins J1-38, J1-40

pins J1-45, J1-47
pins J1-44, J1-46

pins J5-B12, J5-B13
pins J5-B32, J5-B33

pins J5-B16, J5-B17
pins J5-B36, J5-B37

pins J5-A18, J5-A19
pins J5-A38, J5-A39

pins J5-A14, J5-A15
pins J5-A34, J5-A35

B230_RX1_P, B230_RX1_N
B230_TX1_P, B230_TX1_N

B230_RX0_P, B230_RX0_N
B230_TX0_P, B230_TX0_N

pins J1-15, J1-17
pins J1-14, J1-16

pins J1-21, J1-23
pins J1-20, J1-22

pins J5-B4, J5-B5
pins J5-B24, J5-B25

pins J5-B8, J5-B9
pins J5-B28, J5-B29

Table 4: FMC connector pin-outs of available MGT lanes of the MPSoC

The FMC connector provides pins for reference clock output to the Mezzanine module and clock input to PL banks of the MPSoC:

Clock Signal Schematic Name	FMC Connector Pins	Direction	Clock Source	Notes
B228_CLK0	J5-D4 / J5-D5	in	FMC Connector J5	Extern MGT clock
B229_CLK0	J5-B20 / J5-B21	in	FMC Connector J5	Extern MGT clock
FMCCLK2	J5-K4 / J5-K5	out	Carrier Board PLL SI5338A U35, CLK2	Clock signal to Mezzanine module
FMCCLK3	J5-J2 / J5-J3	out	Carrier Board PLL SI5338A U35, CLK3	Clock signal to Mezzanine module
B64_L14_P / B64_L14_N	J5-H4 / J5-H5	in	FMC Connector J5	Extern LVDS clock to PL bank
B48_L6_P / B48_L6_N	J5-G2 / J5-G3	in	FMC Connector J5	Extern LVDS clock to PL bank

Table 5: FMC connector pin-outs for reference clock output

The FMC connector provides further interfaces like JTAG and I²C interfaces:

Interfaces	I/O Signal Count	Pin schematic Names / FMC Pins	Connected to	Notes
JTAG	5	FMC_TCK, pin J5-D29 FMC_TMS, pin J5-D33 FMC_TDI, pin J5-D30 FMC_TDO, pin J5- D31	SC CPLD U17, bank 1	VCCIO: 3V3SB TRST_L, pin J5-D34 pulled-up to 3V3_PER
I²C	2	FMC_SCL, pin J5-C30 FMC_SDA, pin J5-C31	I²C Switch U16	I²C-lines pulled-up to 3V3_PER
Control Lines	4	FMC_PRSNT_M2C, pin J5-H2	I²C I/O Expander U38	'PG' = 'Power Good'-signal 'C2M' = carrier to (Mezzanine) module 'M2C' = (Mezzanine) module to carrier
		FMC_PG_C2M, pin J5-D1 (3V3_PER pull-up)	SC CPLD U39, bank 0
		FMC_PG_M2C, pin J5-F1 (3V3_PER pull-up)	I²C I/O Expander U38
		FMC_CLK_DIR, pin J5-B1 (pulled-down to GND)	SC CPLD U17, bank 1

Table 6: FMC connector pin-outs of available interfaces to the System Controller CPLD

Several VCCIO voltages are available on the FMC connector to operate the I/O's on different voltage levels:

VCCIO Schematic Name	FMC Connector J5 Pins	Notes
12V	C35/C37	extern 12V power supply
3V3_PER	D32/D36/D38/D40/C39	3.3V peripheral supply voltage
FMC_VADJ	H40/G39/F40/E39	adjustable FMC VCCIO voltage, supplied by DC-DC converter U8

Table 7: Available VCCIO voltages on FMC connector

MIO Bank Interfaces

The TEBF0808 carrier board provides several interfaces, which are configured on the MIO banks 500 .. 503 of the Zynq Ultrascale+ MPSoC.

Following table contains the assignment of the MIO pins to the configured interfaces:

MIO	Configured as	System Controller CPLD	Notes
0..12	Dual QSPI	-	Dual Flash Memory on TE0808 / TE0803 SoM; Bootable
13..23	SD0: eMMC	-	eMMC Memory U2; Bootable
24, 25	-	CPLD (U39) MUXED	-
26..29	-	CPLD (U17 MUXED	Bootable JTAG (PJTAG0)
30	force reboot after FSBL-PLL config for PCIe	CPLD (U39) MUXED	-
31	PCIe reset	CPLD (U39) MUXED	-
32	-	CPLD (U39) MUXED	-
33	-	CPLD (U39) MUXED	-
34..37	-	CPLD (U39) MUXED	-
38, 39	I2C0	-	-
40	forwarded to PWRLED_P / LED_P	CPLD (U39) MUXED	-
41	-	-	-
42, 43	UART0	CPLD (U39) MUXED	-
44	SD_WP to FPGA	CPLD (U39) MUXED	-
45..51	SD1: SD	-	Bootable MikroSD / MMC Card
52..63	USB0	-	-
64..75	GEM3	-	Ethernet RGMII
76, 77	MDC / MDIO	-	Ethernet RGMII

Table 8: MIO Assignment

Following interfaces are provided by the MIO bank of the Zynq Ultrascale+ MPSoC:

4x USB3.0 Superspeed ports (downward compatible to USB2.0 Highspeed)
SDIO port with muxed MikroSD and MMC Card socket
Gigabit Ethernet interface connected per RGMII
eMMC interface
Master I²C interface to on-board peripherals

The block-diagram below visualizes the interfaces of the MIO bank at the Zynq Ultrascale+ MPSoC and their associated on-board peripherals.

Image Added

Figure 4: TEBF0808 MIO Interfaces

PS GT Bank Interfaces

The PS GT Bank 505 provides beside the USB3.0 Lane also following interfaces:

SATA (PS GT bank, MGT2 Lane)
DisplayPort (PS GT bank, MGT3 Lane, only TX-pair routed)
PCI Express (PS GT bank, MGT0 Lane)

Function	MGT Lane	Schematic Names / B2B pins	Required Ref Clock	Clock Source	Comment
PCIe	PS 0	PCI_TX_N, pin J2-67 PCI_TX_P, pin J2-69 PCI_RX_N, pin J2-70 PCI_RX_P, pin J2-72	100 MHz	clock signal of SoM's prog. PLL	single lane PCIe connector clock signal routed on carrier board to PCIe connector J1
USB3	PS 1	USB3_TXUP_N, pin J2-61 USB3_TXUP_P, pin J2-63 USB3_RXUP_N, pin J2-64 USB3_RXUP_P, pin J2-66	100 MHz	clock signal of SoM's prog. PLL	clock signal routed on-module, Optional (not equipped) 100 MHz osci. U6 is possible (Configurable on Zynq PS).
SATA	PS 2	SATA_TX_N, pin J2-55 SATA_TX_P, pin J2-57 SATA_RX_N, pin J2-58 SATA_RX_P, pin J2-60	150 MHz	On-board oscillator U23	optional: clock signal of SoM's prog. PLL
DP.0	PS 3	DP0_TX_N, pin J2-49 DP0_TX_P, pin J2-51	27 MHz	clock signal of SoM's prog. PLL	DisplayPort GT SERDES clock signal, routed on-module to MGT bank

Table 9: PS GT Lane Assignment

Following block diagram shows the wiring of the MGT Lanes of the PS GT bank 505 to the particular high speed data interfaces:

Image Added

Figure 5: TEBF0808 PS GT Bank 505 Interface

Follwowing table contains a brief description of the control and status signals of PCIe interface:

Signal Schematic Name	FPGA Direction	Description	Logic
WAKE	Input	Link reactivation	Low active
PERST	Input	PCI Express reset input	Low active
PRSNT1	Input	Reference pin for PCIe card lane size	-
PRSNT2	Input	PCI Express ×1 cards	connect to PRSNT1
PRSNT3	Input	PCI Express ×4 cards	connect to PRSNT1
PRSNT4	Input	PCI Express ×8 cards	connect to PRSNT1
PRSNT5	Input	PCI Express ×16 cards	connect to PRSNT1
PCIE_I²C	BiDir	2-wire PCIE System Management Bus	-

Table 10: Description of MGT Connectors Control and Status Signals

MGT Interfaces SFP+ and FireFly

The TEBF0808 carrier board provides the high speed MGT interface connectors "SFP+" (Enhanced small form-factor pluggable) and Samtec "FireFly". This connectors are capable of data transmission rates up to 10 Gbit/s with SFP+ and 28 Gbit/s with FireFly.

Function

MGT Lane

Schematic Names / B2B pins

Required Ref Clock

Clock Source

Comment

FireFly

MGT Lanes 0..3

B128_RX3_N, B128_RX3_P, pins J2-28, J2-30
B128_TX3_N, B128_TX3_P, pins J2-25, J2-27

B128_RX2_N, B128_RX2_P, pins J2-34, J2-36
B128_TX2_N, B128_TX2_P, pins J2-31, J2-33

B128_RX1_N, B128_RX1_P, pins J2-40, J2-42
B128_TX1_N, B128_TX1_P, pins J2-37, J2-39

B128_RX0_N, B128_RX0_P, pins J2-46, J2-48
B128_TX0_N, B128_TX0_P, pins J2-43, J2-45

...

Several VCCIO voltages are available on the FMC connector to operate the I/O's on different voltage levels:

...

Table 7: Available VCCIO voltages on FMC connector

MIO Bank Interfaces

The TEBF0808 carrier board provides several interfaces, which are configured on the MIO banks 500 .. 503 of the Zynq Ultrascale+ MPSoC.

Following table contains the assignment of the MIO pins to the configured interfaces:

...

Following interfaces are provided by the MIO bank of the Zynq Ultrascale+ MPSoC:

4x USB3.0 Superspeed ports (downward compatible to USB2.0 Highspeed)
SDIO port with muxed MikroSD and MMC Card socket
Gigabit Ethernet interface connected per RGMII
eMMC interface
Master I²C interface to on-board peripherals

The block-diagram below visualizes the interfaces of the MIO bank at the Zynq Ultrascale+ MPSoC and their associated on-board peripherals.

Image Removed

Figure 4: TEBF0808 MIO Interfaces

PS GT Bank Interfaces

The PS GT Bank 505 provides beside the USB3.0 Lane also following interfaces:

...

single lane PCIe connector

clock signal routed on carrier board to PCIe connector J1

...

clock signal routed on-module,
also optional (not equipped) 100 MHz osci. U35 configurable

...

optional: clock signal of SoM's prog. PLL

...

DisplayPort GT SERDES clock signal,
routed on-module to MGT bank

Table 9: PS GT Lane Assignment

Following block diagram shows the wiring of the MGT Lanes of the PS GT bank 505 to the particular high speed data interfaces:

Image Removed

...

Follwowing table contains a brief description of the control and status signals of PCIe interface:

...

Table 10: Description of MGT Connectors Control and Status Signals

MGT Interfaces SFP+ and FireFly

The TEBF0808 carrier board provides the high speed MGT interface connectors "SFP+" (Enhanced small form-factor pluggable) and Samtec "FireFly". This connectors are capable of data transmission rates up to 10 Gbit/s with SFP+ and 28 Gbit/s with FireFly.

Function

MGT Lane

Required Ref Clock

Clock Source

Comment

FireFly

MGT Lanes 0..3

-

clock signal of SoM's prog. PLL

clock signal on-module routed to MGT bankon-module routed to MGT bank

SFP

MGT Lane 2

B230_RX2_P, pin J1-9
B230_RX2_N, pin J1-11

B230_TX2_P, pin J1-8
B230_TX2_N, pin J1-10

SFP

MGT Lane 2

125 / 156.25 MHz

clock signal of SoM's prog. PLL

clock signal routed on carrier board to MGT bank

SFP

MGT Lane 3

B230_RX3_P, pin J1-3
B230_RX3_N, pin J1-5

B230_TX3_P, pin J1-2
B230_TX3_N, pin J1-4

125 / 156.25 MHz

clock signal of SoM's prog. PLL

clock signal routed on carrier board to MGT bank

...

PMOD	Interface	Connected to	Notes
P1	I²C	8-channel I²C Switch U27	Accessible on MPSoC's I²C interface through I²C switch U27
P2	GPIO	HP Bank of MPSoC (4 I/O's, B65_T0 ... B65_T3), System Controller CPLD U17 (4 I/O's, EX_IO1 ... EX_IO4)	Voltage translation via IC U33 with direction control, only singled-ended signaling possible	P2	I²C	8-channel I²C Switch U27	only singled-ended signaling possibleAccessible on MPSoC's I²C interface through I²C switch U27
P3	I²C	8-channel I²C Switch U27	Accessible on MPSoC's I²C interface through I²C switch U27

...

The System Controller CPLDs will be programmed by the XMOD-Header J28 in a cascaded JTAG chain as visualized in Figure 89. To program the System Controller CPLDs, the JTAG interface of these devices have to be activated by DIP-switch S4-3.
The 4 GPIO/UART pins (XMOD1_A/B/E/G) of the XMOD-Header J28 are routed to the System Controller CPLD U17.

...

Further JTAG interfaces of the TEBF0808 carrier board are the ARM JTAG 20-pin IDC connector J30 and on the FMC Connector J5. This JTAG interfaces are connected to the System Controller CPLD U17, hence the logical processing and forwarding of the JTAG signals depend on the SC CPLD firmware. The documentation of the firmware of the SC CPLD U17 contains detailed information on this matter.

On-board Peripherals

System Controller

...

CPLDs

The TEBF0808 is equipped with two System Controller CPLDs - Lattice Semiconductor LCMXO2-1200HC (MachXO2 Product Family) - with the schematic designators U17 and U39.

...

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

Both Sytem System Controller CPLDs are connected to the Zynq Ultrascale+ MPSoC through MIO, PL IO-bank pins and I²C interface. The CPLDs are connected with each other through the IO pins SC_IO0 ... SC_IO8.

...

Clock Source	Schematic Name	Frequency	Clock Input Destination
SiTime SiT8008BI oscillator, U10	USB0_RCLK	52.000000 MHz	USB 2.0 transceiver PHY U9, pin 26
SiTime SiT8008BI oscillator, U13	ETH_CLK	25.000000 MHz	Gigabit Ethernet PHY U12, pin 34
SiTime SiT8008BI oscillator, U7	-	25.000000 MHz	Quad PLL clock generator U35, pin 3
DSC1123 oscillator, U23	B505_CLK1	150.0000 MHz	PS GT Bank, dedicated for SATA interface
DSC1123 oscillator, U6 optional, not equipped	B505_CLK0	100.0000 MHz	PS GT Bank, dedicated for USB interface
Silicon Labs 570FBB000290DG, U45 optional, not equipped	B47_L5 (LVDS)	250.MHz	PL Bank clock capable input pins
SiTime SiT8008BI oscillator, U25	CLK_CPLD	2524.576000 MHz	System Controller CPLD U35, pin 128

...

I²C Slave Devices connected to MPSoC I²C Interface	I²C Switch Position	I²C Slave Address	Schematic Names of I²C Bus Lines
8-channel I²C switch U16	-	0x73	I2C_SDA / I2C_SCL
8-channel I²C switch U27	-	0x77	I2C_SDA / I2C_SCL
SC CPLD U39, bank 2, pins 52 (SDA), 50 (SCL)	-	User programmable	I2C_SDA / I2C_SCL
I²C Slave Devices connected to 8-channel I²C Switch U16	I²C Switch Position	I²C Slave Address	Schematic Names of I²C Bus Lines
On-board Quad programmable PLL clock generator U35 Si5338	0	0x70	MCLK_SDA / MCLK_SCL
8-bit I²C IO Expander U44	1	0x26	SFP_SDA / SFP_SCL
PCIe Connector J1	2	module dependent	PCIE_SDA / PCIE_SCL
SFP+ Connector J14A	3	module dependent	SFP1_SDA / SFP1_SCL
SFP+ Connector J14B	4	module dependent	SFP2_SDA / SFP2_SCL
Configuration EEPROM U24U42	5	0x54	MEM_SDA / MEM_SCL
Configuration EEPROM U36	5	0x52	MEM_SDA / MEM_SCL
Configuration EEPROM U41	5	0x51	MEM_SDA / MEM_SCL
Configuration EEPROM U22	5	0x50	MEM_SDA / MEM_SCL
8-bit I²C IO Expander U38	5	0x27	MEM_SDA / MEM_SCL
FMC Connector J5	6	module dependent	FMC_SDA / FMC_SCL
USB3.0 Hub configuration EEPROM U5	7	0x51	USBH_SDA / USBH_SCL
USB3.0 Hub	7	0x60	USBH_SDA / USBH_SCL
I²C Slave Devices connected to 8-channel I²C Switch U27	I²C Switch Position	I²C Slave Address	Schematic Names of I²C Bus Lines
PMOD Connector P1	0	module dependent	PMOD_SDA / PMOD_SCL
24-bit Audio Codec U3	1	0x38	A_I2C_SDA / A_I2C_SCL
FireFly Connector J15	2	module dependent	FFA_SDA / FFA_SCL
FireFly Connector J22	3	module dependent	FFB_SDA / FFB_SCL
On-module Quad programmable PLL clock generator Si5345 (TE0808)	4	0x69	PLL_SDA / PLL_SCL
SC CPLD U17, bank 3, pins 13 (SDA), 14 (SCL)	5	User programmable	SC_SDA / SC_SCL
8-bit I²C IO Expander U34	6	0x24	FF_E_SDA / FF_E_SCL
PMOD Connector P3	7	module dependent	EXT_SDA / EXT_SCL

...

EEPROM Modell	Schematic Designator	Memory Density	Purpose
24LC128-I/ST	U24U30	128 Kbit	user
24AA025E48T-I/OT	U36	2 Kbit	user
24AA025E48T-I/OT	U41	2 Kbit	user
24AA025E48T-I/OT	U42	2 Kbit	user
24LC128-I/ST	U5	128 Kbit	USB3.0 Hub U4 configuration memory

Table 21: On-board configuration EEPROMs overview

4-port USB3.0 Hub

On the carrier board there are up to 4 USB3.0 Super Speed ports available, which are also downward compatible to USB2.0 High Speed ports. The USB3.0 ports are provided by Cypress Semiconductor CYUSB3324 4-port USB3.0 Hub controller U4. The pin-strap configuration option of the USB3.0 Hub is disabled, so this controller gets the configuration data and parameter from the configuration EEPROM U5. The I²C interface of the EEPROM and the controller is also accessible by the Zynq Ultrascale+ MPSoC through I²C switch U16.

On the Upstream-side, this controller is connected to the MGT1 lane of MPSoC's PS GT bank to establish the USB3.0 data lane. For the USB2.0 interface, the controller is connected to the on-board USB2.0 PHY U9. The USB2.0 PHY is connected per ULPI interface (MIO pins 52..63) to MPSoC's MIO bank.

The USB3.0 Hub controller has also an ARM Cortex-M0 controller integrated, refer to the data sheet for further features and programmable options.

CAN FD Transceiver

On-board CAN FD (Flexible Data Rate) transceiver is provided by Texas Instruments TCAN337. This controller is the physical layer of the CAN interface and is specified for data rates up to 1 Mbps. The controller has many protection features included to ensure CAN network robustness and to eliminate the need for additional protection circuits. Refer to the data sheet of this transceiver for more details and specifications.

The transceiver is connected to System Controller CPLD U17, means it works on this interface with 3.3V VCCIO. The logical signal processing of the CAN interface depends on the current firmware ot the SC CPLD U17.

eMMC Memory

The TEBF0808 carrier board is equipped with embedded MMC memory connected to the PS MIO bank (MIO13 ... MIO23) of the Zynq Ultrascale+ MPSoC. The memory is provided by MTFC4GACAJCN-4M from Micron Technology. It has a memory density of 32 Gbit (4 GByte) and is sectored into 8 banks a 4 Gbit.

24-bit Audio Codec

For high resolution digital audio signal processing, the TEBF0808 carrier board is equipped with the Analog Devices 24-bit Audio Codec chip ADAU1761 with the schematic designator U3. The Audio Codec chip is connected to the Intel High Defintion Audio (Intel HDA) compatible 9-pin header J9 with single-ended signaling for analog stereo audio signal input and output. It supports also MIC / Jack detect. Its I²C control interface is accessible by the Zynq Ultrascale+ MPSoC through I²C switch U27.

The 24-bit Audio Codec provides numerous features and is also fully programmable with its dedicated graphical tool from the manufacturer. Refer to the data sheet of this chip for more detail information and specifications.

SDIO Port Expander

Due to the different signaling voltage levels of the MicroSD and MMC Card interfaces (3.3V) and the PS MIO bank of the Zynq Ultrascale+ MPSoC (1.8V), there is voltage-translation necessary, which is fullfilled by the SDIO port expander Texas Instruments TXS02612, U15. This IC also muxes the MikroSD and the MMC Card sockets to the SDIO port of the MPSoC, which is controlled by the signal 'SEL_SD' of the System Controller CPLD U39. The SC CPLD U39 also controls the load switches to enable the card sockets J16 and J27 and to report the card detect signal both of the sockets to the MPSoC (see schematic).

DIP-Switches

There are two 4 bit DIP Switches on the TEBF0808 carrier board to configure options and set parameters. The table below describes the functionalities of the particular switches:

...

-I/OT	U42	2 Kbit	user
24LC128-I/ST	U5	128 Kbit	USB3.0 Hub U4 configuration memory

Table 21: On-board configuration EEPROMs overview

4-port USB3.0 Hub

On the carrier board there are up to 4 USB3.0 Super Speed ports available, which are also downward compatible to USB2.0 High Speed ports. The USB3.0 ports are provided by Cypress Semiconductor CYUSB3324 4-port USB3.0 Hub controller U4. The pin-strap configuration option of the USB3.0 Hub is disabled, so this controller gets the configuration data and parameter from the configuration EEPROM U5. The I²C interface of the EEPROM and the controller is also accessible by the Zynq Ultrascale+ MPSoC through I²C switch U16.

On the Upstream-side, this controller is connected to the MGT1 lane of MPSoC's PS GT bank to establish the USB3.0 data lane. For the USB2.0 interface, the controller is connected to the on-board USB2.0 PHY U9. The USB2.0 PHY is connected per ULPI interface (MIO pins 52..63) to MPSoC's MIO bank.

The USB3.0 Hub controller has also an ARM Cortex-M0 controller integrated, refer to the data sheet for further features and programmable options.

CAN FD Transceiver

On-board CAN FD (Flexible Data Rate) transceiver is provided by Texas Instruments TCAN337. This controller is the physical layer of the CAN interface and is specified for data rates up to 1 Mbps. The controller has many protection features included to ensure CAN network robustness and to eliminate the need for additional protection circuits. Refer to the data sheet of this transceiver for more details and specifications.

The transceiver is connected to System Controller CPLD U17, means it works on this interface with 3.3V VCCIO. The logical signal processing of the CAN interface depends on the current firmware ot the SC CPLD U17.

eMMC Memory

The TEBF0808 carrier board is equipped with embedded MMC memory connected to the PS MIO bank (MIO13 ... MIO23) of the Zynq Ultrascale+ MPSoC. The memory is provided by MTFC4GACAJCN-4M from Micron Technology. It has a memory density of 32 Gbit (4 GByte) and is sectored into 8 banks a 4 Gbit.

24-bit Audio Codec

For high resolution digital audio signal processing, the TEBF0808 carrier board is equipped with the Analog Devices 24-bit Audio Codec chip ADAU1761 with the schematic designator U3. The Audio Codec chip is connected to the Intel High Defintion Audio (Intel HDA) compatible 9-pin header J9 with single-ended signaling for analog stereo audio signal input and output. It supports also MIC / Jack detect. Its I²C control interface is accessible by the Zynq Ultrascale+ MPSoC through I²C switch U27.

The 24-bit Audio Codec provides numerous features and is also fully programmable with its dedicated graphical tool from the manufacturer. Refer to the data sheet of this chip for more detail information and specifications.

SDIO Port Expander

Due to the different signaling voltage levels of the MicroSD and MMC Card interfaces (3.3V) and the PS MIO bank of the Zynq Ultrascale+ MPSoC (1.8V), there is voltage-translation necessary, which is fullfilled by the SDIO port expander Texas Instruments TXS02612, U15. This IC also muxes the MikroSD and the MMC Card sockets to the SDIO port of the MPSoC, which is controlled by the signal 'SEL_SD' of the System Controller CPLD U39. The SC CPLD U39 also controls the load switches to enable the card sockets J16 and J27 and to report the card detect signal both of the sockets to the MPSoC (see schematic).

DIP-Switches

There are two 4-bit DIP-witches present on the TEBF0808 carrier board to configure options and set parameters. The following section describes the functionalities of the particular switches.

DIP-switch S4

Table below describes the functionalities of the switches of DIP-switch S4 at their single positions:

DIP-switch S4	Position ON	Position OFF	Notes
S4-1	PUDC_B is Low	PUDC_B is HIGH	Internal pull-up resistors during configuration are enabled at ON-position, means I/O's are 3-stated until configuration of the FPGA completes.
S4-2	x	x	not connected
S4-3	SC CPLDs' JTAG enabled	SC CPLDs' JTAG disabled	JTAG interface is enabled on both SC CPLDs, as this CPLDs are configured in a casdaced JTAG chain.
S4-4	DC-DC converter U18 (5V) enabled	DC-DC converter U18 (5V) not manually enabled	In OFF-position, the DC-DC-converter will be still enabled by the Enable-signal ('5V_EN') of SC CDPD U39 (wired-OR circuit).

Table 22: DIP-switch S4 functionality description

DIP-switch S5

DIP-switch S5 located close to PWR push-button is connected to the two System Controller CPLDs, its functionalities depend on the current firmware of the CPLDs.

The DIP-switch is connected to SC CPLD U17 and U39 as fellows:

DIP-switch S5	Signal Schematic Name	Connected to	Functionality	CPLD Documentation
S5-1	SC_SW1	SC CPLD U39, pin 133	set 2-bit code for boot mode selection	TEBF0808 Slave CPLD Section: Boot Mode
S5-2	SC_SW2	SC CPLD U39, pin 138	set 2-bit code for boot mode selection	TEBF0808 Slave CPLD Section: Boot Mode
S5-3	SC_SW3	SC CPLD U17, pin 6	user defined	TEBF0808 Master CPLD
S5-4	SC_SW4	SC CPLD U17, pin 5	set FMC_VADJ: 1.8V at ON-position, 1.2V at OFF-position	TEBF0808 Master CPLD

Table 23: DIP-switch S5 connection to SC CPLDs

The boot mode of the mounted Ultrascale+ Zynq MPSoC module will be set in current SC CPLD U39 firmware version as described in the table below:

S5-1	S5-2	Description

...

DIP-switch S5 located close to PWR push-button is connected to the two System Controller CPLDs, its functionalities depend on the current firmware of the CPLDs.

The switches of this DIP-switch have to be set in bit-patterns to set a parameter like boot mode or FMC_VADJ value:

ONxxx

S5-1	S5-2	S5-3	S5-4	Description
ON
ON	ON	Default, boot from SD/eMMC, 1.8V FMC VADJ	ON	ON	x	x	Boot from microSD , SD or SPI Flash if no SD is detected
OFF	ON	x		Boot from eMMC
ON	OFF	x		Boot mode PJTAG0
OFF	OFF	x		Boot mode main JTAG
x	x	x	ON	FMC VADJ = 1.8V
x	x	x	OFF	FMC VADJ = 1.2V

Table 23: DIP-switch S4 functionality descriptionS5 boot mode selection

On-board LEDs

The TEBF0808 carrier board is equipped with several LED to signal current states and activities. The functionality of the LEDs D4 ... D7 depends on the current firmware of the SC CPLDs U17 and U39.

...

Figure 12: Power Distribution Diagram

Note
Current rating of Samtec Razor Beam™ LSHM Samtec Razor Beam LP Terminal/Socket Strip ST5/SS5 B2B connectors is 21.0A 5 A per pin (2 adjacent pins powered1 pin powered per row).

Power-On Sequence Diagram

...

Following diagram visualizes the connection of the DC-DC converter control signals ('Enable', 'Power-Good') with System Controller CPLD U39, which enables the particular on-board voltages.

Figure 13: Power-On Sequence Utilizing DCDC Converter Control Signals

Note

As shown in Figure 1213, the DIP switch S4-4 has to be closed if using only 12V single power supply through 12V power jack J25, otherwise the 5V voltage level will not be enabled to generate the 3V3SB voltage to power up the SC CPLD U39 and starting the power-on sequence.
By using an ATX-24 power connector on J20, there is usually also a 5V supply voltage provided, hence the DIP switch S4-4 is not relevant in this case of power supply.

...

J22PER 1, 10

Peripheral Designator	VCC / VCCIO	Direction	Pins	Notes
J23	3.3VSB	Out	Pin 1	PC Compatible BEEPER
J11	12V	Out	Pin A2, A3, B1, B2, B3	PCIe Connector
J11	3.3V_PCI	Out	Pin A9, A10, B8, B10	-
J29	5V	Out	Pin 5	CAN-Bus Header
J13	DP_TX_PWR	Out	Pin 20	Display-Port Connector
J14A	3.3V_PCI	Out	Pin T15, T16	SFP+ 2x1 Connector
J14B	3.3V_PCI	Out	Pin L15, L16	SFP+ 2x1 Connector
J15	3.3V_PER	Out	Pin 1, 10	FireFly Connector
J22	3.3V_PER	Out	Pin 1, 10	FireFly Connector	Connector
J7A	VBUS4	Out	Pin U1	USB3.0 Connector
J7B	VBUS3	Out	Pin U10	USB3.0 Connector
J8	VBUS1	Out	Pin 19	USB3.0 Header
J8	VBUS2	Out	Pin 1	-
J16	3.3V_SD_A	Out	Pin 4	MicroSD Card Socket
J27	3.3V_	SD_B	Out	Pin	FireFly Connector
J7A	VBUS4	Out	Pin U1	USB3.0 Connector
J7B	VBUS3	Out	Pin U10	USB3.0 Connector
J8	VBUS1	Out	Pin 19	USB3.0 Header
J8	VBUS2	Out	Pin 1	-
J16	3.3V_SD_A	Out	Pin 4	MicroSD Card Socket
J27	3.3V_SD_B	Out	Pin 4	MMC Card Socket
B1	VBATT	In	Pin +	Battery Holder

Table 32: Power pin description of Peripherals' Connector

B2B connectors

...

4	MMC Card Socket
B1	VBATT	In	Pin +	Battery Holder

Table 32: Power pin description of Peripherals' Connector

B2B connectors

Include Page

	5.2 x 7.6 UltraSoM+ ST5 and SS5 B2B Connectors
	5.2 x 7.6 UltraSoM+ ST5 and SS5 B2B Connectors

Technical Specifications

Absolute Maximum Ratings

Parameter	Min	Max	Unit	Notes / Reference Document
Power supply voltage (12V nominal)	11.4	12.6	V	ANSI/VITA 57.1 FPGA Mezzanine Card (FMC) standard
Battery Voltage VBATT	-0.5	2	V	Xilinx DS925 data sheet
Voltage on pins of PMOD P2	-0.5	3.75	V	MachXO2 Family Data Sheet
Storage temperature (ambient)	-55	85	°C	Marvell 88E1512 datasheet

Table 33: Board absolute maximum ratings.

Note
Assembly variants for higher storage temperature range are available on request.

Recommended Operating Conditions

...

Technical Specifications

...

Parameter Min Max Unit Notes / Reference Document
Power supply voltage (12V nominal) 11.4 12.6 V ANSI/VITA 57.1 FPGA Mezzanine Card (FMC) standard
Battery Voltage VBATT -0.5 2 V Xilinx DS925 data sheet
Voltage on pins of PMOD P2 -0.5 3.75 V MachXO2 Family Data Sheet
Storage temperature (ambient)
-55
85
°C
Marvell 88E1512 datasheet
Table 33: Board absolute maximum ratings.
Note
Assembly variants for higher storage temperature range are available on request.

Recommended Operating Conditions

...

1.2	1.5	V	Xilinx DS925 data sheet
Voltage on pins PMOD P2	3.135	3.6	V	MachXO2 Family Data Sheet

Table 34: Board recommended operating conditions.

Note
Please check TRM TE0808 / TE0803 and Xilinx datasheet DS925 for complete list of absolute maximum and recommended operating ratings for the mounted UltraSoM+.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Extended grade: 0°C to +85°C.

The carrier board itself is capable to be operated at industrial grade temperature range.

Please check the operating temperature range of the mounted UltraSOM+ modules, which determine the relevant operating temperature range of the overall system.

Physical Dimensions

Module size: 170 mm × 170 mm. Please download the assembly diagram for exact numbers
Mating height with standard connectors: 5 mm
PCB thickness: 1.844 mm ± 10%
Highest part on PCB: approx. 32 mm. Please download the step model for exact numbers

All dimensions are given in millimeters.

Image Added Image Added

Figure 14: Board physical dimensions drawing.

Revision History

Hardware Revision History

Date	Revision	Notes	Link to PCN	Documentation Link
-	04	Current available board revision	-	TEBF0808-04
-	03	Second production release	-	TEBF0808-03
-	02	First production release	-	TEBF0808-02
-	01	Prototype	-	-

Table 35: Board hardware revision history.

Hardware revision number is written on the PCB board together with the module model number separated by the dash.

Image Added

Figure 15: Board hardware revision number.

Document Change History

Date

Revision

Contributors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

Page info

infoType	Current version
dateFormat	yyyy-MM-dd
prefix	v.
type	Flat

Page info

infoType	Modified by
dateFormat	yyyy-MM-dd
type	Flat

System Controller links fixed

2019-09-03

v.96

Thomas Steffens

correction EEPROM Designator
correction typ U25 CLK

2018-07-02

v.89

Martin Rohrmüller

Typo

2018-05-31

v.88

John Hartfiel

Typo correction Table 13
Typo correction Table 9

2017-11-15

v.86

Ali Naseri

DIP-switches section revised and updated

2017-11-13

v.82

Ali Naseri

updated B2B connector max. current rating
per pin

2017-11-13

v.80

John Hartfiel

rework B2B section

2017-10-19

v.79

Ali Naseri

added additionally MGT lanes information

2017-10-18

v.75

Table 34: Board recommended operating conditions.

Note
Please check TRM TE0808 / TE0803 and Xilinx datasheet DS925 for complete list of absolute maximum and recommended operating ratings for the mounted UltraSoM+.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Extended grade: 0°C to +85°C.

The carrier board itself is capable to be operated at industrial grade temperature range.

Please check the operating temperature range of the mounted UltraSOM+ modules, which determine the relevant operating temperature range of the overall system.

Physical Dimensions

Module size: 170 mm × 170 mm. Please download the assembly diagram for exact numbers
Mating height with standard connectors: 5 mm
PCB thickness: 1.844 mm ± 10%
Highest part on PCB: approx. 32 mm. Please download the step model for exact numbers

All dimensions are given in millimeters.

Image Removed Image Removed

Figure 14: Board physical dimensions drawing.

Revision History

Hardware Revision History

...

Notes

...

Hardware revision number is written on the PCB board together with the module model number separated by the dash.

Image Removed

Figure 15: Board hardware revision number.

Document Change History

yyyy-MM-dd

Date

Revision

Contributors

Description

Page info

modified-date

dateFormat

Ali Naseri

added Power Rails section

2017-08-29

v.70

John Hartfiel

update document change history
published

2017-08-28

v.69

Ali Naseri

Initial document

--

all

Page info

infoType	Modified users
type	Flat
showVersions	false

--

Table 36: Document change history.

...

Trenz Electronic Documentation

Page History

Versions Compared

Old Version 75

New Version Current

Key

MIO Bank Interfaces

PS GT Bank Interfaces

MGT Interfaces SFP+ and FireFly

MIO Bank Interfaces

PS GT Bank Interfaces

MGT Interfaces SFP+ and FireFly

On-board Peripherals

System Controller

CPLDs

4-port USB3.0 Hub

CAN FD Transceiver

eMMC Memory

24-bit Audio Codec

SDIO Port Expander

DIP-Switches

4-port USB3.0 Hub

CAN FD Transceiver

eMMC Memory

24-bit Audio Codec

SDIO Port Expander

DIP-Switches

On-board LEDs

Power-On Sequence Diagram

B2B connectors

B2B connectors

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Technical Specifications

Recommended Operating Conditions

Operating Temperature Ranges

Physical Dimensions

Revision History

Hardware Revision History

Document Change History

Operating Temperature Ranges

Physical Dimensions

Revision History

Hardware Revision History

Document Change History