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The Trenz Electronic teCORE™ IP "AXI4-Stream TLAST ControlEFUSE_USER" is designed to be interfaced to two AXI4-Stream interfaces. This core does add generated TLAST pulses at determined intervalsprovide simple access to Xilinx EFUSE_USR Primitive from Vivado IPI This IP Core is only a IP Wrapper around the primitive.

Overview

Feature Summary

• AXI4-Stream slave for inputWrapper for EFUSE_USR Primitive
• AXI4-Stream master for output
• Selectable input/output data width 8-256 bits
• Fixed or variable TLAST repeat period
• or
• Direct 32 bit output port

Applications

• Data acquisition

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The following sections detail the performance of the core.

Maximum Frequencies

The maximum achievable clock frequency may vary. It is expected that this IP core can run at 250MHz in any 7-Series FPGAMaximum Frequency is not applicable as this core provide only static output values.

Latency

There is no added latencyLatency is not applicable as this core provide only static output values.

Throughput

There is no degradation of the throughput introduced by this IP CoreThroughput is not applicable as this core provide only static output values.

Resource Utilization

This core does not use any dedicated I/O or CLK resources.

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Use Cases

The EFUSE_USR IP Core can be used with Zynq PS or MicroBlaze or MicroBlaze MCS.

MicroBlaze MCS

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EFUSE value can be read from MCS Input port.

MicroBlaze AXI4-Stream

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EFUSE value can be read using MicroBlaze special instructions.