Introduction
The Trenz Electronic teCORE™ IP "AXI4-Stream TLAST Control" is designed to be interfaced to two AXI4-Stream interfaces. This core does add generated TLAST pulses at determined intervals.
| teCORE™ IP Facts Table | |
|---|---|
| Supported Device Family | Zynq -7000, 7 Series |
| Supported User Interfaces | AXI4-Stream |
| Resources | 1 DSP48 |
| Provided with Core | |
| Documentation | Product Guide |
| Design Files | VHDL Source Code |
| Tested Design Flows | |
| Design Entry | Vivado Design Suite, IP Integrator |
| Simulation | Vivado Simulator |
| Synthesis | Vivado Synthesis |
| Support | |
| Provided by Trenz Electronic GmbH | |
Overview
Feature Summary
- AXI4-Stream slave for input
- AXI4-Stream master for output
- Selectable input/output data width 8-256 bits
- Fixed or variable TLAST repeat period
Applications
- Data acquisition
Licensing
This Trenz Electronic teCORE™ is licensed under MIT License.
Product Specification
Performance
The following sections detail the performance of the core.
Maximum Frequencies
The maximum achievable clock frequency may vary. It is expected that this IP core can run at 250MHz in any 7-Series FPGA.
Latency
There is no added latency.
Throughput
There is no degradation of the throughput introduced by this IP Core.
Resource Utilization
This core does not use any dedicated I/O or CLK resources.
| Data width | LUTs | FFs | DSP48E1 |
|---|---|---|---|
| 8-256 | tbd | tbd | 1 |
Overview
Content Tools