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- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM"
Template Change history: Date | Version | Changes | Author |
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| 4.2 | | ED |
| 4.1 | | ED |
| 4.0 | - Rework for smaller TRM which can be generated faster
- Reduce Signal Interfaces Pin
- Reduce On Board Periphery
- Reduce Power
- Move Configuration Signals from Overview to own section
| JH |
| 3.12 | - Version History
- changed from list to table
- all
- changed title-alignment for tables from left to center
| ma |
| 3.11 | - update "Recommended Operating Conditions" section
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| 3.1 | - New general notes for temperature range to "Recommended Operating Conditions"
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| 3.02 | - add again fix table of content with workaround to use it for pdf and wiki
- Export Link for key features examples
- Notes for different Types (with and without Main FPGA)
- Export Link for Signals, Interfaces and Pins examples
- Notes for different Types (Modul, Modul Hybrid, Evalboard, Carrier)
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| 3.01 | - remove fix table of content and page layout ( split page layout make trouble with pdf export)
- changed and add note to signal and interfaces, to on board periphery section
- ...(not finished)
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| 3.00 | - → separation of Carrier/Module and evaluation kit TRM
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| 2.15 | - add excerpt macro to key features
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| 2.14 | - add fix table of content
- add table size as macro
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Important General Note:
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Note for Download Link of the Scroll ignore macro: |
Overview
The Trenz Electronic TEB2000 carrier board provides functionality for development, evaluation and testing purposes of Trenz 4 x 5 cm SoMs (System on Module).
The carrier board is equipped with a broad range of various components and connectors for different configuration setups and needs. On-module functional components and multipurpose I/Os of the SoM's PL and PS logic are connected via board-to-board connectors to the carrier board components and connectors for easy user access.
See page "4 x 5 SoM Carriers" for more information about the SoM's supported by the TE0703 TEB2000 Carrier Board.
Refer to http://trenz.org/teb2000-info (Links is correct, url should be redirect to Resources Page, but is not) for the latest online version of this manual and other available documentation.
Key Features
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- On Board:
- System Controller (SC) (LCMXO2-1200HC-4TG144I1))
- Mini USB for JTAG and UART connection (FTDI FT2232H), compatible with AMD and other vendor development tools
- Mini USB second UART connection (FTDI FT230XQ)
- SDIO port expander
- 4 x User LEDs
- D1 and , D2 are connected to the SC, their function depends on the firmwareSC (firmware-dependent functionality)
- D3, D4 connected to SC and D3 and D4 are connected to the SC and the 4 x 5 SoM and can be directly controlled by it
- 2 x User push button
- Connected to the SC , the fuction is firmware depend(firmware-dependent functionality)
- Currently used for Hard- and Soft-Reset
- 4 User DIP switches
- Enable/disable update of the SC
- MIO0 (readable accessible signal by SC and SoM)
- 2 "mode" bits
- Interface:
- Trenz 4 x 5 SoM socket
- 3 x Samtec LSHM series high-speed connectors
- Micro SD card connector
- 2 x VG96 backplane connectors assembly option (mounting holes and solder pads)
- Mini or Normal USB for SoM USB-OTG connection 1)
- RJ45 GbE connector
- Power:
- Overvoltage-, undervoltage- and reversed- supply-voltage-protection
- Barrel jack (2.1 mm) for 5V power supply input
- Dimension:
- Notes
1)Depends on assembly variant |
Block Diagram
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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.
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Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name. Example: TE0812 Block Diagram |
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All created DrawIOs should be named according to the Module name: Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD |
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anchor | Figure_OV_BD |
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title-alignment | center |
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title | TExxxx TEB2000 block diagram |
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draw.io Diagram |
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border | truefalse |
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diagramName | TEB2000_OV_BD |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hiddentop |
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diagramDisplayName | |
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lbox | true |
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diagramWidth | 642 |
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height | 902630 |
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revision | 1114 |
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Main Components
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Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
- System Controller (SC) CPLD, U5
- USB-to-JTAG/UART-FTDI, U4, U12
- UART LEVEL Shifter, U8
- SDIO Port Expander, U2
- I²C Repeater, U7
- Power Input Protection, U11
- DCDC, U3
- USB Power Supply Switch, U1
- Reset / Push button, S1, S6 NEU
- 4x Dip Switches, S2
- ULED1 D1 (red), D2 (green)
- FLED1 con to SC PL9A, D3 (red), D4 (green)
- Ethernet jack, J14
- Samtec Razor Beam™ LSHM-150/130 B2B connector, JB1, JB2, JB3
- Footprint for VG96 Connector / VG96 Connector, J1 and J2
- +5V power jack, J13
- microSD Card Socket, J3
- Bank IO Voltages jumper, J5, J8, J9, J10
- Mini USB Type B jack, J4 (FT2232H), J21 (FT230XQ)
- USB Host Connector, either a USB A jack, J6 or a Micro USB, J12
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anchor | Figure_OV_MC |
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title-alignment | center |
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title | TExxxx main components |
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draw.io Diagram |
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border | true |
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diagramName | TEB2000-01_Figure_OV_MC |
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simpleViewer | false |
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width | links | auto |
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tbstyle | top |
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lbox | true |
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diagramWidth | 641 |
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revision | 2 |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
U1, USB Power Supply Switch
U2, SDIO Port Expander
U3, DCDC
U4, U12, USB-to-JTAG/UART-FTDI
U5, System Controller (SC) CPLD
U7, I²C Repeater
U8, UART LEVEL Shifter
U11, Power Input Protection
S1, Push button Reset
S2, 4x Dip Switches
S6, Push button Soft Reset
J1, J2, Footprint for VG96 Connector / VG96 Connector
J3, Socket microSD Card
J4, Mini USB Type B jack (FT2232H)
J5, J8, J9, J10, Jumper Bank IO Voltages
J6, or J12, USB Host Connector, either a USB A jack or a Micro USB
J13, +5V power jack
J14, Ethernet jack
J21, Mini USB Type B jack (FT230XQ)
Dx, U-LED red and green (D1, D2), F-LED red and green (D3, D4)
Initial Delivery State
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anchor | Figure_OV_MC |
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title-alignment | center |
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title | TEB2000 main components |
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draw.io Diagram |
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border | false |
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diagramName | TEB2000-01_Figure_OV_MC |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramDisplayName | |
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lbox | true |
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diagramWidth | 641 |
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height | 814 |
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revision | 5 |
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Image Added |
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- System Controller (SC), U5
- USB-to-JTAG/UART-FTDI, U4
- USB-to-UART-FTDI, U12
- UART Level Shifter, U8
- SDIO Port Expander, U2
- I²C Repeater, U7
- Power Input Protection, U11
- DCDC, U3
- USB Power Supply Switch, U1
- Reset / Push button, S1, S6
- 4x Dip Switch, S2
- LED D1 (red), D2 (green)
- LED D3 (red), D4 (green)
- Ethernet Jack, J14
- Samtec Razor Beam™ LSHM-150/130 B2B connector, JB1, JB2, JB3
- Assembly option for VG96 Connector, J1, J2
- Power Jack, J13
- microSD Card Socket, J3
- Bank IO Voltages jumper, J5, J8, J9, J10
- Mini USB Type B Jack, J4 (FT2232H), J21 (FT230XQ)
- USB Host Connector, J6 (USB A) or J12 (Micro USB)
Initial Delivery State
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Note |
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Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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Scroll Title |
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anchor | Table_OV_IDS |
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title-alignment | center |
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title | Initial delivery state of programmable devices on the module |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Storage device name | Content | Notes |
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EEPROM | Preprogrammed with Microchip programmer license | Do not overwrite! | System Controller | Preprogrammed with Firmware | Visit TEB2000 Firmware for further information.
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Signals, Interfaces and Pins
Connectors
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anchor | Table_SIP_C |
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title-alignment | center |
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title | Board Connectors |
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Note |
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Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
Scroll Title |
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anchor | Table_OV_IDS |
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title-alignment | center |
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title | Initial delivery state of programmable devices on the module |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default | style |
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widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Connector Type | Designator
| Interface | IO CNT |
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Storage device name | ContentEEPROM | Preprogrammed with AMD programmer license | Do not overwrite! | System Controller CPLD | Preprogrammed with SC CPLD Firmware | The Firmware sources are available for modification to your needs. Visit TE0703 Firmware for further information.
| |
The carrier is shipped in the following configuration:
VCCIO -A/B/C/D voltage selection jumpers are all set to 1.8 V.SD IO Voltage jumper J11 is set to 1.8 V.VBat jumper J7 is set to gnd.Switch S1 configured as reset button in CPLD.The Base Board is shipped with two VG96 backplane connectors, which are not soldered.VG96 | J1 | JB1 - IO | 48 SE / 24 DIFF |
| VG96 | J1 | JB3 - IO | 36 SE / 18 DIFF |
| VG96 | J1 | B2B/SC - I²C | 2 |
| Micro USB Type A/B 1) | J12 | JB3 - USB 2.0 OTG | 2 |
| RJ-45 Ethernet
| J14 | B2B - ETH | 8 |
| RJ-45 Ethernet | J14 | SC - ETH LED | 4 |
| VG96 | J2 | JB2 - IO | 65 SE / 32 DIFF |
| VG96 | J2 | SC - IO | 16 |
| Mini USB Type B | J21 | SC - USB 2.0 | 2 |
| microSD Card socket | J3 | SDIO | SDIO 2) |
| Mini USB Type B | J4 | FTDI - USB 2.0 | 2 |
| USB Type A 1) | J6 | JB3 - USB 2.0 OTG | 2 |
| B2B
| JB1
| J1 - IO
| 48 SE / 24 DIFF |
| B2B
| JB1
| 2 x UART or 4 x IO
| 4
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| B2B | JB1 | I2C or 2 x IO
| 2 |
| B2B | JB1 | SC - IO | 2 |
| B2B | JB1 | SDIO | SDIO 2) or 6 x IO |
| B2B | JB1 | ETH - MDI | ETH |
| B2B | JB2 | J2 - IO | 65 SE / 32 DIFF |
| B2B | JB2 | SC - JTAG | 4 |
| B2B | JB2 | SC - Reset | 1 |
| B2B | JB2 | 2 x LED or 2 x IO | 2 |
| B2B | JB3 | J1 - IO | 36 SE / 18 DIFF |
| B2B | JB3 | USB | USB |
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1) Depending on the variant only one of the USB connectors is assembled. 2) Depending on firmware microSD Card socket is connected to SC or SoM. Refer to TEB2000 CPLD Firmware for further information. |
Test Points
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delete the Test Point section. Example: Test Point | Signal | Notes1) |
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TP1 | PWR_PL_OK |
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1) Direction: - IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
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Scroll Title |
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anchor | Table_SIP_TPs |
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title-alignment | center |
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title | Test Points Information |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Test Point | Signal | Notes |
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TP1 | 5VIN |
| TP2 | 5VIN |
| TP3 | VIN |
| TP4 | VIN |
| TP5 | 3.3V |
| TP6 | 3.3V |
| TP7 | VCCIOA |
| TP8 | VCCIOA |
| TP9 | VCCIOB |
| TP10 | VCCIOB |
| TP11 | VCCIOC |
| TP12 | VCCIOC |
| TP13 | VCCIOD |
| TP14 | VCCIOD |
| TP15 | M1.8VOUT |
| TP16 | M1.8VOUT |
| TP17 | M3.3VOUT |
| TP18 | M3.3VOUT |
| TP19 | UART_VBUS |
| TP20 | UART_VBUS |
| TP21 | VCCJTAG |
| TP22 | VCCJTAG |
| TP23 | 3.3V_SD |
| TP24 | 3.3V_SD |
| TP25 | USB-VBUS_R |
| TP26 | USB-VBUS_R |
| TP27 | ETH-VCC |
| TP28 | ETH-VCC |
| TP29 | Vbus |
| TP30 | Vbus |
| TP31 | CM1 |
| TP32 | CM0 |
| TP33 | MIO0 |
| TP34 | JTAGEN |
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On-board Peripherals
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection Example: Chip/Interface | Designator | Connected To | Notes |
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ETH PHY | U10 | | Gigabit ETH PHY |
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Scroll Title |
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anchor | Table_OBP |
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title-alignment | center |
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title | On board peripherals |
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S2 DIP switches are configured as follows:Switch | Position | Signal name | Description |
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S2-1 | OFF | CM1 | PGOOD signal active state set to high. |
S2-2 | ON | CM0 | FPGA access to SoM.
See TE0703 Firmware section "JTAG" for access options.S2-3 | ON | JTAGEN |
S2-4 | ON | MIO0 | Boot source set to SD Card. See TE0703 Firmware section "Boot Mode" for access options. |
Signals, Interfaces and Pins
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For subsection examples see: <Series Name> TRM Template section examples
Note |
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- Table with all connectors and Designator
- List of different interfaces per connector
- IO CNT (for FPGA IOs where functionality can be changed by customer)
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Connectors
Scroll Title |
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anchor | Table_SIP_C |
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title-alignment | center |
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title | Board Connectors |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Connector Type | DesignatorConnectionEndpoint | Interface | IO CNT | Notes | VG96 | J1 | JB1 | IO | 48 SE / 24 DIFF | To SoM via JB1 |
3x 2.54 mm Pin Header | J7 | JB1 | Battery Voltage | 1 | To SoM via JB1. 1.2 to 1.5 Volt |
RJ-45 Ethernet
| J14 | JB1 | Ethernet | 8 | Gbit capable, Phy MDI to SoM, LEDs to SC
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VG96 | J2 | JB2 | IO | 48 SE / 24 DIFF | To SoM via JB2 |
VG96 | J2 | JB2 | IO | 18 SE / 9 DIFF | To SoM via JB2 |
VG96 | J1 | JB3 | IO | 36 SE / 18 DIFF | To SoM via JB3 |
Micro USB Type A/B or USB Type A | Exclusive J6 or J12 | JB3 | USB 2.0 OTG | 3 | To SoM, Data ± and ID. Only on USB jack possible |
VG96 | J2 | SC | IO | 18 | To SC X0 unto X17 |
B2B | JB2 | SC | JTAG | 4 | To SC |
B2B | JB2 | SC | Reset, RESIN | 1 | To SC |
Mini USB Type B | J4 | SC | USB 2.0 | 2 | To Carrier FTDI |
Mini USB Type B | J21 | SC | USB 2.0 | 2 | To Carrier FTDI |
B2B | JB1 | SC | UART | 2 | UART to SoM for application
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B2B | JB1 | SC | UART | 2 | UART to SoM for HSS/System Boot
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microSD Card socket | J3 | SC or SoM | SD | 6 | VG96 | J1 | SoM and SC | I²C | 2 | To SoM via JB1and SC |
Test Points
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delete the Test Point section.
Example:
Test Point | Signal | Notes1) |
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TP1 | PWR_PL_OK | 1) Direction:
- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
Scroll Title |
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anchor | Table_SIP_TPs |
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title-alignment | center |
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title | Test Points Information |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Chip/Interface | Designator | Connected To |
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Test Point | Signal | Direction 1)TP15VININ | Carrier supply voltage | TP2 | 5VIN | IN | Carrier supply voltage | TP3 | VIN | IN | Carrier supply voltage after protection circuit | TP4 | VIN | IN | Carrier supply voltage after protection circuit | TP5 | 3.3V | OUT | Carrier generated | TP6 | 3.3V | OUT | Carrier generated | TP7 | VCCIOA | IN | IO Voltage, generted by SoM | TP8 | VCCIOA | IN | IO Voltage, generted by SoM | TP9 | VCCIOB | IN | IO Voltage, generted by SoM | TP10 | VCCIOB | IN | IO Voltage, generted by SoM | TP11 | VCCIOC | IN | IO Voltage, generted by SoM | TP12 | VCCIOC | IN | IO Voltage, generted by SoM | TP13 | VCCIOD | IN | IO Voltage, generted by SoM | TP14 | VCCIOD | IN | IO Voltage, generted by SoM | TP15 | M1.8VOUT | IN | IO Voltage, generted by SoM | TP16 | M1.8VOUT | IN | IO Voltage, generted by SoM | TP17 | M3.3VOUT | IN | IO Voltage, generted by SoM | TP18 | M3.3VOUT | IN | IO Voltage, generted by SoM | TP19 | UART_VBUS | IN | Carrier USB Bus Voltage | TP20 | UART_VBUS | IN | Carrier USB Bus Voltage | TP21 | VCCJTAG | IN | JTAG Reference Voltage generated, by the SoM | TP22 | VCCJTAG | IN | JTAG Reference Voltage generated, by the SoM | TP23 | 3.3V_SD | OUT | Carrier microSD card Voltage | TP24 | 3.3V_SD | OUT | Carrier microSD card Voltage | TP25 | USB-VBUS_R | OUT | Carrier USB Bus Voltage | TP26 | USB-VBUS_R | OUT | Carrier USB Bus Voltage | TP27 | ETH-VCC | IN | TP28 | ETH-VCC | IN | TP29 | Vbus | IN | External/FTDI USB Bus Voltage | TP30 | Vbus | IN | External/FTDI USB Bus Voltage | TP31 | CM1 | IN | DIP Switches TP32 | CM0 | IN | TP33 | MIO0 | IN | TP34 | JTAGEN | IN | 1) Direction: - IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
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On-board Peripherals
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Notes :
In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection
Example:
- B2B Connector
- FTDI (FT2232H) U4
- FTDI (FT230XQ) U12
- SD Port Expander U2
- Push button S1
- DIP Switch S2
- All LEDs
| Visit TEB2000 CPLD Firmware for further information. | FTDI FT2232H | U4 | | JTAG/UART for Application | FTDI FT230XQ | U12 | | UART for HSS/System Boot
| EEPROM | U10 | | Preprogrammed with Microchip programmer license. Do not overwrite! | SD IO Port Expander | U2 | - SC
- B2B Connector JB1
- microSD Card J3
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| I2C Repeater | U7 | |
| Oscillator | U6 | | 12 MHz |
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Configuration and System Control Signals
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- Overview all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
- In case it's connected to CPLD always link to CPLD description and add not from the current implementation here(in case it's available)
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Scroll Title |
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anchor | Table_OV_CNTRL |
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title-alignment | center |
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title | Controller signal. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Signal Name | Connector.Pin | Direction1) | Description |
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S1 | S1.2 / S1.4 | IN | Push button 2) | SRST | S6.2 / S6.4 | IN | Push button | SRST | JB2.56 | OUT | Push button | CM1 | S2.8 | IN | DIP Switch 2) | CM0 | S2.7 | IN | DIP Switch 2) | JTAGEN | S2.6 | IN | DIP Switch 2) | MIO0 | S2.5 | IN | DIP Switch 2) | VCCIOA | J5.2 | IN | SoM IO Bank supply 3) | VCCIOB | J8.2 | IN | SoM IO Bank supply 3) | VCCIOC | J9.2 | IN | SoM IO Bank supply 3) | VCCIOD | J10.2 | IN | SoM IO Bank supply 3) | SD_CD | J3.9 | IN | SD Card socket Detect Signal | VBUS_V_EN | JB3.54 | IN | Enables USB Host Bus Voltage | USB-VBUS | JB3.56 | OUT | Signal to SoM | RESIN | JB2.17 | OUT | Reset signal 2)
| EN1 | JB1.27 | OUT | Power enable signal 2)
| PGOOD | JB1.29 | INOUT | Power good and/or Boot mode select signal 2) | MODE | JB1.31 | INOUT | Boot mode select signal 2) | NOSEQ | JB1.8 | INOUT | Power Management and/or Select JTAG target on the SoM 2) | PROGMODE | JB1.90 | INOUT | Select JTAG target on the SoM 2) | MIO14 / MIO15 | JB1.91 / JB1.86 | INOUT | UART to SoM (FT2230H) 2) | MIO12 / MIO13 | JB1.100 / JB1.98 | INOUT | UART to SoM (FT230XQ) 2)
| MIO10-SCL / MIO10 MIO10-SDA / MIO11 | J1A.A1 / JB1.96 J1A.A2 / JB1.94 | INOUT | I2C bus 2) | TMS_B / TDI_B / TDO_B / TCK_B | JB2.94 / JB2.96 / JB2.98 / JB2.100 | Signal-dependent | JTAG configuration and debugging interface. JTAG reference voltage: VCCJTAG |
1) Direction: - IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
2) Firmware dependent. Refer to TEB2000 CPLD Firmware for further information. 3) Select 1.8V or 3.3V via jumper. Refer to 4 x 5 Module Integration Guide for further information. |
Power and Power-On Sequence
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Enter the default value for power supply and startup of the module here. - Order of power provided Voltages and Reset/Enable signals
Link to Schematics, for power images or more details |
Power Rails
Chip/Interface | Designator | Connected To | Notes |
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ETH PHY | U10 | | Gigabit ETH PHY |
Scroll Title |
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anchor | Table_OBP |
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title-alignment | center |
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title | On board peripherals |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Chip/Interface | Designator | Connected To | Notes |
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System Controller | U5 | - SoM
- FTDI
- JB1 B2B connector
UART, 6x MIO, 5x Config signals - JB2 B2B connector
JTAG, RESIN and 18 IOs - SD Port Expander
Channel B1, Channel Select, SD Interrupt - Push button S1
- DIP Switch S2
- All LEDs
| The Firmware sources are available for modification to your needs. Visit TEB2000 CPLD Firmware for further information. |
FTDI FT2232H | U4 | | UART for Application |
EEPROM | U10 | | Preprogrammed with AMD programmer license. Do not overwrite! |
FTDI FT230XQ | U12 | | UART for HSS/System Boot
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Oscillator | U6 | | 12 MHz |
SD IO Port Expander | U2 | - SC
- Via JB1 B2B connector to SoM
- microSD Card J3
| Configuration and System Control Signals Page properties |
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List of all power rails which are accessible by the customer - Main Power Rails and Variable Bank Power
- Overview all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
- In case it's connected to CPLD always link to CPLD description and add not from the current implementation here(in case it's available)
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anchor | Table_OVPWR_CNTRLPR |
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title-alignment | center |
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title | Controller signalModule power rails. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Physical defined SignalsPower Rail Name/ Schematic Name | Connector.Pin |
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Signal NameEndpoint | DescriptionS1.2 / S1.4 | S1 | SC.BANK-0.114 | IN | Reset push button. | Functions are firmware dependant. Visit TE0703 CPLD - CC703S for further information. | S6.2 / S2.4 | SRST | JB3.56 | OUT | Soft reset push button for SoM. | S2.1 | CM1 | SC.BANK-1.75 | IN | S2.2 | CM0 | SC.BANK-1.76 | IN | S2.3 | JTAGEN | SC.BANK-0.120 | IN | S2.4 | MIO0 | JB1.88 | IN | J5.2 | VCCIOA | JB1.10 / JB1.12 / J1B.VCCIOA | INOUT | J8.2 | VCCIOB | JB2.2 / JB2.4 / J1B.VCCIOB | INOUT | J9.2 | VCCIOC | JB2.6 / J2B.VCCIOC | INOUT | J10.2 | VCCIOD | JB2.8 / JB2.10 / J2B.VCCIOD | INOUT | J3.9 | SD_CD | SC.Bank-1.93 | IN | SD Card socket Interrupt Signal | Software defined Signals |
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Connector.Pin | Signal Name | Endpoint | Direction1) | Description |
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JB3.54 | VBUS_V_EN | U1.4 | IN | Enable from SoM | JB3.56 | USB-VBUS | U1.8 → R5 (12K) → JB3.56 | OUT | Signal to SoM | U1.5 | USB_OC | SC.BANK-1.73 | IN | Signal to SC | JB2.17 | RESIN | SC.BANK-0.119 | INOUT | Between SoM and SC | JB1.27 | EN1 | SC.BANK-1.81 | INOUT | Between SoM and SC | JB1.29 | PGOOD | SC.BANK-1.82 | INOUT | Between SoM and SC | JB1.31 | MODE | SC.BANK-1.83 | INOUT | Between SoM and SC | JB1.8 | NOSEQ | SC.BANK-1.78 | INOUT | Between SoM and SC | JB1.90 | PROGMODE | SC.BANK-1.104 | INOUT | Between SoM and SC | JB1.91 / JB1.86 | MIO14 / MIO15 | To SC.Bank-1.105 / SC.Bank-1.95 | INOUT | UART to SoM | JB1.100 / 98 | MIO12 / MIO13 | To SC.Bank-1.100 / SC.Bank-1.99 | INOUT | Second UART to SoM | J1A.MIO10-SCL / J1A.MIO11-SDA | MIO10-SCL / MIO10 MIO10-SDA / MIO11 | JB1.96 / SC.Bank-1.MIO10 JB1.94 / SC.Bank-1.MIO11 | INOUT | I2C with 5.1 kOhm pull-up resistors. To SoM and SC | 1) Direction: - IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
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Power and Power-On Sequence
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Enter the default value for power supply and startup of the module here. - Order of power provided Voltages and Reset/Enable signals
Link to Schematics, for power images or more details |
Power Rails
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List of all power rails which are accessible by the customer
- Main Power Rails and Variable Bank Power
Scroll Title |
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anchor | Table_PWR_PR |
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title-alignment | center |
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title | Module power rails. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Rail Name/ Schematic Name | Connector + Pin | Direction1) | Notes |
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5VIN | J13.1 | IN | 5VIN | J2A.5VIN | OUT | 3.3V | J1C.3.3V / J2C.3.3V / JB1.2 / JB1.4/ JB1.6/ JB1.14/ JB1.16 / JB2.1 / JB2.3 / JB2.5 / JB2.7 | OUT | USB-VBUS | J6.1 / J12.1 / JB3.56 | OUT | M1.8VOUT | JB1.40 / J11.1 | IN | From SoM |
M1.8VOUT | J5.3 / J8.3 / J9.3 / J10.3 / J11.1 | OUT | M3.3VOUT | JB2.9 / JB2.11 | IN | From SoM |
M3.3VOUT | J5.1 / J8.1 / J9.1 / J10.1 / J1C.M3.3VOUT / J2C.M3.3VOUT; | OUT | VCCJTAG | JB2.92 | IN | From SoM |
ETH-VCC | JB1.13 | IN | From SoM |
VCCIOA | JB1.10 / JB1.12 | IN | AMD SoM abhängig |
VCCIOA | J5.2 / J1B.VCCIOA | OUT | Use jumper J5 to select between M1.8VOUT or M3.3VOUT. |
VCCIOB | JB2.2 / JB2.4 | IN | AMD SoM abhängig |
VCCIOB | J8.2 / J1B.VCCIOB | OUT | Use jumper J8 to select between M1.8VOUT or M3.3VOUT. |
VCCIOC | JB2.6 | IN | AMD SoM abhängig |
VCCIOC | J9.2 / J2.VCCIOC | OUT | Use jumper J9 to select between M1.8VOUT or M3.3VOUT. |
VCCIOD | JB2.8 / JB2.10 | IN | AMD SoM abhängig |
VCCIOD | J10.2 / J2.VCCIOD | OUT | Use jumper J10 to select between M1.8VOUT or M3.3VOUT. |
1) Direction:
- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
Recommended Power up Sequencing
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List baseboard design hints for final baseboard development. |
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anchor | Table_BB_DH |
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title-alignment | center |
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title | Baseboard Design Hints |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Sequence | Net name | Recommended Voltage Range | Pull-up/down | Description | Notes |
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0 | - | - | - | Configuration signal setup. | See Configuration and System Control Signals. |
1 | 5VIN | 5V (± 5 %) | - | Main Power supply via J13 Barrel Plug 2.1 mm. | Carrier and SoM power supply. Minimal 1 A, maximal 4A. Power consumption depends mainly on design and cooling solution. |
2 | M3.3VOUT (JB2, 9, 11) | 3.3 V (± 3 %) Schematic | - | SoM generated voltage, which signals operational readyness of the SoM. | 3 | - | - | - | Apply voltages to Carrier powered external IO when voltages under point 2 are present. | Board to Board Connectors
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This section is optional and only for modules.J13.1 | IN |
| 5VIN | J2A.A1 / J2A.A2 | OUT |
| 3.3V | J1C.C31 / J2C.C31 / JB1.2 / JB1.4/ JB1.6/ JB1.14/ JB1.16 / JB2.1 / JB2.3 / JB2.5 / JB2.7 | OUT |
| USB-VBUS_R | J6.1 / J12.1 | OUT |
| USB-VBUS | JB3.56 | OUT |
| M1.8VOUT | JB1.40 | IN |
| M1.8VOUT | J5.3 / J8.3 / J9.3 / J10.3 | OUT |
| M3.3VOUT | JB2.9 / JB2.11 | IN |
| M3.3VOUT | J5.1 / J8.1 / J9.1 / J10.1 / J1C.C32 / J2C.C32 | OUT |
| VCCJTAG | JB2.92 | IN |
| ETH-VCC | JB1.13 | IN |
| ETH-VCC | J14A.1 | OUT |
| VCCIOA | JB1.10 / JB1.12 / J1B.B1 | OUT | Selection via J5 2) | VCCIOB | JB2.2 / JB2.4 / J1B.B32 | OUT | Selection via J8 2) | VCCIOC | JB2.6 / J2B.B32
| OUT | Selection via J9 2) | VCCIOD | JB2.8 / JB2.10 / J2B.B1 | OUT | Selection via J10 2) |
1) Direction: - IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
2) Select 1.8V or 3.3V via jumper. Refer to 4 x 5 Module Integration Guide for further information. |
Recommended Power up Sequencing
Page properties |
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List baseboard design hints for final baseboard development. |
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anchor | Table_BB_DH |
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title-alignment | center |
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title | Baseboard Design Hints |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Sequence | Net name | Recommended Voltage Range | Pull-up/down | Description | Notes |
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0 | - | - | - | Configuration signal setup. | See Configuration and System Control Signals. | 1 | 5VIN | 5 V (± 5 %) | - | Main Power supply. | Carrier and SoM power supply. Minimal 1 A, maximal 4A. Power consumption depends mainly on design and cooling solution. | 2 | M3.3VOUT / M1.8VOUT | 3.3 V (± 3 %) / 1.8 V (± 3 %) | - | SoM generated output voltages. | These voltages can be used - to supply bank voltages,
- to supply periphery and/or
- as power good signal to enable external power regulators.
Important: Consider maximum power consumption. | 3 | - | - | - | Apply voltages to Carrier powered external IO when voltages under point 2 are present. |
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Board to Board Connectors
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- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
Include Page |
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| 6 x 6 SoM LSHM B2B Connectors |
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| 6 x 6 SoM LSHM B2B Connectors |
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Include Page |
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| 4 x 5 SoM LSHM B2B Connectors |
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| 4 x 5 SoM LSHM B2B Connectors |
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Technical Specifications
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List of all power rails which are accessible by the customer - Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)
This Table shows the real values and reasons for the limits, so that they do not get lost. Power Rail / Schematic Name | Description | Min | Max | Unit | Notes | Reason for the limit |
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SD Card Limits | Limits for 3.3 V and 1.8 V SD Card supply. Only Recommanded values are given. | Rec: 2.7 1.7 | Rec: 3.6 1.95 | V | Supplied by M3.3VOUT and optional by M1.8VOUT, when SD IO Jumper is to 1.8 V. |
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| 5VIN | Carrier supply voltage rail before the input protection. | Abs: -40 Rec: 4.75 | Abs: 60 Rec: 5.5 | V | Voltages outside of the range 4.06 to 5.58 V will trigger the input protection. Rec.= USB Bus Voltage |
| VCCIOA | SoM IO Bank Voltage. | - | - | V | Voltage can be supplied by M1.8VOUT, M3.3VOUT or externally by VG96 IO. |
| VCCIOB | SoM IO Bank Voltage. | - | - | V | Voltage can be supplied by M1.8VOUT, M3.3VOUT or externally by VG96 IO. |
| VCCIOC | SoM and Carrier Sc IO Bank 2 voltage. | Abs: -0.5 Rec: 1.14 | Abs: 3.75 Rec: 3.6 | V | Voltage can be supplied by M1.8VOUT, M3.3VOUT or externally by VG96 IO. System Controller Limits: Abs: -0.5 to 3.75 Rec VCC: 2.375 to 3.6 Rec IO: 1.14 to 3.6 | Limited by Absolute Maximum Values of the Sc. | VCCIOD | SoM IO Bank Supply Voltage. | - | - | V | Voltage can be supplied by M1.8VOUT, M3.3VOUT or externally by VG96 IO. |
| M1.8VOUT | SoM supplied voltage. Range based on Carrier (± 3 %). Consult SoM requirements.
| Abs: -0.3 | Abs: 4.9 | V | When suppling SC IO Bank 2 via VCCIOC, the limit ist -0.5 to 3.75 V. |
| M3.3VOUT | SoM supplied voltage. | Abs: -0.5 | Abs: 4.6 | V | When suppling SC IO Bank 2 via VCCIOC, the limit ist -0.5 to 3.75 V. When suppling a SD Card, SD Card limits are 2.7 to 3.6 V. | M3.3VOUT is limited by U2 in the range -0.5 to 4.6 V. | VBAT | Dependent on SoM requirements. | - | - | V |
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| VCCJTAG | SoM supplied JTAG Reference Voltage for Carrier SC IO Bank 3. | Abs: -0.5 | Abs: 3.75 | V | System Controller Limits: Abs: -0.5 to 3.75 Rec VCC: 2.375 to 3.6 Rec IO: 1.14 to 3.6 | Limited by Absolute Maximum Values of the Sc. | ETH-VCC | ETH Bias Voltage from SoM. | - | - | V |
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Absolute Maximum Ratings *)
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anchor | Table_TS_AMR |
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title-alignment | center |
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title | Absolute maximum ratings |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Rail / Schematic Name | Description | Min | Max | Unit |
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5VIN | Main input power supply | -0.3 | 60 | V | VCCIOA 1) 2) | Module power supply. | - | - | V | VCCIOB 1) 2) | Module power supply. | - | - | V | VCCIOC 1) 2) | Module and Carrier power supply. | -0.5 | 3.75 | V | VCCIOD 1) 2) | Module power supply. | - | - | V | M1.8VOUT | Module and carrier power supply. | -0.3 | 1.95 | V | M3.3VOUT | Module and carrier power supply. | -0.3 | 3.6 | V | VCCJTAG | JTAG Reference Voltage | -0.5 | 3.75 | V | ETH-VCC | Power supply for ETH connection. | - | - | V |
1) Module-dependent. 2) Voltage is intended to be supplied by M1.8VOUT or M3.3VOUT but can also be supplied externally via VG96 connection. |
*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
This TRM is generic for all variants. Temperature range can differ depending on assembly variant. The voltage ranges between variants should not be affected (exceptions are possible, depending on custom request)
Temperature Range:
This carrier board is capable of being operated at industrial-grade temperatures, which cover at least the range of -40 °C to 85 °C.
Please check the operating temperature range of the mounted SoM and peripheral devices, which determines the operating temperature range of the overall system.
The operating temperature range depends on software and hardware design and cooling solution. Please contact us for options.
Voltage Rails:
Scroll Title |
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anchor | Table_TS_ROC |
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title-alignment | center |
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title | Recommended operating conditions. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Rail / Schematic Name | Description | Min | Max | Unit | Notes |
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5VIN | Main input power supply | 4.75 | 5.25 | V |
| VCCIOA 1) 2) | Module power supply. | - | - | V |
| VCCIOB 1) 2) | Module power supply. | - | - | V |
| VCCIOC 1) 2) | Module and Carrier power supply. | 1.14 | 3.6 | V |
| VCCIOD 1) 2) | Module power supply. | - | - | V |
| M1.8VOUT | Module and carrier power supply. | 1.746 | 1.854 | V |
| M3.3VOUT | Module and carrier power supply. | 3.201 | 3.399 | V |
| VCCJTAG | JTAG Reference Voltage | 1.14 | 3.6 | V |
| ETH-VCC | Power supply for ETH connection |
|
use "include page" macro and link to the general B2B connector page of the module series,
For example: 6 x 6 SoM LSHM B2B Connectors Include Page |
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PD:6 x 6 SoM LSHM B2B Connectors | PD:6 x 6 SoM LSHM B2B Connectors | Include Page |
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PD:4 x 5 SoM LSHM B2B Connectors | PD:4 x 5 SoM LSHM B2B Connectors | Technical Specifications
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List of all power rails which are accessible by the customer - Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)
|
Absolute Maximum Ratings *)
Scroll Title |
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anchor | Table_TS_AMR |
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title-alignment | center |
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title | Absolute maximum ratings |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Rail / Schematic Name | Description | Min | Max | Unit | Notes |
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5VIN | Carrier supply voltage rail before the input voltage protection activates. | 012V | Voltages in the range 4.06 to 5.58 V will trigger the input protection. | VCCIOA | Intended as Supply Voltage for a SoM IO Bank. Connects the external VG96 IO to the SoM. Dependent on Carrier and SoM combination, their settings and your external IO devices connected to VG96. | - | - | V | Voltage intended to be supplied by either M1.8VOUT or M3.3VOUT. |
VCCIOB | Intended as Supply Voltage for a SoM IO Bank. Connects the external VG96 IO to the SoM. Dependent on Carrier and SoM combination, their settings and your external IO devices connected to VG96. | - | - | V | Voltage intended to be supplied by either M1.8VOUT or M3.3VOUT. |
VCCIOC | Supplies SC IO Bank 2. Connects the external VG96 IO to the SoM and the Carrier SC. Dependent on Carrier and SoM combination, their settings and your external IO devices connected to VG96. | -0.5 | 3.75 | V | Limited by Absolute Maximum Values of the Sc. |
VCCIOD | Intended as Supply Voltage for a SoM IO Bank. Connects the external VG96 IO to the SoM. Dependent on Carrier and SoM combination, their settings and your external IO devices connected to VG96. | - | - | V | Voltage intended to be supplied by either M1.8VOUT or M3.3VOUT. |
M1.8VOUT | SoM supplied voltage.
Range based on Carrier (± 3 %). Consult SoM requirements.
-0.3 | M3.3VOUT +0.3 V | V | Voltage limited by Q1/MP5077GG-Z Enabled Pin. –0.3V to Vcc +0.3 V (M3.3VOUT-max = 4.6) Connected SD cards might be destroyed above 1.95 V. | M3.3VOUT | SoM supplied voltage. Range based on Carrier (± 3 %). Consult SoM requirements. | -0.5 | 4.6 | V | Limited by U2/TXS02612RTWR. Connected SD cards might be destroyed above 3.6 V. |
VCCJTAG | Supplies SC IO Bank 3. JTAG Reference Voltage from SoM. Consult SoM documentation. | -0.5 | 3.75 | V | ETH-VCC | ETH Bias Voltage from SoM. Consult SoM documentation. | - | - | V | *) Stresses beyond those listed under TEB2000 TRM - New Carrier-Board may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
or any other conditions beyond those indicated under TEB2000 TRM - New Carrier-Board. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Temperature Range:
This carrier board is capable to be operated at industrial grade temperatures.
- Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
Please check the operating temperature range of the mounted SoM and peripheral devices, which determines the operating temperature range of the overall system.
The Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Voltage Rails:
Scroll Title |
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anchor | Table_TS_ROC |
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title-alignment | center |
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title | Recommended operating conditions. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Rail / Schematic Name | Description | Min | Max | Unit | Notes |
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5VIN | Carrier supply voltage rail before the input voltage protection activates. | 4.75 | 5.25 | V | Tolerance is ±5 %. | VCCIOA | Intended as Supply Voltage for a SoM IO Bank. Connects the external VG96 IO to the SoM. Dependent on Carrier and SoM combination, their settings and your external IO devices connected to VG96. | 1.75 | 3.4 | V | Voltage intended to be supplied by either M1.8VOUT or M3.3VOUT. | VCCIOB | Intended as Supply Voltage for a SoM IO Bank. Connects the external VG96 IO to the SoM. Dependent on Carrier and SoM combination, their settings and your external IO devices connected to VG96. | 1.75 | 3.4 | V | Voltage intended to be supplied by either M1.8VOUT or M3.3VOUT. | VCCIOC | Supplies SC IO Bank 2. Connects the external VG96 IO to the SoM and the Carrier SC. Dependent on Carrier and SoM combination, their settings and your external IO devices connected to VG96. | 1.2 | 3.4 | V | Voltage intended to be supplied by either M1.8VOUT or M3.3VOUT. | VCCIOD | Intended as Supply Voltage for a SoM IO Bank. Connects the external VG96 IO to the SoM. Dependent on Carrier and SoM combination, their settings and your external IO devices connected to VG96. | 1.75 | 3.4 | V | Voltage intended to be supplied by either M1.8VOUT or M3.3VOUT. | M1.8VOUT | SoM supplied voltage. Range based on Carrier (± 3 %). Consult SoM requirements. 1.75 | 1.85 | V | Tolerance is ±3 %. | M3.3VOUT | SoM supplied voltage. Range based on Carrier. Consult SoM requirements. | 3.2 | 3.4 | V | Tolerance is ±3 %.VCCJTAG | Supplies SC IO Bank 3. JTAG Reference Voltage from SoM. Consult SoM documentation. | 1.2 | 3.3 | V | Values from Schematic. | ETH-VCC | ETH Bias Voltage from SoM. Consult SoM documentation
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Physical Dimensions
Carrier size: 100 mm x 64.5 mm.
Note that few parts are slightly hanging over the PCB edge. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm.
PCB thickness: 1.64 64 mm ± 10 %.
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anchor | Figure_TS_PD |
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title-alignment | center |
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title | Physical Dimension |
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title | Physical Dimension |
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diagramName | TEB2000-01-Figure_TS_PD |
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simpleViewer | false |
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links | auto |
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tbstyle | hidden |
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lbox | true |
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diagramWidth | 641 |
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height | 752 |
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revision | 1 |
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scroll-pdf | true |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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| Image RemovedImage Added |
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Currently Offered Variants
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anchor | Table_VCP_SO |
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title-alignment | center |
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title | Trenz Electronic Shop Overview |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Revision History
Hardware Revision History
Hardware The hardware revision number can be found is on the PCB board together with adjacent to the module model number identifier, separated by the a dash.
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anchor | Figure_RV_HRN |
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title-alignment | center |
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title | Board hardware revision number. |
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diagramName | TEB2000-01_Figure_RH_HRN |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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lbox | true |
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diagramWidth | 641 |
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height | 506 |
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revision | 1 |
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Image Added | Create DrawIO object here: Attention if you copy from other page, objects are only linked. | Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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anchor | Table_RH_HRH |
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title-alignment | center |
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title | Hardware Revision History |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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Scroll Title |
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anchor | Table_RH_DCH |
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title-alignment | center |
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title | Document change history. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Date | Revision | Contributor | Description |
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Page info |
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infoType | Modified date |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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| Page info |
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infoType | Current version |
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prefix | v. |
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type | Flat |
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showVersions | false |
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| Page info |
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infoType | Modified by |
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type | Flat |
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showVersions | false |
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| - <add TRM change list here>
| | | 2024-08-26 | v.27 | Kilian Jahn | 01 | -- | all | Page info |
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infoType | Modified users |
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type | Flat |
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showVersions | false |
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| |
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Disclaimer
Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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