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Refer to httpshttp://wiki.trenz-electronic.de/display/PD/TEBF0808+TRMorg/tebf0808-info for the current online version of this manual and other available documentation.

The Trenz Electronic TEBF0808 carrier board is a baseboard for the Xilinx Zynq Ultrascale+ MPSoC modules TE0808 and TE0803, which exposes the module's B2B connector pins to accessible connectors and provides a whole range of on-board components to test and evaluate the Zynq Ultrascale+ SoMs and for developing purposes. The carrier board has a Mini-ITX form factor making it capable to be fitted into a PC enclosure. On the PC enclosure's rear and front panel, MGT interfaces and connectors are accessible, for the front panel elements there are also Intel-PC compatible headers available. 

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  • Mini-ITX form factor, PC enclosure compatible
  • ATX-24 power supply connector
  • Optional 12V standard power plug
  • Headers
    • Intel 10-pin HDA Audio
    • Intel 9-pin Power-/Reset-Button, Power-/HD-LED
    • PC-BEEPER
  • On-board Power- / Reset-Switches
  • 2x Configuration 4-bit DIP-switches
  • 2x Optional 4-wire PWM fan connectors
  • PCIe Slot - one PCIe lane (16 lane connector)
  • CAN FD Transceiver (10 Pin IDC connector and 6-pin header)
  • 4x On-board configuration EEPROMs (1x Microchip 24LC128-I/ST, 3x  Microchip 24AA025E48T-I/OT)
  • Dual SFP+ Connector (2x1 Cage)
  • 1x DisplayPort (single lane)
  • 1x SATA Connector
  • 2x USB3.0 A Connector (Superspeed Host Port (Highspeed at USB2.0))
  • 1x USB3.0 on-board connector with two ports
  • FMC HPC Slot (FMC_VADJ max. VCCIO)
  • FMC Fan
  • Gigabit Ethernet RGMII PHY with RJ45 MegJackMagJack
  • All carrier board peripherals' I²C interfaces muxed to MPSoC's I²C interface
  • Quad programmable PLL clock generator SI5338A
  • 2x SMA coaxial connectors for clock signals
  • MicroSD- / MMC-Card Socket (bootable)
  • 32 Gbit (4 GByte) on-board eMMC flash (8 banks a 4 Gbit)
  • 2x System Controller CPLDs Lattice MachXO2 1200 HC
  • 1x Samtec FireFly (4 GT lanes bidirectional)
  • 1x Samtec FireFly connector for reverse loopback
  • 2x JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for programming MPSoC and SC CPLDs
  • 20-pin ARM JTAG Connector (PS JTAG0)
  • 3x PMOD connector (GPIO's and I²C interface to SC CPLDs and MPSoC module)
  • On-board DC-DC PowerSoCs

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On-board PeripheralB2BMPSoC Unit /
SoM peripheral
DescriptionTRM Section
FMC HPC J5, 24 LVDS pairs (48 I/O's)J1PL Bank (FMC_VADJ)

PL I/O-bank pins, differential pairs

FMC HPC Connector
FMC HPC J5, GTH InterfaceJ1MGT Bank10 MGT LanesFMC HPC Connector
SFP+ 2x1 Cage J14J1MGT Bank2 MGT Lanes to dual SFP+ ConnectorMGT Interfaces SFP+ and FireFly
SMA Coax J33J1On-module PLLSMA Coaxial Connector to on-module
PLL Clock Input pin
Programmable PLL Clock Generator
FMC HPC J5
  • 10 LVDS pairs (20 I/O's)
  • 1 LVDS Clock to PL Bank
  • 2 MGT Clocks to MGT Banks
J2

PL Bank (FMC_VADJ)

MGT Bank

PL I/O-bank pins, differential pairs

1 clock capable PL bank pin-pair

2 MGT clock input pin-pairs

FMC HPC Connector 
Programmable PLL Clock Generator

24-bit Audio Codec U3J3PL Bank (1.8 V)PL I/O-bank pins to on-board
24-bit Audio Codec
Intel-PC Compatible Headers and FAN Connectors
24-bit Audio Codec
10 I/O's to SC CPLD U17J3PL Bank (1.8 V)

PL I/O-bank pins to on-board
System Controller CPLD U17

System Controller CPDLsCPLDs
8 I/O's to SC CPLD U39J3PL Bank (1.8 V)

PL I/O-bank pins to on-board
System Controller CPLD U39

System Controller CPDLsCPLDs
SDIO Interface, SD- / MMC-Card MuxJ3PS MIOSDIO interface connected to
SD- / MMC-Card socket
MIO Bank Interfaces
SDIO Port Expander
Board Peripheral's I²C Interfaces
muxed to MPSoC I²C
J3PS MIOMPSoC I²C interface configured as
master connected to on-board slaves
MIO Bank Interfaces 
8-Channel I²C Switches
4 MIO to SC CPLD U17J3PS MIOFunctionality depending on MPSoC and
CPLD firmware
System Controller CPDLsCPLDs
15 MIO to SC CPLD U39J3PS MIO

Functionality depending on MPSoC and
CPLD firmware

System Controller CPDLs
Ethernet PHY RGMIIJ3PS MIOEthernet PHY U12 connected per RGMII

MIO Bank Interfaces
Gigabit Ethernet PHY

eMMC FlashJ3PS MIOeMMC Flash memory interface on PS bankMIO Bank Interfaces 
eMMC Memory
USB2.0 PHY ULPIJ2PS MIOUSB2.0 PHY U9 connected per ULPIMIO Bank Interfaces
High-speed USB ULPI PHY
SAMTEC FireFly Connector J6/J15J2MGT BankMGT Lanes to Samtec FireFly connectorMGT Interfaces SFP+ and FireFly
JTAG Interface via XMOD Header J12J2PS ConfigMPSoC USB programmable JTAG interface

MIO Bank Interfaces
JTAG Interface

USB3.0 LaneJ2PSGTUSB3.0 PS MGT Lane

MIO Bank Interfaces
PS GT Bank Interfaces

4-port USB3.0 Hub--USB3.0 (2.0 compatible) Hub with 4 portsMIO Bank Interfaces
4-port USB3.0 Hub
USB3.0 / RJ45 GbE Connector J7,
USB3.0 Connector J8
--2-port USB3.0 / RJ45 GbE Connector (stacked)MIO Bank Interfaces
25 SoM Control Signals to
SC CPLDs U17 / U39
J2On-module DC-DC
converter, PLL clock
generator
Control Signals, e.g.  "Enable"- / "Power Good"-
signals of DC-DC-converter and further on-module
peripherals

Power-On Sequence Diagram
Programmable PLL Clock Generator

150 MHz Osci Clock InputJ2-150 MHz SATA interface MGT clockOscillators

Signals DONE, INIT_B, SRST_B, ...
to SC CPLD U39

J2PS ConfigMPSoC control signal for PS- / PL configurationSystem Controller CPDLsCPLDs

SATA Connector J31
PCIe Connector J1
DisplayPort J13

J2PSGTConnectors of the MGT based data interfacesPS GT Bank Interfaces

PLL Clock Output to

  • PCIe Interface
  • On-board PLL U35
  • MGT Bank (B2B J3)
J2On-module PLL
clock generator

Reference clock signals of the on-module
programmable PLL clock generator

Programmable PLL Clock Generator
4 I/O's to PMOD P2 via IC U33J4PL Bank (FMC_VADJ)PL user I/O's accessible on PMOD connector P2CAN FD Interface and PMOD Connectors
3 I/O's to SC CPLD U17 via IC U32J4PL Bank (FMC_VADJ)PL user I/O's routed to System Controller
CPLD U17
System Controller CPDLsCPLDs
FMC HPC J5
  • 46 LVDS pairs (92 I/O's)
  • 1 LVDS Clock to PL Bank
J4PL Bank (FMC_VADJ)

PL I/O-bank pins, differential pairs

1 clock capable PL bank pin-pair

FMC HPC Connector
Programmable PLL Clock Generator

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FunctionMGT LaneSchematic Names / B2B pinsRequired Ref ClockClock SourceComment
PCIePS 0

PCI_TX_N, pin J2-67
PCI_TX_P, pin J2-69

PCI_RX_N, pin J2-70
PCI_RX_P, pin J2-72

100 MHzclock signal of SoM's prog. PLL

single lane PCIe connector

clock signal routed on carrier board to PCIe connector J1

USB3PS 1

USB3_TXUP_N, pin J2-61
USB3_TXUP_P, pin J2-63

USB3_RXUP_N, pin J2-64
USB3_RXUP_P, pin J2-66

100 MHzclock signal of SoM's prog. PLL

clock signal routed on-module,
also optional Optional (not equipped) 100 MHz osci. U35 configurable. U6 is possible (Configurable on Zynq PS).

SATAPS 2

SATA_TX_N, pin J2-55
SATA_TX_P, pin J2-57

SATA_RX_N, pin J2-58
SATA_RX_P, pin J2-60

150 MHzOn-board oscillator U23

optional: clock signal of SoM's prog. PLL

DP.0PS 3

DP0_TX_N, pin J2-49
DP0_TX_P, pin J2-51

27 MHzclock signal of SoM's prog. PLL

DisplayPort GT SERDES clock signal,
routed on-module to MGT bank

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PMODInterfaceConnected toNotes
P1I²C8-channel I²C Switch U27Accessible on MPSoC's I²C interface through I²C switch U27
P2GPIOHP Bank of MPSoC (4 I/O's, B65_T0 ... B65_T3),
System Controller CPLD U17 (4 I/O's, EX_IO1 ... EX_IO4)
Voltage translation via IC U33 with direction control,
only singled-ended signaling possible
P2I²C8-channel I²C Switch U27Accessible on MPSoC's I²C interface through I²C switch U27
P3I²C8-channel I²C Switch U27Accessible on MPSoC's I²C interface through I²C switch U27

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The System Controller CPLDs will be programmed by the XMOD-Header J28 in a cascaded JTAG chain as visualized in Figure 89. To program the System Controller CPLDs, the JTAG interface of these devices have to be activated by DIP-switch S4-3.
The 4 GPIO/UART pins (XMOD1_A/B/E/G) of the XMOD-Header J28 are routed to the System Controller CPLD U17.

...

Further JTAG interfaces of the TEBF0808 carrier board are the ARM JTAG 20-pin IDC connector J30 and on the FMC Connector J5. This JTAG interfaces are connected to the System Controller CPLD U17, hence the logical processing and forwarding of the JTAG signals depend on the SC CPLD firmware. The documentation of the firmware of the SC CPLD U17 contains detailed information on this matter.

On-board Peripherals

System Controller

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CPLDs

The TEBF0808 is equipped with two System Controller CPLDs - Lattice Semiconductor LCMXO2-1200HC (MachXO2 Product Family) - with the schematic designators U17 and U39.

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Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

Both Sytem System Controller CPLDs are connected to the Zynq Ultrascale+ MPSoC through MIO, PL IO-bank pins and I²C interface. The CPLDs are connected with each other through the IO pins SC_IO0 ... SC_IO8.

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Clock SourceSchematic NameFrequencyClock Input Destination
SiTime SiT8008BI oscillator, U10USB0_RCLK52.000000 MHzUSB 2.0 transceiver PHY U9, pin 26
SiTime SiT8008BI oscillator, U13ETH_CLK25.000000 MHzGigabit Ethernet PHY U12, pin 34
SiTime SiT8008BI oscillator, U7-25.000000 MHzQuad PLL clock generator U35, pin 3
DSC1123 oscillator, U23B505_CLK1150.0000 MHzPS GT Bank, dedicated for SATA interface

DSC1123 oscillator, U6

optional, not equipped

B505_CLK0100.0000 MHzPS GT Bank, dedicated for USB interface

Silicon Labs 570FBB000290DG, U45

optional, not equipped

B47_L5 (LVDS)250.MHzPL Bank clock capable input pins
SiTime SiT8008BI oscillator, U25CLK_CPLD2524.576000 MHzSystem Controller CPLD U35, pin 128

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I²C Slave Devices connected to MPSoC I²C InterfaceI²C
Switch
Position
I²C Slave AddressSchematic Names of I²C Bus Lines
8-channel I²C switch U16-0x73I2C_SDA / I2C_SCL
8-channel I²C switch U27-0x77I2C_SDA / I2C_SCL
SC CPLD U39, bank 2, pins 52 (SDA), 50 (SCL)-User programmableI2C_SDA / I2C_SCL
I²C Slave Devices connected to 8-channel I²C Switch U16I²C
Switch
Position
I²C Slave AddressSchematic Names of I²C Bus Lines
On-board Quad programmable PLL clock generator U35 Si533800x70MCLK_SDA / MCLK_SCL
8-bit I²C IO Expander U4410x26SFP_SDA / SFP_SCL
PCIe Connector J12module dependentPCIE_SDA / PCIE_SCL
SFP+ Connector J14A3module dependentSFP1_SDA / SFP1_SCL
SFP+ Connector J14B4module dependentSFP2_SDA / SFP2_SCL
Configuration EEPROM U24U4250x54MEM_SDA / MEM_SCL
Configuration EEPROM U3650x52MEM_SDA / MEM_SCL
Configuration EEPROM U4150x51MEM_SDA / MEM_SCL
Configuration EEPROM U2250x50MEM_SDA / MEM_SCL
8-bit I²C IO Expander U3850x27MEM_SDA / MEM_SCL
FMC Connector J56module dependentFMC_SDA / FMC_SCL
USB3.0 Hub configuration EEPROM U570x51USBH_SDA / USBH_SCL
USB3.0 Hub70x60USBH_SDA / USBH_SCL
I²C Slave Devices connected to 8-channel I²C Switch U27I²C
Switch
Position
I²C Slave AddressSchematic Names of I²C Bus Lines
PMOD Connector P10module dependentPMOD_SDA / PMOD_SCL
24-bit Audio Codec U310x38A_I2C_SDA / A_I2C_SCL
FireFly Connector J152module dependentFFA_SDA / FFA_SCL
FireFly Connector J223module dependentFFB_SDA / FFB_SCL
On-module Quad programmable PLL clock generator Si5345 (TE0808)40x69PLL_SDA / PLL_SCL
SC CPLD U17, bank 3, pins 13 (SDA), 14 (SCL)5User programmableSC_SDA / SC_SCL
8-bit I²C IO Expander U3460x24FF_E_SDA / FF_E_SCL
PMOD Connector P37module dependentEXT_SDA / EXT_SCL

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EEPROM ModellSchematic DesignatorMemory DensityPurpose
24LC128-I/STU24U30128 Kbituser
24AA025E48T-I/OTU362 Kbituser
24AA025E48T-I/OTU412 Kbituser
24AA025E48T-I/OTU422 Kbituser
24LC128-I/STU5128 KbitUSB3.0 Hub U4 configuration memory

...

DIP-Switches

There are two 4-bit DIP Switches -witches present on the TEBF0808 carrier board to configure options and set parameters. The table below following section describes the functionalities of the particular switches.

DIP-switch S4

Table below describes the functionalities of the switches of DIP-switch S4 at their single positions:

DIP-switch S4Position ONPosition OFFNotes
S4-1PUDC_B is LowPUDC_B is HIGHInternal pull-up resistors during configuration are enabled at ON-position,
means I/O's are 3-stated until configuration of the FPGA completes. 
S4-2xxnot connected
S4-3SC CPLDs' JTAG enabledSC CPLDs' JTAG disabledJTAG interface is enabled on both SC CPLDs, as this CPLDs are
configured in a casdaced JTAG chain.
S4-4DC-DC converter U18 (5V) enabledDC-DC converter U18 (5V) not manually enabledIn OFF-position, the DC-DC-converter will be still enabled by the
Enable-signal ('5V_EN') of SC CDPD U17 U39 (wired-OR circuit).

Table 22: DIP-switch S4 functionality description

DIP-switch S5

DIP-switch S5 located close to PWR push-button is connected to the two System Controller CPLDs, its functionalities depend on the current firmware of the CPLDs.

The switches of this DIP-switch have to be set in bit-patterns to set a parameter like boot mode or FMC_VADJ value:is connected to SC CPLD U17 and U39 as fellows:

DIP-switch S5Signal Schematic NameConnected toFunctionalityCPLD Documentation
S5-1SC_SW1SC CPLD U39, pin 133set 2-bit code for boot mode selection

TEBF0808 Slave CPLD

Section: Boot Mode

S5-2SC_SW2SC CPLD U39, pin 138
S5-3SC_SW3SC CPLD U17, pin 6user defined

TEBF0808 Master CPLD

S5-4SC_SW4SC CPLD U17, pin 5set FMC_VADJ: 1.8V at ON-position, 1.2V at OFF-position

Table 23: DIP-switch S5 connection to SC CPLDs


The boot mode of the mounted Ultrascale+ Zynq MPSoC module will be set in current SC CPLD U39 firmware version as described in the table below:

S5-1S5-2Description
ONONDefault, boot from SD/microSD or SPI Flash if no SD is detected
OFFONBoot from eMMC
ONOFFBoot mode  PJTAG0
OFFOFFBoot mode main  JTAG
S5-1S5-2S5-3S5-4Description
ONONONONDefault, boot from SD/eMMC, 1.8V FMC VADJ
ONONxxBoot from microSD, SD or SPI Flash
OFFONxxBoot from eMMC
ONOFFxxBoot mode  PJTAG0
OFFOFFxxBoot mode main  JTAG
xxxONFMC VADJ = 1.8V
xxxOFFFMC VADJ = 1.2V

Table 23: DIP-switch S4 functionality descriptionS5 boot mode selection

On-board LEDs

The TEBF0808 carrier board is equipped with several LED to signal current states and activities. The functionality of the LEDs D4 ... D7 depends on the current firmware of the SC CPLDs U17 and U39.

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Following diagram visualizes the connection of the DC-DC converter control signals ('Enable', 'Power-Good') with System Controller CPLD U39, which enables the particular on-board voltages.

 


Figure 13: Power-On Sequence Utilizing DCDC Converter Control Signals

Note

As shown in Figure 1213, the DIP switch S4-4 has to be closed if using only 12V single power supply through 12V power jack J25, otherwise the 5V voltage level will not be enabled to generate the 3V3SB voltage to power up the SC CPLD U39 and starting the power-on sequence.
By using an ATX-24 power connector on J20, there is usually also a 5V supply voltage provided, hence the DIP switch S4-4 is not relevant in this case of power supply.

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  • Module size: 170 mm × 170 mm.  Please download the assembly diagram for exact numbers

  • Mating height with standard connectors: 5 mm

  • PCB thickness: 1.844 mm ± 10%

  • Highest part on PCB: approx. 32 mm. Please download the step model for exact numbers

All dimensions are given in millimeters.

 Image Removed       Image Removed

Figure 14: Board physical dimensions drawing.

Revision History

Hardware Revision History

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Notes

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  • Please download the assembly diagram for exact numbers

  • Mating height with standard connectors: 5 mm

  • PCB thickness: 1.844 mm ± 10%

  • Highest part on PCB: approx. 32 mm. Please download the step model for exact numbers

All dimensions are given in millimeters.

 Image Added       Image Added

Figure 14: Board physical dimensions drawing.

Revision History

Hardware Revision History

 DateRevision

Notes

Link to PCNDocumentation Link
-04Current available board revision-TEBF0808-04
-03Second production release-TEBF0808-03
-02First production release-TEBF0808-02
-01Prototype--

Table 35: Board hardware revision history.

Hardware revision number is written on the PCB board together with the module model number separated by the dash.

Image Added

Figure 15: Board hardware revision number.

Document Change History

 Date

Revision

ContributorsDescription

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
typeFlat

Page info
infoTypeModified by
dateFormatyyyy-MM-dd
typeFlat

  • System Controller links fixed
2019-09-03v.96Thomas Steffens
  • correction EEPROM Designator
  • correction typ U25 CLK

2018-07-02

v.89Martin Rohrmüller
  • Typo

2018-05-31

v.88

John Hartfiel
  • Typo correction Table 13
  • Typo correction Table 9
2017-11-15v.86Ali Naseri
  • DIP-switches section revised and updated

2017-11-13

v.82

Ali Naseri
  • updated B2B connector max. current rating
    per pin

2017-11-13

v.80

...

Hardware revision number is written on the PCB board together with the module model number separated by the dash.

Image Removed

Figure 15: Board hardware revision number.

Document Change History

yyyy-MM-dd

 Date

Revision

ContributorsDescription
Page info
modified-datemodified-datedateFormatJohn Hartfiel
  • rework B2B section
2017-10-19

v.79

Ali Naseri
  • added additionally MGT lanes information

2017-10-18

v.75
Ali Naseri
  • added Power Rails section

2017-08-29

v.70



John Hartfiel
  • update document change history
  • published
2017-08-28v.69Ali Naseri
  • Initial document

--

all

Page info
infoTypeModified users
typeFlat
showVersionsfalse

  • --

Table 36: Document change history.

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