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The Trenz Electronic TE0807 is an industrial-grade MPSoC SoM integrating a Xilinx an AMD Zynq UltraScale+ MPSoC, up to 8 GBytes of DDR4 SDRAM via 64bit 64 bit wide data bus, max. 512 MByte Flash memory for configuration and operation, 20 Gigabit transceivers and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os are provided via rugged high-speed stacking connections. All this in a compact 5.2 x 7.6 cm form factor, at the competitive price.

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• MPSoC: ZYNQ UltraScale+ ZU7EV 900-pin package
• Memory
  - 64bit 64 bit DDR4, 8 GByte maximum
  - Dual SPI boot Flash in parallel, 512 MByte maximum
• User I/Os
  - 65 x PS MIOs, 48 x PL HD GPIOs,  156 x PL HP GPIOs (3 banks)
  - Serial transceivers: 4 x GTR + 16 x GTH
  - Transceiver clocks inputs and outputs
  - PLL clock generator inputs and outputs
• Si5345 - 10 output PLL
• All power supplies on board, single 3.3V power source required
  - 14 on-board DC-DC regulators and 13 LDOs
  - LP, FPLPD, FPD, PL separately controlled power domains
• Support for all boot modes (except NAND) and scenarios
• Support for any combination of PS connected peripherals
• Size: 52 x 76 mm, 3 mm mounting holes for skyline heat spreader
• B2B connectors: 4 x 160 pin

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Main Components

1. AMD Xilinx ZYNQ UltraScale+ ZU7EV-1FBVB900 MPSoC, U1
2. EN63A0QI 12A MPQ8633B 20 A PowerSoC DC-DC converter, U4
3. TI TPS72018 LDO @1.8V, U6
4. TI TPS74401 LDO @0.9V, U14
5. TI TPS74401 LDO @1.2V, U28TI TPS72018 LDO @1.8V, U6
6. Clock, U5
7. Quarz Crystal @50.000MHz, Y1
8. Low-power programmable oscillator @ 25.000000 MHz (IN0 for U5), U25
9. TI TPS74801 LDO @1.8V, U10
10. TI TPS74801 LDO @0.9V, U8
11. 8 Gbit (512Mx16) DDR4-2400 SDRAM, U12
12. 8 Gbit (512Mx16) DDR4-2400 SDRAM, U9
13. 8 Gbit (512Mx16) DDR4-2400 SDRAM, U2
14. 8 Gbit (512Mx16) DDR4-2400 SDRAM, U3
15. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
16. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
17. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
18. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
19. 1.8V, 512 Mbit QSPI flash memory ,U17
20. 1.8V, 512 Mbit QSPI flash memory, U7
21. TI TPS72018 LDO @1.8V, U27

Initial Delivery State

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Table 3: Selectable boot modes by dedicated boot mode pins.

For functional details see  ug1085 - Zynq UltraScale+ TRM (Boot Modes Section).

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Table 4: B2B connector pin-outs of available PL and PS banks of the TE0807-01 03 SoM.

All MIO banks are powered from on-module DC-DC power rail. All PL I/O Banks have separate VCCO pins in the B2B connectors, valid VCCO should be supplied from the baseboard.

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The configuration of the I/O's MIO13 - MIO77 are depending on the base-board peripherals connected to these pins.

MGT Lanes

The Xilinx AMD Zynq UltraScale+ MPSoC device used on the TE0807 module has 20 high-speed data lanes (Xilinx AMD GTH / GTR transceiver). All of them are wired directly to B2B connector. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

Table 45: MGT lanes

There are 2 clock sources for the GTH and GTR transceivers. The clock inputs of the MGT transceivers are connected directly to the B2B connectors, so the clock can be provided by the carrier board, and clock inputs are also . The second clock source is provided by the on-board clock generator Si5345A (U5). As there are no capacitive coupling of the data and clock lines that are connected to the B2B connectors, these may be required on the user’s PCB depending on the application.

Table 56: MGT reference clock sources

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Table 47: B2B connector pin-out of JTAG interface.

Configuration Bank Control Signals

The Xilinx AMD Zynq UltraScale+ MPSoC's PS configuration bank 503 control signal pins are accessible through B2B connector J2.

For further information about the particular control signals and how to use and evaluate them, refer to the  Xilinx AMD Zynq UltraScale+ MPSoC TRM and UltraScale Architecture Configuration - User Guide.

Table 58: B2B connector pin-out of MPSoC's PS configuration bank.

Analog Input

The Xilinx AMD Zynq UltraScale+ MPSoC provides differential pairs for analog input values. The pins are exposed to B2B-connector J2.

Table 69: B2B connector pin-out of analog input pins

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Table 710: PS MIO pin assignment of the Quad SPI Flash memory ICs.

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Table 11: TE0807-03 Table 8: TE0807-01 PS MIO mapping

On-board Peripherals

Flash

The TE0808 TE0807 SoM can be configured with max. 512 MByte Flash memory for configuration and operation.

Table 1012: Peripherals connected to the PS MIO pins.

DDR4 SDRAM

The TE0807-01 03 SoM is equipped with with four DDR4 -2400 SDRAM modules chips with a total of up to 8 GByte memory density. The SDRAM modules chips are connected to the Zynq the Zynq MPSoC's PS DDR controller (bank 504) with a 64 - bit wide data bus.

Refer to the Xilinx AMD Zynq UltraScale+ datasheet DS925 for more information on whether the specific package of the Zynq UltraScale+ MPSoC supports the maximum data transmission rate of 2400 MByte/s.

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Table 11Table 13: Programmable PLL clock generator input/output.

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Table 1214: B2B connector pin-out of Si5345A programmable clock generator.

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Si5345 OTP can only be programmed two times, as different user configurations may required different setup TE0808 TE0807 is normally shipped with blank OTP.
For more information refer to Si5345 at SiLabs.

Oscillators

The TE0808TE0807-04 SoM is equipped with two on-board oscillators to provide the Zynq's MPSoC's PS configuration bank 503 with reference clock signals.

Table 13: Reference clock-signals to PS configuration bank 503.

On-board LEDs

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LED

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Table 15: On-board osciallators

MAC Address EEPROMs

There is one Microchip 24AA025E48 serial EEPROMs (U11) present containing a globally unique 48-bit node address, which are compatible with EUI-48(TM) specification. The device are organized as two blocks of 128 x 8 Kbit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. The MAC address EEPROM accessible over I²C bus on B2B connector J2-92 (PLL_SDA)  / J2-90 (PLL_SCL).

On-board LEDs

Table 16: LED's description.

Power and Power-On Sequence

Power Consumption

The maximum power consumption of a module mainly depends on the design which is running on the FPGA.

AMD provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table 17: Maximum current of power supplies. *to be determined soon with reference design setup.

Power supply with minimum current capability of 3A for system startup is recommended. For the lowest power consumption and highest efficiency of on board DC/DC regulators it is recommended to powering the module from one single 3.3V supply. Except 'PS_BATT', all input power supplies have a nominal value of 3.3V. Although the input power supplies

Table 14: LED's description.

Power and Power-On Sequence

Power Consumption

The maximum power consumption of a module mainly depends on the design which is running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

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Table 15: Maximum current of power supplies. *to be determined soon with reference design setup.

Power supply with minimum current capability of 3A for system startup is recommended. For the lowest power consumption and highest efficiency of on board DC/DC regulators it is recommended to powering the module from one single 3.3V supply. Except 'PS_BATT', all input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

The TE0808 TE0807 module equipped with the Xilinx AMD Zynq UltraScale+  MPSoC MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features. This features allow to offset the power and heat constraints against overall performance and operational efficiency.

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The fourth Power Domain is for the Programmable Logic (PL). If individual Power Domain control is not required, power rails can be shared between domains.

On the TE0808-04 TE0807 SoM, following power domains can be powered up individually with power rails available on the B2B connectors:

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See also AMD datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0807 module.

Power-On Sequence

The TE0807

Power-On Sequence

The TE0807 SoM meets the recommended criteria to power up the Xilinx AMD Zynq UltraScale+ MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular Power Domains and powering up the on-board voltages.

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Operation Conditions of the DC-DC Converter Control Signals

Operation Conditions of the DC-DC Converter Control Signals

The control signals have to be asserted on the B2B connector J2, whereby some of the Power-Good signals need external pull-up resistors.

Table 1618: Recommended operation conditions of DC-DC converter control signals.

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It is important that all PS and PL I/Os are tri-stated at power-on until the "Power Good"-signals are high, meaning that all on-module voltages have become stable and module is properly powered up.

See Xilinx AMD datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0808 TE0807 SoM.

Voltage Monitor Circuit

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Power Power Rails

Table 1619: TE0807-01 03 power rails

Bank Voltages

Table 1720: TE0807-01 03 I/O bank voltages

See Xilinx AMD Zynq UltraScale+ datasheet DS925 for the voltage ranges allowed.

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Table 1821: Module absolute maximum ratings

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Table 1922: Recommended operating conditions

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

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• Module size: 52 mm × 76 mm.  Please download the assembly diagram for exact numbers

• Mating height with standard connectors: 4mm5 mm

• PCB thickness: 1.6mm7 mm

• Highest part on PCB: approx. 3mm. Please download the step model for exact numbers

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Hardware Revision History

Table 2023: Hardware revision history table

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Document Change History

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Revision

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Description

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Table 24

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• initial document

Table 21: Document change history

Disclaimer

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