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Table of Contents
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External Bank 2 differential clock connection
TE0600 -02 module have optional connection to FPGA bank 2 differential clock input pins. To provide connection from B2B_B2_L41_P signal to Y13 FPGA pin, zero-resistor R69 should be soldered. To provide connection B2B_B2_L41_N signal to AB13 FPGA pin, zero-resistor R81 should be soldered. Note that in this case optional user oscillator U13 can't be used.
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| Signal FPGA pin | AV3 M18 | AV2 M17 | AV1 V20 | AV0 U19 | Speed grade | SDRAM | Temp grade | Status |
|---|---|---|---|---|---|---|---|---|
| TE0600-02[V|B] | 0 | 0 | 0 | 0 | 2 | 2x128MBit | C | obsolete |
| TE0600-02[V|B]I | 0 | 0 | 0 | 1 | 2 | 2x128MBit | I | obsolete |
| TE0600-02[V|B]F | 0 | 0 | 1 | 0 | 3 | 2x128MBit | C | obsolete |
| TE0600-02[V|B]IF | 0 | 0 | 1 | 1 | 3 | 2x128MBit | I | obsolete |
| TE0600-02[V|B]MF | 0 | 1 | 0 | 0 | 3 | 2x512MBit | C | obsolete |
| TE0600-03[V|B] | 0 | 0 | 0 | 0 | 2 | 2x128MBit | C | full productionobsolete |
| TE0600-03[V|B]I | 0 | 0 | 0 | 1 | 2 | 2x128MBit | I | full productionobsolete |
| TE0600-03[V|B]F | 0 | 0 | 1 | 0 | 3 | 2x128MBit | C | full productionobsolete |
| TE0600-03[V|B]IF | 0 | 0 | 1 | 1 | 3 | 2x128MBit | I | full productionobsolete |
| TE0600-03[V|B]MF | 0 | 1 | 0 | 0 | 3 | 2x512MBit | C | full productionobsolete |
| TE0600-04-52I11 | 0 | 0 | 0 | 1 | 2 | 2x128MBit | I | full production |
| TE0600-04-72C11 | 0 | 0 | 0 | 0 | 2 | 2x128MBit | C | full production |
| TE0600-04-72C21 | 0 | 1 | 0 | 0 | 2 | 2x512MBit | C | full production |
| TE0600-04-83C21 | 0 | 1 | 1 | 0 | 3 | 2x512MBit | C | full production |
| TE0600-04-83I11 | 0 | 0 | 1 | 1 | 3 | 2x128MBit | I | full production |
| TE0600-04-83I21 | 0 | 1 | 1 | 1 | 3 | 2x512MBit | I | full production |
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Date | Revision | Contributors | Description |
|---|---|---|---|
| 2011-10-01 | 0.01 | AIK | Release. |
| 2011-10-05 | 0.02 | AIK | Added B2B pin-out section. |
| 2011-10-06 | 0.03 | AIK | Reformatted pin-out tables. Added eFUSE programming section. |
| 2011-10-06 | 0.04 | AIK | Added board photos. Additions to eFUSE section. |
| 2011-10-06 | 0.05 | AIK | Removed net length information for nets which can't be measured right. |
| 2011-10-06 | 0.06 | AIK | Added power consumption section. |
| 2011-10-08 | 0.07 | AIK | Little fixes after FDR audit. |
| 2011-10-12 | 0.08 | AIK | Fix in eFUSE section. |
| 2011-11-11 | 0.09 | AIK | Added pin numbering description for B2B connectors |
| 2012-01-20 | 0.10 | AIK | Added pin compatibility note and manual reference. |
| 2012-04-12 | 0.11 | AIK | Added FPGA banks VCCIO voltages table. |
| 2012-04-17 | 1.00 | FDR | Updated documentation link. Replaced obsolete ElDesI and RedMine links with current GitHub links. Updated dating convention. |
| 2012-05-18 | 1.01 | AIK | Corrected cross-reference in section 3.2. Corrected LED description. |
| 2012-06-18 | 1.02 | FDR | Removed junction temperature limits under connector current ratings. |
| 2012-07-18 | 1.03 | AIK | Added table with B2B signals summary per FPGA bank |
| 2012-10-30 | 2.01 | AIK | Fork to 01 and 02 board revisions |
| 2012-11-06 | 2.01 | AIK | Fixed bank 1 power options |
| 2012-11-21 | 2.02 | AIK | Updated module diagram |
| 2012-11-30 | 2.03 | AIK | Added Ethernet disable note |
| 2012-12-19 | 2.04 | AIK | Fixed SPI Flash size on block diagram |
| 2013-01-21 | 2.05 | AIK | Added PHY reset note |
| 2013-03-13 | 2.06 | AIK | Connectors current chapter moved to separate document |
| 2013-03-13 | 2.07 | AIK | Changed Bank 1 power supply description and VCCIO0 sources description |
| 2016-01-29 | 2.08 | AIK | Pause advertise correction |
| 2016-11-05 | 3.00 | FDR | Document ported to wiki and adapted to web presentation. |
| 2017-04-03 | TT | Added REV03 to assembly Variant Table | |
| 2024-03-11 | 4.00 | MT | Added REV04 to assembly variant coding table |
| 2024-03-21 | 4.01 | VY | Updated SoM statuses in Assembly variants pin coding Table |
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