TE0600 TRM

Overview

Trenz Electronic GigaBee XC6SLX series are industrial-grade FPGA micromodules integrating a leading-edge Xilinx Spartan-6 LX FPGA, Gigabit Ethernet transceiver (physical layer), two independent banks of 16-bit-wide 128/512 MBytes DDR3 SDRAM, 16 MBytes SPI Flash memory for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via robust board-to-board (B2B) connectors.

All this on a tiny footprint, smaller than half a credit card, at the most competitive price.

Block diagram

Block diagram of the GigaBee XC6SLX board

Main components

Pictures were photographed from revision 3 and serve for informational purposes only.

Top side:

• Xilinx Spartan-6 LX FPGA
• clock generator
• 10/100/1000 Mbps Ethernet PHY
• protected 1-Wire EEPROM
• DDR3-SDRAM
• DC-DC converters

Bottom side:

• B2B connector J1
• B2B connector J2
• Flash memory

Key features

• Industrial-grade Xilinx Spartan-6 LX FPGA micromodule (LX45 / LX100 / LX150)

• 10/100/1000 tri-speed Gigabit Ethernet transceiver (PHY)

• 2 x 16-bit-wide 1 Gb (128 MB) or 4 Gb (512 MB) DDR3 SDRAM

• 128 Mb (16 MB) SPI Flash memory (for configuration and operation) accessible through:

• 1 kb protected 1-Wire EEPROM with SHA-1 Engine

• JTAG port (SPI indirect)

• FPGA configuration through:

  • B2B connector

  • JTAG port

  • SPI Flash memory

• Plug-on module with 2 × 100-pin high-speed hermaphroditic strips

• Up to 52 differential, up to 109 single-ended (+ 1 dual-purpose) FPGA I/O pins available on B2B strips

• 6.0 A x 1.2 V power rail

• 3.0 A x 1.5 V power rail

• 2x 1A x 2.5V power rail

• 125 MHz reference clock signal

• Single-ended custom oscillator (option)

• eFUSE bit-stream encryption (LX100 or larger)

• 1 user LED

• Evenly-spread supply pins for good signal integrity

Additional assembly options are available for cost or performance optimization upon request.

Initial Delivery State

Power Consumption

Power consumption of GigaBee XC6SLX modules highly depend on the FPGA design implemented. Some typical power consumptions are provided below for the following reference systems:

• Boards – GigaBee XC6SLX 45/100/150

• Base board – TE0603-02

• Power supply – 5 V for baseboard

• Connected Gigabit Ethernet cable

Detailed Description

Power Supply

The nominal supply voltage of the GigaBee XC6SLX is 3.3 volt. The minimum supply voltage is 3.0 volt. The maximum supply voltage is 3.45 volt.

Board power supply diagram

Power Supply Sources

GigaBee XC6SLX board must be powered at least in one of the following two ways:

• through B2B connector J1 (pins 1, 3, 5, 7, 9, 11, 13, 15),
• through B2B connector J2 (pins 2, 4, 6, 8, 10, 12).

We recommend to supply the module with all these 14 pins. When one or more of these pins are not power supplied, it or they can be used as power source for user applications.

Please make sure that your logic design does not draw more RMS current per pin than specified in section Board-to-board Connectors.

FPGA banks VCCIO power supply

FPGA VCCIO power options are shown below. Default values for configurable voltages are shown in braces.

Bank 0 power supply VCCIO0 can be configured by user to 3.3 V, 2.5 V or 1.5 V, see Chapter VCCIO0 Power Rail. Banks 1 and 3 VCCIO supply voltage is configured to 1.5 V to communicate with DDR3 SDRAM memory chip.

By special request, modules can be supplied without DDR3 SDRAM chips. Contact Trenz Electronic support for details.

On-board Power Rails

GigaBee XC6SLX has the following power rails on-board.

Table below summarizes power rails information.

Power Supervision

Power-on Reset

During power-on, the /RESET line is first asserted. Thereafter, the supply voltage supervisor monitors the power supply rail 3.3V and keeps the /RESET line active (low) as long as the supply rail remains below the threshold voltage (2.93 volt). An internal timer delays the return of the /RESET line to the inactive state (high) to ensure proper system reset prior to a regular system start-up. The typical delay time td of 200 ms starts after the supply rail has risen above the threshold voltage.

After this delay, the /RESET line is reset (high) and the FPGA configuration can start. When the supply rail voltage drops below the threshold voltage, the /RESET line becomes active (low) again and stays active (low) as long as the rail voltage remains below the threshold voltage (2.93 volt). Once the rail voltage raises again and remains over the threshold voltage for more than the typical delay time td of 200 ms, the /RESET line returns to the inactive state (high) to allow a new system start-up.

Power Fail

GigaBee XC6SLX integrates a power-fail comparator which can be used for low-battery detection, power-fail warning, or for monitoring a power supply other than the main supply 3.3 V. When the voltage of the PFI (power-fail comparator input, input pin 16 of connector J2) line drops below 1.25 volt, the /PFO (power-fail comparator output, FPGA pin A2, label IO_L83P_3) line becomes active (low). The user application can sense this line to take action. To set a power fail threshold higher than 1.25 volt, the user can implement a simple resistive voltage divider on the carrier board.

Board-to-board Connectors

EPROM

GigaBee XC6SLX board contains a Maxim DS2502-E48 node address chip with factory-programmed valid MAC-48 address and 768 bits of OTP-EPROM memory for user data.

Address chip provide convenient data access through 1-Wire interface up to 16.3 kbps (FPGA pin T11).

More information can be found in the Maxim DS2502-E48 product overwiew.

Additional 1Kb protected 1-Wire EEPROM with SHA-1 engine DS2432 accessible via the same line.

More information can be found at the Maxim DS2432 product page.

DDR3 SDRAM Memory

The board contains two 1 Gb (128 MB) or 4 Gb (512 MB) DDR3 SDRAM chips. Data width of each chip is 16 bit. DDR3 memory connected to FPGA bank 1 and FPGA bank 3. Spartan-6 Memory controller Blocks operations can be merged to implement effective 32-bit memory interface. Refer Xilinx XAPP496 for detailed information.

Flash Memory

GigaBee XC6SLX board contains 128 Mb (16 MB) serial flash memory chip Winbond W25Q128FV (W25Q128BV till REV 02) (U11). This serial flash chip can operate as general SPI memory mode and in double or quad modes. Usage of dual and quad modes increase bandwidth up to 40 MB/s.

For more information see Winbond W25Q128JVEIQ (W25Q128BV or W25Q128FV in old revisions) product overview.

Flash can be programmed in several ways:

• Direct SPI programming via J1 connector.
• Indirect SPI programming via FPGA pins, controlled by JTAG.
• Direct SPI programming by FPGA, using SPI core.

Serial flash is connected to FPGA bank 2 and B2B connector J1; used pins are listed in the table below.

Serial flash signals connection

Ethernet

The board contains a Marvell Alaska Ethernet PHY chip (88E1111) operating at 10/100/1000 Mb/s. The board supports GMII interface mode with the FPGA. Configuration details:

• PHY address – 00111
• Do not advertise the PAUSE bit
• Auto Neg
• Advertise all caps
• Prefer slave
• Auto crossover
• 125clk - enabled
• GMII to copper
• Fiber auto-detect - disabled
• Sleep mode - disabled

Ethernet signals from PHY are connected to B2B connector J1. To use Ethernet in your design, GigaBee module should be connected to the carrier board, which have Ethernet magnetics and RJ45 connector. TE0603 carrier board can be used to access Ethernet capabilities of GigaBee XC6SLX series modules.

Oscillators

The module has one 25 MHz oscillator for Ethernet PHY (U9). Ethernet PHY provides clock multiplication and resulting 125 MHz clock acts as a system and user clock for the FPGA (FPGA input pin AA12).

The module also provides additional 3.3 V single-ended oscillator (U12) which can be used as a system and user clock for the FPGA (FPGA input pin Y13).

User LED

The module contains one user active-low LED connected to FPGA output pin T20. To access more LEDs, use a carrier board and drive FPGA signals connected to B2B connectors. As LED connected to FPGA bank with configurable VCCIO to light LED FPGA pin should in '0' (low) state. To disable LED FPGA pin should be in 'Z' (High impedance).

Watchdog

GigaBee XS6LX has a watchdog timer that is periodically triggered by a positive or negative transition of the WDI (watchdog input) line (FPGA pin V9). When the supervising system fails to re-trigger the watchdog circuit within the time-out interval (min 1.1 s, typ 1.6 s, max 2.3 s), the /WDO (watchdog output) line becomes active (low). This event also re-initializes the watchdog timer.

If zero-resistors R2 is not assembled, the watchdog is disabled (alternate assembly).

If zero-resistors R2 is assembled, the watchdog can be enabled (standard assembly). In this case there is still two options:

To enable the watchdog, after module power-up, drive the WDI signal to generate at least one transition (no matter positive or negative).

To keep watchdog disabled, set WDI FPGA signal output to high-impedance. One way to reach this goal is to leave FPGA pin V9 (label IO_L50N_2) undeclared in user constrains file (UCF) and set “unused IOB pins” to “float” in the Xilinx Project Navigator options, see Fig. below.

(Project properties > Configuration options > Unused IOB Pins > Float).

Unused IOB Pins option selection.

In the standard assembly, the /WDO (watchdog output) line is left unconnected1 and the only possibility to reset the module is by driving the /MR (master reset) line active (low) through pin 18 of connector J2.

In the alternate assembly, the /WDO (watchdog output) line is connected through zero-resistor R3 to /MR (master reset) line.

Configuration Options

The FPGA on GigaBee XC6SLX board can be configured by means of the following devices:

• Xilinx download cable (JTAG)
• SPI Flash memory

JTAG Configuration

The FPGA can be configured through the JTAG interface. JTAG signals are connected to B2B connector J2. When GigaBee XC6SLX board is used with the TE0603 carrier board, the JTAG interface can be accessed via connectors J5 and J6 on the carrier board.

Flash Configuration

Default configuration option for FPGA is “Master Serial/SPI”. The bit-stream for the FPGA is stored in a serial Flash chip (U11). See chapter 2.7 Flash Memory for additional information.

eFUSE Programming

eFUSE programming feature is not directly supported by GigaBee XC6SLX modules, but it is possible to use it. To program eFUSE, please follow the steps below:

• Connect VCCAUX to 3.3V power rail.
  On TE0603 it can be done by connecting J5 pin 2 or J6 “VREF” (VCCAUX) to J1 any pin from 1,2,3,4 (3.3V). See Figure below.
• Program eFUSE using JTAG cable and iMPACT software.
• Remove power supply connections to VCCAUX

B2B Connectors Pin Descriptions

This section describes how the various pins on B2B connectors J1 and J2 connects to TE0600 on-board components. There are five main signal types connected to B2B connectors:

• FPGA users signals;
• FPGA system signals;
• Power signals;
• Ethernet PHY signals;
• Other system signals.

B2B signals count

Pin Labeling

FPGA user signals connected to B2B connectors are characterized by the "B2B_Bx_Lyy_p" naming convention, where:

• B2B defines a "FPGA to B2B" signal type;
• Bx defines the FPGA bank (x = bank number);
• Lyy defines a differential pair or signal number (yy = pair number);
• p defines a differential signal polarity (P = positive, N = negative); single ended signals do not have this field.

Ethernet PHY signals use "PHY_name" naming conversions where "PHY" defines signal type "PHY to B2B" and "name" is PHY signal name.

Remaining signals use custom names.

Pin Numbering

Note that GigaBee XC6SLX have hermaphroditic B2B connectors. A feature of  hermaphroditic connector numbering is that connected signal numbers don't match. Odd signals on module connect to even signals on baseboard. For example module signal 1 to baseboard signal 2, module signal 2 to baseboard signal 1, module signal 3 to baseboard signal 4 and so on.

Pin Types

Most pins of B2B connectors J1 and J2 are general-purpose, user-defined I/O pins (GPIOs). There are, however, up to 8 different functional types of pins on the TE0600, as outlined in Table below. In pin-out tables Table 11 and Table 12, the individual pins are colour-coded according to pin type as in Table below.

TE0600 pin types

Note that some of Spartan-6 I/O types are partially compatible, so pins of compatible types can be used as inputs for signal of other type. For example pins from FPGA bank with 1.5V VCCO (IOSTANDARD = LVCMOS15) can be used as inputs for 1.2V, 1.8V, 2.5V and 3.3V signals.

See “Spartan-6 FPGA SelectIO Resources” page 38 for detailed information.

External Bank 2 differential clock connection

TE0600-02 module have optional connection to FPGA bank 2 differential clock input pins. To provide connection from B2B_B2_L41_P signal to Y13 FPGA pin, zero-resistor R69 should be soldered. To provide connection B2B_B2_L41_N signal to AB13 FPGA pin, zero-resistor R81 should be soldered. Note that in this case optional user oscillator U13 can't be used.

J1 Pin-out

J1 pin-out

J2 Pin-out

J2 Pin-out

Signal Integrity Considerations

Traces of differential signals pairs are routed symmetrically (as symmetric pairs).

Traces of differential signals pairs are NOT routed with equal length, although difference in signal lines length is negligible for actual signal frequencies. For applications where traces length has to be matched or timing differences have to be compensated, Tables abowe list the trace length of I/O signal lines measured from FPGA balls to B2B connector pins.

Traces of differential signals pairs are routed with a differential impedance between the two traces of 100 ohm. Single ended traces are routed with 60 ohm impedance.

An electronic version of these pin-out tables are available for download from the Trenz Electronic support area of the web site.

Module revisions and assembly variants

Module revision coded by 4 FPGA BR[3:0] pins, which can be read by FPGA firmware. All these pins should be configured to have internal PULLUP.

Board revisions pin coding

Main differences between 01 and 02 revisions:

• More powerful regulators for 1.2V and 1.5V rails
• VCCAUX separated from 2.5V power rail
• 128Mbit SPI Flash
• Additional secure 1Kbit EEPROM
• Optional B2B connection to bank 2 differential clock input

Main differences between 02 and 03 revisions:

• Optimized placement and routing for DC/DC converters
• Added thermal vias to mounting holes
• Added Testpoints
• Changed Board revision identification to REV03
• Changed U9 from SIT1602AI-83-33E-25.0000 to SiT8008AI-73-XXS-25.000000E
• Added Track-it™ Traceability Pad
• Change SPI Flash from W25Q128BVEIG to W25Q128FVEIG
• DDR3 changed from IM4G16D3EABG-125I to IM4G16D3FABG-125I for the 4 GBit variants
• U13 (DS2432P+) is no longer populated by default

Main differences between 03 and 04 revisions:

• Optimized placement and routing
• More powerful regulators
• Removed stucked vias
• Added Testpoints
• Changed Board revision identification to REV04
• U12 was fitted for all module assembly variants as default

Module assembly variants coded by 4 zero ohm resistors, connected to FPGA AV[3:0] pins. All these pins should be configured to have internal PULLUP.

Assembly variants pin coding

Related Materials and References

The following documents provide supplementary information useful with this user manual.

Data Sheets

• Xilinx DS160: Spartan-6 Family Overview
  This overview outlines the features and product selection of the Spartan®-6 family.
  http://www.xilinx.com/support/documentation/data_sheets/ds160.pdf

• Xilinx DS162: Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
  This data sheet contains the DC and switching characteristic specifications for the Spartan®-6 family.
  http://www.xilinx.com/support/documentation/data_sheets/ds162.pdf

• Samtec Razor Beam LSHM series overview.
  http://www.samtec.com/LSHM

• Maxim DS2502-E48 product overview.
  http://www.maxim-ic.com/datasheet/index.mvp/id/3748

• Winbond W25Q128BV product overview.
  http://www.winbond.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/SerialFlash/W25Q128BV.htm

• Maxim DS2432 product page.
  http://www.maximintegrated.com/datasheet/index.mvp/id/2914

Documentation Archives

• Xilinx Spartan-6 Documentation
  http://www.xilinx.com/support/documentation/spartan-6.htm

• Xilinx Documentation
  http://www.xilinx.com/documentation/
  http://www.xilinx.com/support/documentation/

• Trenz Electronic GigaBee Series Documentation
  http://docs.trenz-electronic.de/Trenz_Electronic/products/TE0600-GigaBee_series/

User Guides

• Xilinx UG380: Spartan-6 FPGA Configuration User Guide
  This all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques.
  http://www.xilinx.com/support/documentation/user_guides/ug380.pdf

• Xilinx UG381: Spartan-6 FPGA SelectIO Resources
  http://www.xilinx.com/support/documentation/user_guides/ug381.pdf

Design and Development Tools

• Xilinx ISE Design Suite
  http://www.xilinx.com/ISE/
  http://www.xilinx.com/tools/designtools.htm

• Xilinx ISE Design Suite (version archive)
  http://www.xilinx.com/download/
  http://www.xilinx.com/support/download/

• Xilinx ISE WebPACK
  http://www.xilinx.com/tools/webpack.htm
  http://www.xilinx.com/webpack/

Design Resources

• Trenz Electronic GigaBee Design Resources
  https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/TE0600

• Trenz Electronic GigaBee Reference Designs
  https://github.com/Trenz-Electronic/
  https://github.com/Trenz-Electronic/TE-EDK-IP/
  https://github.com/Trenz-Electronic/TE060X-GigaBee-Reference-Designs/

Tutorials

• Xilinx UG695: ISE In-Depth Tutorial
  Chapter 8: Configuration Using iMPACT
  http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/ise_tutorial_ug695.pdf

Glossary of Abbreviations and Acronyms

	A WARNING notice denotes a hazard. It calls attention to an operating procedure, practice, or the like that, if not correctly performed or adhered to, could result in damage to the product or loss of important data. Do not proceed beyond a WARNING notice until the indicated conditions are fully understood and met.
	A CAUTION notice denotes a risk. It calls attention to an operating procedure, practice, or the like that, if not correctly performed or adhered to, could result in a fault. (undesired condition that can lead to an error) Do not proceed beyond a CAUTION notice until the indicated conditions are fully understood and met.
API	application programming interface
B2B	board-to-board
DSP	digital signal processing; digital signal processor
EDK	Embedded Development Kit
IOB	input / output blocks; I/O blocks
IP	intellectual property
ISP	In-System Programmability
OTP	one-time programmable
PB	push button
SDK	Software Development Kit
TE	Trenz Electronic
XPS	Xilinx Platform Studio

Mechanical Dimensions

GigaBee XC6SLX can reach a minimum vertical height of about 8 mm, if B2B connectors are not assembled. The maximum component height on the module board on the top side is about 3.5 mm. The maximum component height on the module board on the bottom side is about 3.0 mm.

The typical minimum and maximum height from the carrier board surface, of a GigaBee XC6SLX when it mounted on a carrier board, is respectively about 5.0 mm and about 13 mm.

GigaBee XC6SLX has 4 mounting holes, one in each corner. The module can be fixed by screwing M3 screws (ISO 262) onto a carrier board through those mounting holes.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Weight

GigaBee XC6SLX weighs between 17.1 and 17.3 g with standard connectors.

Document Change History

Date	Revision	Contributors	Description
2011-10-01	0.01	AIK	Release.
2011-10-05	0.02	AIK	Added B2B pin-out section.
2011-10-06	0.03	AIK	Reformatted pin-out tables. Added eFUSE programming section.
2011-10-06	0.04	AIK	Added board photos. Additions to eFUSE section.
2011-10-06	0.05	AIK	Removed net length information for nets which can't be measured right.
2011-10-06	0.06	AIK	Added power consumption section.
2011-10-08	0.07	AIK	Little fixes after FDR audit.
2011-10-12	0.08	AIK	Fix in eFUSE section.
2011-11-11	0.09	AIK	Added pin numbering description for B2B connectors
2012-01-20	0.10	AIK	Added pin compatibility note and manual reference.
2012-04-12	0.11	AIK	Added FPGA banks VCCIO voltages table.
2012-04-17	1.00	FDR	Updated documentation link. Replaced obsolete ElDesI and RedMine links with current GitHub links. Updated dating convention.
2012-05-18	1.01	AIK	Corrected cross-reference in section 3.2. Corrected LED description.
2012-06-18	1.02	FDR	Removed junction temperature limits under connector current ratings.
2012-07-18	1.03	AIK	Added table with B2B signals summary per FPGA bank
2012-10-30	2.01	AIK	Fork to 01 and 02 board revisions
2012-11-06	2.01	AIK	Fixed bank 1 power options
2012-11-21	2.02	AIK	Updated module diagram
2012-11-30	2.03	AIK	Added Ethernet disable note
2012-12-19	2.04	AIK	Fixed SPI Flash size on block diagram
2013-01-21	2.05	AIK	Added PHY reset note
2013-03-13	2.06	AIK	Connectors current chapter moved to separate document
2013-03-13	2.07	AIK	Changed Bank 1 power supply description and VCCIO0 sources description
2016-01-29	2.08	AIK	Pause advertise correction
2016-11-05	3.00	FDR	Document ported to wiki and adapted to web presentation.
2017-04-03		TT	Added REV03 to assembly Variant Table
2024-03-11	4.00	MT	Added REV04 to assembly variant coding table Added REV04 to revision coding table Added main differences between 03 and 04 revisions Updated nets lengths table Added info about additional 3.3V single-ended oscillator (U12) Updated supply diagram Updated block diagram

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