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The Trenz Electronic TE0823 -01-3PIU1FL is (3PIU1FA /3PIU1FL) is an industrial-grade MPSoC module integrating a low power Xilinx Zynq UltraScale+ ZU3CG, 1 GByte LPDDR4 SDRAM, 128 MByte Flash memory for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking connections.

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SoC/FPGA
- Xilinx Zynq UltraScale+ XCZU3CG-L1SFVC784I
  - Application Processor: Dual-core ARM Cortex-A53 MPCore
  - Real-Time Processor: Dual-core ARM Cortex-R5 MPCore
- Package: SFVC784
- Device: ZU3
- Engine: CG
- Speed: -1LI (also non-low power assembly options possible)
- Temperature range: industrial
RAM/Storage
- Low power DDR4 on PS with 32 bit data width
- 128 MByte QSPI boot Flash in dual parallel mode
- 8 GByte e.MMC memory with 8 bit data width
- MAC address serial EEPROM with EUI-48 node identity
On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY
- Hi-speed USB2 ULPI transceiver with full OTG support
Interface
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, SATA, PCIe, DP)
  Four high-speed serial I/O (HSSIO) interfaces supporting following protocols:
  - PCI Express interface version 2.1 compliant
  - SATA 3.1 specification compliant interface
  - DisplayPort source-only interface with video resolution up to 4k x 2k
  - USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
  - 1 GB/s serial GMII interface
- 14 x PS MIOs
  - MIO for UART
  - thereof 6 MIO for SD card interface (default configuration)
  - MIO for PJTAG
- JTAG
- Ctrl
Power
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, SATA, PCIe, DP)
  Four high-speed serial I/O (HSSIO) interfaces supporting following protocols:
  - PCI Express interface version 2.1 compliant
  - SATA 3.1 specification compliant interface
  - DisplayPort source-only interface with video resolution up to 4k x 2k
  - USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
  - 1 GB/s serial GMII interface
- 14 x PS MIOs
  - MIO for UART
  - thereof 6 MIO for SD card interface (default configuration)
  - MIO for PJTAG
- JTAG
- Ctrl
Dimension
- 4 x 5 cm
Notes
- Rugged for shock and high vibration
- Evenly spread supply pins for good signal integrity
- Plug-on module with 2 x 100 pin and 1 x 60 pin Razor Beam High-Speed hermaphroditic Terminal/Socket Strips (low profile, 2,5 mm)

Block Diagram

- 3.3V-5V main input
- 3.3V controller input
- Variable bank I/O power input
- All power supplies on board
Dimension
- 4 x 5 cm
Notes
- Rugged for shock and high vibration
- Evenly spread supply pins for good signal integrity
- Plug-on module with 2 x 100 pin and 1 x 60 pin Razor Beam High-Speed hermaphroditic Terminal/Socket Strips (low profile, 2,5 mm)

Block Diagram

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add drawIO object here.

Note
For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .

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title	Reset process.

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Signal	B2B	I/O	Note
EN	JM1-28	Input	CPLD Enable Pin

Signals, Interfaces and Pins

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On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 chip. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an on-board 25MHz oscillator (U11), the 125MHz output clock is left unconnected.oscillator (U11), the 125MHz output clock is left unconnected.

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anchor	Table_SIP_ETH
title	GigaBit Ethernet connection

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Pin	Schematic	Connected to
MDIP0...3	PHY_MDI0...3	B2B, JM1
MDC	ETH_MDC	MIO76
MDIO	ETH_MDIO	MIO77
S_IN	S_IN	B2B, JM3
S_OUT	S_OUT	B2B, JM3
TXD0..3	ETH_TXD0...3	MIO65...68
TX_CTRL	ETH_TXCTL	MIO69
TX_CLK	ETH_TXCK	MIO64
RXD0...3	ETH_RXD0...3	MIO71...74
RX_CTRL	ETH_RXCTL	MIO75
RX_CLK	ETH_RXCK	MIO70
LED0...2	PHY_LED0...2	FPGA Bank 66
RESETn	ETH_RST	MIO24

System Controller CPLD

Special purpose pins are connected to System Controller CPLD and have following default configuration:

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anchor	Table_SIP_ETHCPLD
title	GigaBit Ethernet connectionSystem Controller CPLD special purpose pins

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Schematic

Connected to

Note

MDIP0...3

PHY_MDI0...3

B2B, JM1

MDC

ETH_MDC

MIO76

MDIO

ETH_MDIO

MIO77

S_IN

B2B, JM3

S_OUT

B2B, JM3

TXD0..3

ETH_TXD0...3

MIO65...68

TX_CTRL

ETH_TXCTL

MIO69

TX_CLK

ETH_TXCK

MIO64

RXD0...3

ETH_RXD0...3

MIO71...74

RX_CTRL

ETH_RXCTL

MIO75

RX_CLK

ETH_RXCK

MIO70

LED0...2

PHY_LED0...2

FPGA Bank 66

RESETn

ETH_RST

MIO24

System Controller CPLD

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Pin Name	Mode	Function	Default Configuration
EN1	Input	Power Enable	No hard wired function on PCB. When forced low, PGOOD goes low without effect on power management
PGOOD	Output	Power Good	Only indirect used for power status, see CPLD description
NOSEQ	-	-	No used for Power sequencing, see CPLD description
RESIN	Input	Reset	Active low reset, gated to POR_B
JTAGEN	Input	JTAG Select	Low for normal operation, high for CPLD JTAG access

USB Interface

USB PHY is provided by Microchip USB3320. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V. Reference clock input for the USB PHY is supplied by the on-board 52.00 MHz oscillator (U14).Special purpose pins are connected to System Controller CPLD and have following default configuration:

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anchor	Table_SIP_CPLD
title	System Controller CPLD special purpose pins

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Pin Name

Mode

Function

Default Configuration

EN1

Input

Power Enable

No hard wired function on PCB. When forced low, PGOOD goes low without effect on power management

PGOOD

Output

Power Good

Only indirect used for power status, see CPLD description

NOSEQ

-

No used for Power sequencing, see CPLD description

RESIN

Input

Reset

Active low reset, gated to POR_B

JTAGEN

Input

JTAG Select

Low for normal operation, high for CPLD JTAG access

USB Interface

USB PHY is provided by Microchip USB3320. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V. Reference clock input for the USB PHY is supplied by the on-board 52.00 MHz oscillator (U14).

USB
title	General overview of the USB PHY signals

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PHY Pin	ZYNQ Pin	B2B Name	Notes
ULPI	MIO52..63	-	Zynq USB0 MIO pins are connected to the USB PHY.
REFCLK	-	-	52.000000 MHz from on-board oscillator (U14).
REFSEL[0..2]	-	-	Reference clock frequency select, all set to GND selects 52.000000 MHz.
RESETB	MIO25	-	Active low reset.
CLKOUT	MIO52	-	Connected to 1.8V, selects reference clock operation mode.
DP, DM	-	OTG_D_P, OTG_D_N	USB data lines routed to B2B connector JM3 pins 47 and 49.
CPEN	-	VBUS_V_EN	External USB power switch active high enable signal, routed to JM3 pin 17.
VBUS	-	USB_VBUS	Connect to USB VBUS via a series of resistors, see reference schematics, routed to JM3 pin 55.
ID	-	OTG_ID	For an A-device connect to ground, for a B-device left floating. routed from JM3 pin 23.

2C Interface

On-board I²C devices are connected to MIO38 (SCL) and MIO39 (SDA) which are configured as I²C0 by default. Addresses for on-board I²C slave devices are listed in the table below:

For an A-device connect to ground, for a B-device left floating. routed from JM3 pin 23.

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title	Address table of the I2C bus slave devices

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I2C Device	I2C Address	Notes
Si5338A PLL	0x70	-
EEPROM	0x50	-

Scroll Title

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title	General overview of the USB PHY signals

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PHY Pin

ZYNQ Pin

B2B Name

Notes

ULPI

MIO52..63

-

Zynq USB0 MIO pins are connected to the USB PHY.

REFCLK

-

52.000000 MHz from on-board oscillator (U14).

REFSEL[0..2]

-

Reference clock frequency select, all set to GND selects 52.000000 MHz.

RESETB

MIO25

-

Active low reset.

CLKOUT

MIO52

-

Connected to 1.8V, selects reference clock operation mode.

DP, DM

-

OTG_D_P, OTG_D_N

USB data lines routed to B2B connector JM3 pins 47 and 49.

CPEN

-

VBUS_V_EN

External USB power switch active high enable signal, routed to JM3 pin 17.

VBUS

-

USB_VBUS

Connect to USB VBUS via a series of resistors, see reference schematics, routed to JM3 pin 55.

ID

-

OTG_ID

Trenz Electronic Documentation

Versions Compared

Old Version 9

New Version 10

Key

Block Diagram

Block Diagram

Signals, Interfaces and Pins

System Controller CPLD

System Controller CPLD

USB Interface

USB Interface

2C Interface

MIO Pins