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Scroll Title
anchorTable_OV_IDS
titleInitial delivery state of programmable devices on the module

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
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sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Storage device name

Content

Notes

2x SPI Flash

Not Programmed


System Controller CPLDProgrammed
EEPROMProgrammed
4x DDR4Not Programmed
Programmable Clock GeneratorNot Programmed


Configuration Signals

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Scroll Title
anchorTable_OV_BP
titleBoot process.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

MODE[0:3]

Boot ModePin LocationNote

0000

PS_JTAG

JTAGPSJTAG Interface
0001Quad SPI (24b)MIO0...12QSPI 24bit addressing
0010Quad SPI (32b)MIO0...12QSPI 32bit addressing
0011SD0 2.0MIO13...25SD 2.0
0100NANDMIO9...25Requires 8 bit data bus width
0101SD1 2.0MIO31...51SD 2.0
0110eMMCMIO13...22eMMC version 4.5 at 1.8 V
0111USB2.0MIO52...63Only USB2.0
1000PJTAGMIO26...29PJTAG Connection 0 0ption
1001PJTAGMIO12...15PJTAG Connection 1 0ption
1110SD1 LS 3.0MIO39...51SD 3.0 with complaint voltage level shifter


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