The Trenz Electronic TE0835 is an extended-grade module based on Xilinx Zynq UltraScale+ RFSoC. The module is equipped with 4x 8Gb DDR4 SDRAM Memory, 2x 512Mb SPI Flash Memory, USB2.0, Ethernet Transceiver and 2x Samtec Razor Beam Borard to Board (B2B) Connectors. The system controller CPLD is provided by Lattice MachXO2.
The Zynq UltraScale+ RFSoC family integrates key subsystems for multiband, multi-mode cellular radios and cable infrastructure (DOCSIS) into an SoC platform that contains a feature-rich 64-bitquad-core Arm Cortex-A53 and dual-core Arm Cortex-R5 based processing system.
Refer to http://trenz.org/te0835-info for the current online version of this manual and other available documentation.
- Package: FFVE1156, FSVE1156
- Device: ZU25, ZU27, ZU28, ZU42, ZU43, ZU47, ZU48*
- Engine: DR
- Speed: -1, -L1, -2, -L2
- Temperature: E, I*
- 4x 8Gb DDR4
- 2x 512Mb SPI Flash
- 2k I2C EEPROM
- On Board
- Lattice MachXO2 CPLD
- Programmable Clock Generator
- USB2.0 Transceiver
- Gigabit Ethernet Transceiver
- 3x Oscillators
- 4x User LEDs
- 2x Samtec Razor Beam ST5 (2x80 pol) Board to Board Connectors
- 5V Input Supply Voltage
- 90 x 65 mm
- * Different packages, speed and temperature range are available on assembly options
- Xilinx UltraScale+ RFSoC, U1
- 8Gb DDR4 SDRAM, U2,U3,U5,U9
- Voltage Regulators, U4,U6,U7
- User Red LEDs, D2...5
- Error/Status Red LEDs, D6...7
- Programmable Glock Generator, U15
- Lattice MachXO2 CPLD, U31
- Dual SPI Flash, U24-U25
- USB2.0 Transceiver, U11
- Pin Header 3x1, J3 (not Soldered)
- Green LED, D1
- Gigabit Ethernet Transceiver, U20
- EEPROM, U23
- B2B Connectors, J1
- B2B Connectors, J2
Initial Delivery State
Storage device name
2x SPI Flash
|System Controller CPLD||Programmed|
|4x DDR4 SDRAM||Not Programmed|
|Programmable Clock Generator||Not Programmed|
Configuration must be set through CPLD,U31 by setting MODE0...3 signals.
|Refer to CPLD Page|
|0001||Quad SPI Flash||Refer to CPLD Page|
|0101||SD Card||Refer to CPLD Page|
The reset pin is active low.
|J1-36||Input||Pulled up to 3.3V_CPLD|
Signals, Interfaces and Pins
Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
|FPGA Bank||B2B Connector||Number of I/Os||Voltage Level||Notes|
|Bank 500||J1||12x Single Ended||1.8V||MIO14...25|
|Bank 501||J1||20x Single Ended||1.8V||MIO26...51|
|Bank 505||J1||18x Single Ended, 9x Differential pairs||0.85V||EXT_CLKIN_PSMGT, RX/TX0...3|
2x Differnetial CLK Input,
8x Differential Transceiver
2x Differnetial CLK Input
8x Differential Transceiver
|Bank 65||J2||24x Single Ended, 12x Differential pairs||1.8V||HP Bank|
|Bank 88||J2||16x Single Ended, 8x Differential pairs||3.3V||HD Bank|
16x Single Ended, 8x Differential pairs
4x Differential Clocks
16x Single Ended, 8x Differential pairs
3x Differential Clocks
JTAG access to the Xilinx UltraScale+ MPSoC is through B2B connector JM1. JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on B2B. When the CPLD_JTAGEN is 0 or off, it provides FPGA access and when it is 1 or ON, it provides CPLD access.
|MIO Pin||Connected to||B2B||Notes|
|MIO0...12||SPI FLash, U24-U25||-||Dual SPI FLash|
|MIO13||LED Green, D1||-||3.3V_CPLD|
|MIO14...25||FPGA Bank 500,U1||J1||PSMIO|
|MIO26...27||FPGA Bank 501,U1||J1||PSMIO|
|MIO30...31||FPGA Bank 501, U1||J1||PSMIO|
|MIO34...35||FPGA Bank 501,U1||J1||PSMIO|
|MIO36||Gigabit ETH, U20||-||ETH_RST|
|MIO38...51||FPGA Bank 501, U1||J1||PSMIO|
|MIO63...77||Gigabit ETH, U20||-||ETH|
|Test Point||Signal||Connected to||Notes|
|TP1||CLKOUT||Voltage Regulator, U7|
|TP2||PLL_RSTN||Programmable Clock Generator, U15|
|FPGA Bank 88, U1|
FPGA Bank 501, U1
|TP18||ADC_AVCC||LDO Voltage Regulator, U8|
|TP19||ADC_AVCCAUX||LDO Voltage Regulator, U10|
Quad SPI Flash Memory
The TE0835 is a Dual SPI Flash module equipped with two SPI Flash U24, U25 connecfted to PSMIO FPGA bank 500.
|MIO Pin||Schematic||U24 Pin||U25 Pin||Notes|
System Controller CPLD
The System Controller CPLD (U31) is provided by Lattice Semiconductor LCMXO2-460HC. The CPLD provides JTAG routing, boot mode, User IOs, LEDs, firmware and power management access. For more information please refer to the TE0835 CPLD page.
|MODE0...3||FPGA Bank 503, U1||Boot Mode|
|POR_B||FPGA Bank 503, U1||Programming Status||Pulled up|
|PORG_B||FPGA Bank 503, U1||Programming Status||Pulled up|
|INIT_B||FPGA Bank 503, U1||Configuration initialization||Pulled up|
|DONE||FPGA Bank 503, U1||Configuration Done Status||Pulled up|
|F_TCK||FPGA Bank 503, U1||FPGA JTAG|
|F_TDI||FPGA Bank 503, U1||FPGA JTAG|
|F_TMS||FPGA Bank 503, U1||FPGA JTAG|
|F_TDO||FPGA Bank 503, U1||FPGA JTAG|
|JTAG_TDO||B2B, J1||CPLD JTAG|
|JTAG_TMS||B2B, J1||CPLD JTAG|
|JTAG_TDI||B2B, J1||CPLD JTAG|
|JTAG_TCK||B2B, J1||CPLD JTAG|
|CPLD_JTAGEN||B2B, J1||CPLD JTAG Enable|
|CPLDIO0...3||B2B, J1||CPLD IOs|
|MIO13||LED Green, D1||3.3V_CPLD|
|MIO28||FPGA Bank 501, U1||UART_TX|
|MIO29||FPGA Bank 501, U1||UART_RX|
|FPGA_IO0...1||FPGA Bank 65, U1||IOs|
|EN_PS_PL||Voltage Regulators, U6, U7, U29||PS/PL Enable Signals||Pulled Down|
|EN_GR1||Voltage Regulators, U19, U27, U28||MGTAVTT, PSLL||Pulled Down|
|EN_GR2||Voltage Regulators, U38, U18, U38||PS_MGTRAVTT, 3.3, DDR2.5V||Pulled Down|
|EN_RF_ADC||Voltage Regulators, U8||Enable ADC||Pulled Down|
|PG_RF_DAC||Voltage Regulators, U17||ADC Power Good Status||Pulled Down|
|PG_PS_PL||Voltage Regulators, U6, U7, U29||PS/PL Power Good Status||Pulled Down|
|EN_RF_DAC||Voltage Regulators, U13||Enable DAC||Pulled Down|
|PG_RF_DAC||Voltage Regulators, U10||DAC Power Good Status||Pulled Down|
The TE0835 is equipped with a USB2.0, U11.
|U11 Pin||Schematic||Connected to||Notes|
|RESETB||USB0_RST||FPGA Bank 501, U1|
|STP||USB0_STP||FPGA Bank 502, U1|
|NXT||USB0_NXT||FPGA Bank 502, U1|
|DIR||USB0_DIR||FPGA Bank 502, U1|
|DATA0...7||USB0_DATA0...8||FPGA Bank 502, U1|
The module TE0835 is equipped with a Gigabit Ethernet Transceiver, U20.
|U20 Pin||Signal Name||Connected to||Signal Description||Note|
|MDIO||ETH_MDIO||FPGA Bank 502, U1||Data Management|
|MDC||ETH_MDC||FPGA Bank 502, U1||Data Management clock reference for the serial interface|
|TX_CLK||ETH_TXCK||FPGA Bank 502, U1||Transmit Clock|
|TX_CTRL||ETH_TXCTL||FPGA Bank 502, U1||Transmit Control|
|TXD0...3||ETH_TXD0...3||FPGA Bank 502, U1||Transmit Data|
|RX_CLK||ETH_RXCK||FPGA Bank 502, U1||Receive Clock|
|RX_CTRL||ETH_RXCTL||FPGA Bank 502, U1||Receive Control|
|RXD0...3||ETH_RXD0...3||FPGA Bank 502, U1||Receive Data|
|RESETn||ETH_RST||FPGA Bank 501, U1||Ethernet reset, Active low.|
|XTAL_IN||ETH_XTAL_IN||Oscillator, U21||Reference Clock|
|PHY_MDI0...3||B2B, J1||Media Dependent Interface 0...3|
|LED0...1||PHY_LED0...1||B2B, J1||LED output|
|LED/INT||PHY_LED2||B2B, J1||LED interrupt|
The module TE0835 has an EEPROM IC (U23) connected to PSMIO FPGA Bank 501.
|MIO Pin||Schematic||U23 Pin||Notes|
|MIO Pin||I2C Address||Designator||Notes|
|Designator||Color||Connected to||Active Level||Note|
|D1||Green||MIO13||Active High||3.3V CPLD|
|D2...5||Red||DBG_LED0...3||Active Low||User LED|
The TE0835 SoM has 4x 1 Gigabyte volatile DDR4 SDRAM IC for storing user application code and data.
- Part number: K4A8G165WB
- Supply voltage: 1.2 V
Speed: 2400 Mbps
Temperature: -40 ~ 95 °C
|U14, U21||MEMS Oscillator||25MHz|
|U22||MEMS Oscillator||33.33 MHz|
|Y1||Crystal Oscillator||54 MHz|
|U15||Programmable Clock Generator||Variable|
Programmable Clock Generator
There is a Silicon Labs I2C programmable clock generator on-board (U10) in order to generate reference clocks for the module. Programming can be done using I2C via PIN header J3. The I2C Address is 0x69.
|U15 Pin||Signal||Connected to||Direction||Note|
|FPGA Bank 65,U1||Input|
|SCL||MIO32_I2C1_SCL||Pin Header, J3||Input||I2C|
|SDA||MIO33_I2C1_SDA||Pin Header, J3||Input||I2C|
|OUT6||B128_CLK0||FPGA Bank 128,U1||Output|
|OUT7||B129_CLK0||FPGA Bank 129,U1||Output|
|OUT8||CLK8||FPGA Bank 65,U1||Output|
|OUT9||PSMGT_100MHZ||FPGA Bank 505,U1||Output|
Power and Power-On Sequence
Power supply with minimum current capability of 2.5A for system startup is recommended.
|Power Input Pin||Typical Current|
* TBD - To Be Determined
Power Distribution Dependencies
|Power Rail Name|
B2B J1 Pin
B2B J2 Pin
|Bank 65 HP||VCCO_65||1.8V|
|Bank 503 PSCONFIG|
|Bank 88 HD||VCCO_88||3.3V|
|Bank 128 GTY||MGTAVCC||0.9V|
|Bank 129 GTY||MGTAVCC||0.9V|
|Bank 500 PSMIO||VCCO_PSIO0_500||1.8V|
|Bank 501 PSMIO||VCCO_PSIO0_501||1.8V|
|Bank 504 PSDDR||VCCO_PSDDR_504||1.2V|
|Bank 505 PSGTR||PS_MGTRAVCC||0.85V|
Board to Board Connectors
Absolute Maximum Ratings
|VIN||Input Supply Voltage||0||5||V|
Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
See USB2.0 Datasheet
Module size: 90 mm × 65 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 7 mm.
PCB thickness: 1.65 mm.
Currently Offered Variants
Hardware Revision History
1. Added a VRP resistor on bank 65;
2. LDO U33 is changed on ADP7102ACPZ;
3. Signal FPGA IO0 is connected on AE18 pin of FPGA;
4. Signal DBG_LED3 is connected on AD18 pin of FPGA;
5. Signal MIO13_25 connected to J1 pin 33 instead MIO25.
6. Resistor R84 is removed;
7. LED D1 moved on edge of PCB;
8. Added THT testpoints J4 on CPLD_JTAGEN, R76 was removed;
9. Signals B49_XX_X are renamed in B88_XX_X;
10. C241 is changed on 1nF;
11. Length of CLK signals on RFADC and RFDAC are adjusted;
12. Wrong connection on U8 is fixed (PCB);
13. Wrong connection PGOOD1 pin of U7 is fixed;
14. R17 is changed from 35,5K to 33K for VCC_PL_PS correction.
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
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