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Overview

The Trenz Electronic TE0835 is an extended-grade module based on Xilinx Zynq UltraScale+ RFSoC.  The module is equipped with 4x 8Gb DDR4 SDRAM Memory, 2x 512Mb SPI Flash Memory, USB2.0, Ethernet Transceiver and 2x Samtec Razor Beam Borard to Board (B2B) Connectors. The system controller CPLD is provided by Lattice MachXO2.

The Zynq UltraScale+ RFSoC family integrates key subsystems for multiband, multi-mode cellular radios and cable infrastructure (DOCSIS) into an SoC platform that contains a feature-rich 64-bitquad-core Arm Cortex-A53 and dual-core Arm Cortex-R5 based processing system. 

Refer to http://trenz.org/te0835-info for the current online version of this manual and other available documentation.


Key Features

  • SoC/FPGA
    • Package: FFVE1156, FSVE1156
    • Device: ZU25, ZU27, ZU28, ZU42, ZU43, ZU47, ZU48*
    • Engine: DR
    • Speed: -1, -L1, -2, -L2
    • Temperature: E, I*
  • RAM/Storage
    • 4x 8Gb DDR4 
    • 2x 512Mb SPI Flash
    • 2k I2C EEPROM
  • On Board
    • Lattice MachXO2  CPLD
    • Programmable Clock Generator
    • USB2.0 Transceiver
    • Gigabit Ethernet Transceiver
    • 3x Oscillators
    • 4x User LEDs
  • Interface
    • 2x Samtec Razor Beam ST5 (2x80 pol) Board to Board Connectors
  • Power
    • 5V Input Supply Voltage
  • Dimension
    • 90 x 65 mm
  • Note
    • * Different packages, speed and temperature range are available on assembly options

Block Diagram


TE0835 block diagram

Main Components

TE0835 main components
  1. Xilinx UltraScale+ RFSoC, U1
  2. 8Gb DDR4 SDRAM, U2,U3,U5,U9
  3. Voltage Regulators, U4,U6,U7
  4. User Red LEDs, D2...5
  5. Error/Status Red LEDs, D6...7
  6. Programmable Glock Generator, U15
  7. Lattice MachXO2 CPLD, U31
  8. Dual SPI Flash, U24-U25
  9. USB2.0 Transceiver, U11
  10. Pin Header 3x1, J3 (not Soldered)
  11. Green LED, D1
  12. Gigabit Ethernet Transceiver, U20
  13. EEPROM, U23
  14. B2B Connectors, J1
  15. B2B Connectors, J2

Initial Delivery State

Storage device name

Content

Notes

2x SPI Flash

Not Programmed


System Controller CPLDProgrammed
EEPROMNot Programmed
4x DDR4 SDRAMNot Programmed
Programmable Clock GeneratorNot Programmed
Initial delivery state of programmable devices on the module

Configuration Signals

Configuration must be set through CPLD,U31 by setting MODE0...3 signals.

MODE[3:0]

Boot ModeNote

0000

PS_JTAG

Refer to CPLD Page
0001Quad SPI FlashRefer to CPLD Page
0101SD CardRefer to CPLD Page
Boot process.

The reset pin is active low.

Signal

B2BI/ONote

RESETN

J1-36InputPulled up to 3.3V_CPLD
Reset process.

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

FPGA BankB2B ConnectorNumber of I/OsVoltage Level Notes
Bank 500J112x Single Ended1.8VMIO14...25
Bank 501J120x Single Ended1.8VMIO26...51
Bank 505J118x Single Ended, 9x Differential pairs0.85VEXT_CLKIN_PSMGT, RX/TX0...3
Bank 128J118x Single Ended, 9x Differential pairs0.9VB128_CLK, RX/TX0...3
Bank 129J118x Single Ended, 9x Differential pairs0.9VB129_CLK, RX/TX0...3
Bank 65J224x Single Ended, 12x Differential pairs1.8V
Bank 88J216x Single Ended, 8x Differential pairs3.3VHD_B88
ADCJ2

16x Single Ended, 8x Differential pairs

4x Differential Clocks

Variable
DACJ2

16x Single Ended, 8x Differential pairs

3x Differential Clocks

Variable
General PL I/O to B2B connectors information


JTAG Interface

JTAG access to the Xilinx UltraScale+ MPSoC is through B2B connector JM1. JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on B2B. When the CPLD_JTAGEN is 0 or off, it provides FPGA access and when it is 1 or ON, it provides CPLD access.

JTAG Signal

B2B Connector

JTAG_TMSJ1-24
JTAG_TDIJ1-20
JTAG_TDOJ1-18
JTAG_TCK

J1-22

JTAG pins connection

MIO Pins


MIO PinConnected toB2BNotes
MIO0...12SPI FLash, U24-U25-Dual SPI FLash
MIO13LED Green, D1-3.3V_CPLD
MIO14...25FPGA Bank 500,U1J1PSMIO
MIO26...27FPGA Bank 501,U1J1PSMIO
MIO28...29CPLD, U31-

UART_TX, UART_RX

MIO30...31FPGA Bank 501, U1J1PSMIO
MIO32...33EEPROM,U23-I2C_SCL, I2C_SDA
MIO34...35FPGA Bank 501,U1J1PSMIO
MIO36Gigabit ETH, U20-ETH_RST
MIO37USB2.0, U11-USB_RST
MIO38...51FPGA Bank 501, U1J1PSMIO
MIO52...62USB2.0, U11-USB
MIO63...77Gigabit ETH, U20-ETH
MIOs pins

Test Points

Test PointSignalConnected toNotes
TP1CLKOUTVoltage Regulator, U7
TP2PLL_RSTNProgrammable Clock Generator, U15
TP4CPLD_JTAGEN

B2B, J1

CPLD, U31


TP5JTAG_TDO

B2B, J1

CPLD, U31


TP6JTAG_TDI

B2B, J1

CPLD, U31


TP7JTAG_TCK

B2B, J1

CPLD, U31


TP8JTAG_TMS

B2B, J1

CPLD, U31


TP9GNDGND
TP10...11

IO_L1P_AD15P_88, 

O_L4N_AD12N_88

FPGA Bank 88, U1
TP12VINB2B, J1
TP13...14GNDGND
TP15...16MIO32-MIO33

EEPROM,U23

FPGA Bank 501, U1


TP17GNDGND
TP18ADC_AVCCLDO Voltage Regulator, U8
TP19ADC_AVCCAUXLDO Voltage Regulator, U10
TP203.3V_CPLD

CPLD, U31

B2B, J1


T21CPLD_JT AGEN

B2B, J1

CPLD, U31


Test Points Information


On-board Peripherals

Chip/InterfaceDesignatorNotes
QSPI FlashU24, U25
DDR4 SDRAMU2, U3, U5, U9
CPLDU31
USB2.0U11
Gigabit EthernetU20
Programmable Clock GeneratorU15
EEPROMU22
OscillatorsU14, U21, U12
LEDsD0...7
On board peripherals

Quad SPI Flash Memory

The TE0835 is a Dual SPI Flash module equipped with two SPI Flash U24, U25 connecfted to PSMIO FPGA bank 500.

MIO PinSchematicU24 PinU25 PinNotes
MIO0MIO0_QSPICLK-
MIO1MIO1_QSPIDO-
MIO2MIO2_QSPInWP-
MIO3MIO3_QSPInHOLD-
MIO4MIO4_QSPIDI-
MIO5MIO5_QSPInCS-
MIO7MIO5_QSPI-nCS
MIO8MIO5_QSPI-DI
MIO9MIO5_QSPI-DO
MIO10MIO5_QSPI-nWP
MIO11MIO5_QSPI-nHOLD
MIO12MIO5_QSPI-CLK
Quad SPI interface MIOs and pins

System Controller CPLD

The System Controller CPLD (U31) is provided by Lattice Semiconductor LCMXO2-460HC. The  CPLD provides JTAG routing, boot mode, User IOs, LEDs, firmware and power management access. For more information please refer to the TE0835 CPLD page. 

Schematic/PinConnected toDescriptionNote
MODE0...3FPGA Bank 503, U1Boot Mode
POR_BFPGA Bank 503, U1Programming StatusPulled up
PORG_BFPGA Bank 503, U1Programming StatusPulled up
INIT_BFPGA Bank 503, U1Configuration initializationPulled up
DONEFPGA Bank 503, U1Configuration Done StatusPulled up
F_TCKFPGA Bank 503, U1FPGA JTAG
F_TDIFPGA Bank 503, U1FPGA JTAG
F_TMSFPGA Bank 503, U1FPGA JTAG
F_TDOFPGA Bank 503, U1FPGA JTAG
JTAG_TDOB2B, J1CPLD JTAG
JTAG_TMSB2B, J1CPLD JTAG
JTAG_TDIB2B, J1CPLD JTAG
JTAG_TCKB2B, J1CPLD JTAG
CPLD_JTAGENB2B, J1CPLD JTAG Enable
CPLDIO0...3B2B, J1CPLD IOs
RESETNB2B, J1Reset
MIO13LED Green, D13.3V_CPLD
MIO28FPGA Bank 501, U1UART_TX
MIO29FPGA Bank 501, U1UART_RX
FPGA_IO0...1FPGA Bank 65, U1IOs
EN_PS_PLVoltage Regulators, U6, U7, U29PS/PL Enable SignalsPulled Down
EN_GR1Voltage Regulators, U19, U27, U28MGTAVTT, PSLL Pulled Down
EN_GR2Voltage Regulators, U38, U18, U38PS_MGTRAVTT, 3.3, DDR2.5VPulled Down
EN_RF_ADCVoltage Regulators, U8Enable ADCPulled Down
PG_RF_DACVoltage Regulators, U17ADC Power Good Status Pulled Down
PG_PS_PLVoltage Regulators, U6, U7, U29PS/PL Power Good Status Pulled Down
EN_RF_DACVoltage Regulators, U13Enable DACPulled Down
PG_RF_DACVoltage Regulators, U10DAC Power Good Status Pulled Down
USB2.0 interface connections and pins

USB2.0

The TE0835 is equipped with a USB2.0, U11. 

U11 PinSchematicConnected toNotes
RESETBUSB0_RSTFPGA Bank 501, U1
VDDIO1.8V1.8V
CPENUSB0_CPEB2B, J1
VBUSUSB0_VBUSB2B, J1
IDUSB0_IDB2B, J1
DPUSB0_D_PB2B, J1
DMUSB0_D_NB2B, J1
REFCLKUSB_CLKOschillator, U12
STPUSB0_STPFPGA Bank 502, U1
NXTUSB0_NXTFPGA Bank 502, U1
DIRUSB0_DIRFPGA Bank 502, U1
CLKOUTUSB_CLKOschillator, U12
DATA0...7USB0_DATA0...8FPGA Bank 502, U1
USB2.0 interface connections and pins

Ethernet

The module TE0835 is equipped with a Gigabit Ethernet Transceiver, U20.

U20 PinSignal NameConnected toSignal DescriptionNote
MDIOETH_MDIOFPGA Bank 502, U1Data Management
MDCETH_MDCFPGA Bank 502, U1Data Management clock reference for the serial interface
TX_CLKETH_TXCKFPGA Bank 502, U1Transmit Clock
TX_CTRLETH_TXCTLFPGA Bank 502, U1Transmit Control
TXD0...3ETH_TXD0...3FPGA Bank 502, U1Transmit Data
RX_CLKETH_RXCKFPGA Bank 502, U1Receive Clock
RX_CTRLETH_RXCTLFPGA Bank 502, U1Receive Control
RXD0...3ETH_RXD0...3FPGA Bank 502, U1Receive Data
RESETnETH_RSTFPGA Bank 501, U1Ethernet reset, Active low.
XTAL_INETH_XTAL_INOscillator, U21Reference Clock

MDI0...3

PHY_MDI0...3B2B, J1Media Dependent Interface 0...3
LED0...1PHY_LED0...1B2B, J1LED output
LED/INTPHY_LED2B2B, J1LED interrupt
Ethernet connections

EEPROM

The module TE0835 has an EEPROM IC (U23) connected to PSMIO FPGA Bank 501.

MIO PinSchematicU23 PinNotes
MIO32MIO32_I2C1_SCLSCL
MIO33MIO33_I2C1_SDASDA
I2C EEPROM interface MIOs and pins

MIO PinI2C AddressDesignatorNotes
MIO32...330xA1U23
I2C address for EEPROM

LEDs

DesignatorColorConnected toActive LevelNote
D1GreenMIO13Active High3.3V CPLD
D2...5RedDBG_LED0...3Active LowUser LED
D6RedERR_OUTActive High
D7RedERR_STATUSActive High
On-board LEDs

DDR4 SDRAM

The TE0835 SoM has 4x 1 Gigabyte volatile DDR4 SDRAM IC for storing user application code and data.

  • Part number: K4A8G165WB
  • Supply voltage: 1.2 V
  • Speed: 2400 Mbps

  • Temperature: -40 ~ 95 °C

Clock Sources

DesignatorDescriptionFrequencyNote
U14, U21MEMS Oscillator25MHz
U22MEMS Oscillator33.33 MHz
Y1Crystal Oscillator54 MHz
U12MEMS Oscillator52MHz
U15Programmable Clock GeneratorVariable
Oscillators

Programmable Clock Generator

There is a Silicon Labs I2C programmable clock generator on-board (U10) in order to generate reference clocks for the module. Programming can be done using I2C via PIN header J3.  The I2C Address is 0x69.

U15 Pin
SignalConnected toDirectionNote

IN0

IN0_P

Oscillator, U14Input
IN1-N.C-
IN2EXT_CLK_IN1B2B,J2Input
IN3-N.C

nRST

PLL_RSTN

FPGA Bank 65,U1Input
SCLMIO32_I2C1_SCLPin Header, J3InputI2C
SDAMIO33_I2C1_SDAPin Header, J3InputI2C
OUT0

CLKC

B2B,J2Output

Differential Clock

OUT1CLKBB2B,J2OutputDifferential Clock
OUT2CLKAB2B,J2OutputDifferential Clock
OUT3CLKDB2B,J2OutputDifferential Clock
OUT4CLKEB2B,J2OutputDifferential Clock
OUT5CLKFB2B,J2OutputDifferential Clock
OUT6B128_CLK0FPGA Bank 128,U1Output
OUT7B129_CLK0FPGA Bank 129,U1Output
OUT8CLK8FPGA Bank 65,U1Output
OUT9PSMGT_100MHZFPGA Bank 505,U1Output
OUT9ACLK0A_100MHZB2B, J1Output
Programmable Clock Generator Inputs and Outputs

Power and Power-On Sequence

Power Supply

Power supply with minimum current capability of 2.5A for system startup is recommended.

Power Consumption

Power Input PinTypical Current
VIN (5V)TBD*
Power Consumption

* TBD - To Be Determined

Power Distribution Dependencies

Power Distribution

Power-On Sequence

Power Sequency

Power Rails

Power Rail Name

B2B  J1 Pin

B2B  J2 Pin

DirectionNotes
VIN1,2,3,4,5,6,8-Input
PSBATT14-Input
3.3V_CPLD16-Output
Module power rails.

Bank Voltages

Bank          

Schematic Name

Voltage

Notes
Bank 65 HPVCCO_651.8V
Bank 503 PSCONFIG

VCCO_PSIO3_503

1.8V
Bank 88 HDVCCO_883.3V
Bank 128 GTHMGTAVCC0.9V
Bank 129 GTHMGTAVCC0.9V
Bank 500 PSMIOVCCO_PSIO0_5001.8V
Bank 501 PSMIOVCCO_PSIO0_5011.8V
Bank 502VCCO_PSIO0_5021.8V
Bank 504 PSDDRVCCO_PSDDR_5041.2V
Bank 505 PSGTRPS_MGTRAVCC0.85V
Zynq SoC bank voltages.


Board to Board Connectors

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Technical Specifications

Absolute Maximum Ratings

SymbolsDescriptionMinMaxUnit
VINInput Supply Voltage05V
T_STGStorage Temperature-4095°C
PS absolute maximum ratings

Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

ParameterMinMaxUnitsReference Document
VIN4.55.5VSee Schematic
T_OPR-4085°C

See USB2.0 Datasheet

Recommended operating conditions.

Physical Dimensions

  • Module size: 90 mm × 65 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 7 mm.

PCB thickness: 1.65 mm.

Physical Dimension

Currently Offered Variants 

Trenz shop TE0835 overview page
English pageGerman page
Trenz Electronic Shop Overview

Revision History

Hardware Revision History


DateRevisionChangesDocumentation Link
2019-11-05REV01Initial ReleaseREV01
2020-06-17REV02

1. Added a VRP resistor on bank 65;

2. LDO U33 is changed on ADP7102ACPZ;

3. Signal FPGA IO0 is connected on AE18 pin of FPGA;

4. Signal DBG_LED3 is connected on AD18 pin of FPGA;

5. Signal MIO13_25 connected to J1 pin 33 instead MIO25.

6. Resistor R84 is removed;

7. LED D1 moved on edge of PCB;

8. Added THT testpoints J4 on CPLD_JTAGEN, R76 was removed;

9. Signals B49_XX_X are renamed in B88_XX_X;

10. C241 is changed on 1nF;

11. Length of CLK signals on RFADC and RFDAC are adjusted;

12. Wrong connection on U8 is fixed (PCB);

13. Wrong connection PGOOD1 pin of U7 is fixed;

14. R17 is changed from 35,5K to 33K for VCC_PL_PS correction.

REV02
Hardware Revision History


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

|
Board hardware revision number.

Document Change History

DateRevisionContributorDescription

John Hartfiel

  • Style update

  • Bugfix PDF Link
  • Key features update
2020-11-23v.51Pedram Babakhani
  • Update to REV02

--

all

  • --
Document change history.

Disclaimer

Data Privacy

Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

Limitation of Liability

In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.

Copyright Notice

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.

Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.


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