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Template Revision 2.1 6 - on construction

Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"

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Notes :

  • Add basic key futures, which can be tested with the design


Excerpt
  • Vovadp 2018.3
  • PetaLinux
  • SD
  • ETH
  • MAC from EEPROM
  • USB
  • I2C
  • RTC
  • FMeter
  • SI5338 Initialisation with Modified FSBL (optionalsome additional outputs and SI5338 reconfiguration)
  • Special FSBL for QSPI Programming

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DateVivadoProject BuiltAuthorsDescription
2018
2019-
10
05-
01
092018.
2
3TE0715-test_board-vivado_2018.
2
3-build_
03
05_
20181001131411
20190509094447.zip
TE0715-test_board_noprebuilt-vivado_2018.
2
3-build_
03
05_
20181001131421
20190509094505.zipJohn Hartfiel
  • Rework Board Part Files (PS)
  • small design changes
  • SI5338 reconfiguration default activated on FSBL
  • update linux startup app
2018-04-26
  • TE Script update
  • rework of the FSBLs
  • some additional Linux features
  • MAC from EEPROM
2018-10-012018.2
2017.4
TE0715-test_board-vivado_
2017.4-
2018.2-build_03_20181001131411.zip
TE0715-test_board_noprebuilt-vivado_2018.2-build_03_20181001131421.zip
John Hartfiel
  • Rework Board Part Files (PS)
  • small design changes
  • SI5338 reconfiguration default activated on FSBL
  • update linux startup app
2018-04-262017.4TE0715-test_board-vivado_2017.4-build_07_20180426171530.zip
TE0715-test_board_noprebuilt-vivado_2017.4-build_07_20180426171546.zip
John Hartfiel
  • new assembly variant
2018-03-272017.4te0715-test_board-vivado_2017.4-build_07_20180327223552.zip
te0715-test_board_noprebuilt-vivado_2017.4-build_07_20180327223606.zip
John Hartfiel
  • Board Part Bug fix with UART 1
2018-01-052017.4te0715-test_board-vivado_2017.4-build_01_20180105195436.zip
te0715-test_board_noprebuilt-vivado_2017.4-build_01_20180105195452.zip
John Hartfiel
  • No Design changes
  • Add FSBL for Flash Programming
2017-11-102017.2te0715-test_board-vivado_2017.2-build_05_20171110134232.zip
te0715-test_board_noprebuilt-vivado_2017.2-build_05_20171110134247.zip
John Hartfiel
  • New Web Link on Board Part Files
  • Add optional FSBL Code to reprogram  SI5338
2017-10-192017.2te0715-test_board-vivado_2017.2-build_04_20171019141808.zip
te0715-test_board_noprebuilt-vivado_2017.2-build_04_20171019141825.zip
John Hartfiel
  • changed Flash typ on TE0715_board_files.csv
    (older one is not supported on Vivado 2017.2)
2017-09-222017.2te0715-test_board-vivado_2017.2-build_02_20170927143412.zip
te0715-test_board_noprebuilt-vivado_2017.2-build_02_20170927143427.zip
John Hartfiel
  • initial release


Release Notes and Know Issues

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SoftwareVersionNote
Vivado2018.23needed
SDK2018.23needed
PetaLinux2018.23neededSI5338 Clock Builder
SI ClockBuilder Pro---optional


Hardware

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Notes :

  • list of software which was used to generate the design

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titleHardware Modules

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Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0715 TE0715-03-15-1C1C   03_15_1cREV01,02,031GB32_1gb   REV03|REV02|REV01 1GB      32MB       NA        NA                NA                             
 TE0715TE0715-03-15-1I1I   03_15_1iREV01,02,031GB32_1gb   REV03|REV02|REV01 1GB      32MB       NA        NA                NA                             
 TE0715TE0715-03-15-2I2I   03_15_2iREV01,02,031GB32_1gb   REV03|REV02|REV01 1GB      32MB       NA        NA                NA                             
 TE0715-03-30-1C   TE0715-03-30-1C03_30_1cREV01,02,031GB32_1gb   REV03|REV02|REV01 1GB      32MB       NA        NA                NA                             
 TE0715TE0715-03-30-1I1I   03_30_1iREV01,02,031GB32_1gb   REV03|REV02|REV01 1GB      32MB       NA        NA                NA                             
 TE0715TE0715-03-30-3E3E   03_30_3eREV01,02,031GB32_1gb   REV03|REV02|REV01 1GB      32MB       NA        NA                NA                             
 TE0715TE0715-04-15-1C1C   04_15_1cREV041GB_L32_1gb   REV04             1GB      32MB       NA        NA                Low Power DDR                
 TE0715TE0715-04-15-1I1I   04_15_1iREV041GB_L32_1gb   REV04             1GB      32MB       NA        NA                Low Power DDR                
 TE0715TE0715-04-15-1I31I3  04_15_1iREV041GB_L322,5 mm B2B connector_1gb   REV04             1GB      32MB       NA        NA                Low Power DDR                
 TE0715TE0715-04-15-2I2I   04_15_2i_1gb   REV041GB_L32REV04             1GB      32MB       NA        NA                Low Power DDR                
 TE0715-04-30-1C   TE0715-04-30-1C04_30_1cREV041GB_L32_1gb   REV04             1GB      32MB       NA        NA                Low Power DDR                
 TE0715TE0715-04-30-1I1I   04_30_1iREV041GB_L32_1gb   REV04             1GB      32MB       NA        NA                Low Power DDR                
 TE0715TE0715-04-30-1I31I3  04_30_1iREV041GB_L322,5 mm B2B connector_1gb   REV04             1GB      32MB       NA        NA                Low Power DDR                
 TE0715TE0715-04-30-3E3E   04_30_3e_1gb   REV041GB_L32REV04             1GB      32MB       NA        NA                Low Power DDR                
 TE0715TE0715-04-12s-1C12s     REV041GB_L3212S-1C  04_12s_1c_1gb  REV04             1GB      32MB       NA        NA                Low Power DDR                
 TE0715TE0715-04-30-1IA1IA  04_30_1iREV041GB_L32_1gb   REV04             1GB      32MB       NA        NA                Low Power DDR. Micron Flash  Micron instead of Spansion Flash



Design supports following carriers:

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titleHardware Carrier

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Carrier ModelNotes
TE0701
TE0703used as reference carrier 
TE0705
TE0706
TEBA0841-02


Additional HW Requirements:

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For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

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TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for SDK/HSI and apps_list.csv with settings for HSI
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration


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TypeLocationNotes
SI5338<design name>/misc/Si5338SI5345 SI5338 Project with current PLL Configuration

Prebuilt

init.sh<design name>/misc/sd/Additional Initialization Script for Linux


Prebuilt

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Notes :

  • prebuilt files
  • Template Table:

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      File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Hardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems



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Reference Design is available on:

Design Flow

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  • Basic Design Steps

  • Add/ Remove project specific description

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Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality


  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
    Image RemovedImage Added
  2. Press 0 and enter for minimum setupto start "Module Selection Guide"
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
    1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
    2. Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (uboot.elf and image.ub) with exported HDF
    1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
        Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
  7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
    1. "prebuilt\os\petalinux\default<ddr size>" or "prebuilt\os\petalinux\<short name>"Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
  8. Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::
    Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

...

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
    Note: To program with SDK/Vivado GUI, use special FSBL (zynq_fsbl_flash) on setup
             optional "TE::pr_program_flash_binfile -swapp hello_te0715" possible
  4. Copy image.ub on SD-CardInsert SD-Card
  5. Set Boot Mode to QSPI-Boot and insered SD.
    • Depends on Carrier, see carrier TRM.

SD

  1. Copy image.ub and Boot.bin on SD-Card.
    • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.

...

  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root
  3. You can use Linux shell now.
    1. I2C 1 Bus type: i2cdetect -y -r 1
    2. RTC check: dmesg | grep rtc
    3. ETH0 works with udhcpc

Vivado HW Manager 

  1. Option Features
    1. Webserver to get access to Zynq
      1. insert IP on web browser to start web interface
    2. init.sh scripts
      1. add init.sh script on SD, content will be load automatically on startup (template included in ./misc/SD)

Vivado HW Manager 

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Note:

  • Add picture of HW Manager

  • add notes for the signal either groups or topics, for example:

    Control:

    • add controllable IOs with short notes..

    Monitoring:

    • add short notes for signals which will be monitored only

    SI5338_CLK0 Counter: 

    Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz

...

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).

  • Monitoring:
    • Si5338 CLKS:
      • Set radix from VIO signals to unsigned integer.

...

      • Note: Frequency Counter is inaccurate and displayed unit is Hz
      • MGT CLK is configured to 125MHz by default, FCLK is not configured by default (optional possible over FSBL → 50MHz on delivered configuration, see FSBL description).
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titleVivado Hardware Manager

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Code Block
languageruby
title_i_timing.xdc
# for fmeter only
# set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks {zsys_i/util_ds_buf_0/U0/IBUF_OUT[0]}]
# set_false_path -from [get_clocks {zsys_i/util_ds_buf_0/U0/IBUF_OUT[0]}] -to [get_clocks clk_fpga_0]
# set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks {zsys_i/util_ds_buf_1/U0/BUFG_O[0]}]

...

For SDK project creation, follow instructions from:

Application

Template location: ./sw_lib/sw_apps/

zynq_fsbl

TE modified 2018.2 FSBL

Changes:

  • Si5338 Configuration
    • see main.c, fsbl_hooks.c (d/remove define RECONFIGURE_SI5338 to enable PLL programming with given register_map.h setup (default activate))
    • Add register_map.h, si5338.c, si5338.h

zynq_fsbl_flash

TE modified 2018.2 FSBL

Changes:

  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

hello_te0715

Hello TE0715 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

HTML
<!--
- optional chapter, if petalinux is used
- Add changes from default petalinux project
   -->

For PetaLinux installation and  project creation, follow instructions from:

Config

No changes.

U-Boot

No changes.

Device Tree

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----------------------------------------------------------

FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2018.3 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

  • Modified Files: blconfig.h, bootloader.c
  • Changes:
    • Add some console outputs and changed bootloader read address.
    • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2018.3 xilisf_v5_11

  • Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

zynq_fsbl

TE modified 2018.3 FSBL

General:

  • Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot  platform-top.h)
    • CPLD access
    • Read CPLD Firmware and SoC Type
    • Configure Marvell PHY

zynq_fsbl_flash

TE modified 2018.3 FSBL

General:

  • Modified Files: main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2018.3 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
  • Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2018.3 FSBL

General:

  • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation


zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Template location: ./sw_lib/sw_apps/

zynq_fsbl

TE modified 2018.3 FSBL

General:

  • Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • SI5338 Configuration

zynq_fsbl_flash

TE modified 2018.3 FSBL

General:

  • Modified Files: main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

hello_te0715

Hello TE0715 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

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Note:
  • optional chapter separate

  • sections for linux

  • Add "No changes." or "Activate: and add List"

For PetaLinux installation and  project creation, follow instructions from:

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

  • CONFIG_SUBSYSTEM_ETHERNET_PS7_ETHERNET_0_MAC=""

U-Boot

Start with petalinux-config -c u-boot

Changes:

  • CONFIG_ENV_IS_NOWHERE=y

    # CONFIG_ENV_IS_IN_SPI_FLASH is not set

Change platform-top.h:

Code Block
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#include <configs/platform-auto.h>
#define CONFIG_SYS_BOOTM_LEN 0xF000000
#define DFU_ALT_INFO_RAM \
                "dfu_ram_info=" \
        "setenv dfu_alt_info " \
        "image.ub ram $netstart 0x1e00000\0" \
        "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
        "thor_ram=run dfu_ram_info && thordown 0 ram 0\0"

#define DFU_ALT_INFO_MMC \
        "dfu_mmc_info=" \
        "set dfu_alt_info " \
        "${kernel_image} fat 0 1\\\\;" \
        "dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \
        "thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0"


/*Required for uartless designs */
#ifndef CONFIG_BAUDRATE
#define CONFIG_BAUDRATE 115200
#ifdef CONFIG_DEBUG_UART
#undef CONFIG_DEBUG_UART
#endif
#endif



/*Define CONFIG_ZYNQ_EEPROM here and its necessaries in u-boot menuconfig if you had EEPROM memory. */
//#ifdef CONFIG_ZYNQ_EEPROM
//#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN         1
//#define CONFIG_SYS_I2C_EEPROM_ADDR             0x50
//#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS      4
//#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  5
//#define CONFIG_SYS_EEPROM_SIZE                 1024 /* Bytes */
//#define CONFIG_SYS_I2C_MUX_ADDR                0x74
//#define CONFIG_SYS_I2C_MUX_EEPROM_SEL          0x4
//#endif

#define CONFIG_ZYNQ_EEPROM
#ifdef CONFIG_ZYNQ_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
#define CONFIG_CMD_EEPROM
#define CONFIG_ZYNQ_EEPROM_BUS          0
#define CONFIG_ZYNQ_GEM_EEPROM_ADDR     0x50
#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET  0xFA
#endif

Device Tree

Code Block
languagejs
/include/ "system-conf.dtsi"
/ {
};

/* default */

/* QSPI PHY */
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};

Code Block
languagejs
/include/ "system-conf.dtsi"
/ {
};


/* default */

/* ETH PHY */
&gem0 {

    	status = "okay";
        	ethernet_phy0: ethernet-phy@0 {
        		compatible = "marvell,88e1510";
        		device_type = "ethernet-phy";
                reg = <0>;
    	};
};


/* USB PHY */
/{
    usb_phy0: usb_phy@0 {
        compatible = "ulpi-phy";
        //compatible = "usb-nop-xceiv";
        #phy-cells = <0>;
        reg = <0xe0002000 0x1000>;
        view-port = <0x0170>;
        drv-vbus;
    };
};

&usb0 {
    dr_mode = "host";
    //dr_mode = "peripheral";
    usb-phy = <&usb_phy0>;
};

/* I2C */
// i2c PLL: 0x70, i2c eeprom: 0x50

&i2c1 {
    rtc@6F {        // Real Time Clock
       compatible = "isl12022";
       reg = <0x6F>;
   };

};


Kernel

Start with petalinux-config -c kernel

ChangesActivate:

  • CONFIG_RTC_DRV_ISL12022=y

Rootfs

Activate:

Start with petalinux-config -c rootfs

Changes:

  • CONFIG_i2c-tools=y
  • CONFIG_busybox-httpd=y (for web server app)
  • CONFIG_usbutils=yi2c-tools

Applications

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

webfwu

Webserver application accemble for Zynq access. Need busybox-httpd

Additional Software

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Note:
  • Add description for other Software, for example SI CLK Builder ...
  • SI5338 and SI5345 also Link to:

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File location <design name>/misc/Si5338/RegisterMapSi5338-*.txtslabtimeproj

General documentation how you work with these project will be available on Si5338

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DateDocument Revision

Authors

Description
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modified-date
modified-date
dateFormatyyyy-MM-dd


Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
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Page info
infoTypeModified by
dateFormatyyyy-MM-dd
typeFlat

  • Release 2018.2
  • Redesign Board Part Files
  • New activate SI5338 example over FSBL
  • small Design changes
  • Update Documentation Style
  • 3
  • FSBL Rework
  • Script rework
  • some optional features
2018-10-01v.31John Hartfiel
  • Release 2018.2
  • Redesign Board Part Files
  • New activate SI5338 example over FSBL
  • small Design changes
  • Update Documentation Style
  • Update in process and will be available soon

2019-04-06

v.30John Hartfiel
  • New assembly variant

2018-03-27

v.29John Hartfiel
  • Bugfix Board Part Files
2018-02-13v.28John Hartfiel
  • Release 2017.4
2017-11-10v.22John Hartfiel
  • Design Update with new options
  • Add Si5338 section
  • Update FSBL section
2017-10-19

v.21

John Hartfiel
  • Download Update
2017-10-19v.20John Hartfiel
  • Document style update
2017-10-06v.18John Hartfiel
  • Text correction
  • Update Launch section
  • Supported PCBs
2017-10-02v.14John Hartfiel
  • Document update on Prebuilt section
2017-09-28
v.13
John Hartfiel
  • Initial Release 2017.2
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Page info
infoTypeModified users
dateFormatyyyy-MM-dd
typeFlat

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