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Template Revision 2.12
- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM" - Carrier: TRM Name usually "TEB Series Name" +TRM
Example: "TEB0728 TRM"
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Important General Note:
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Table of Contents |
Overview
The Trenz Electronic TEB0707 is a carrier for 4 x 5 Trenz Electronic modules. It provides three high speed and one low speed CRUVI extension connectors. For more information, please refer to the CRUVI B2B Connectors. The TEB0707 is integrated with an Intel MAX10 FPGA as system controller and is equipped with a Micro USB2.0 Socket with FTDI to JTAG/UART solution, RJ45 LAN Socket, USB A Socket, Micro SD Card Socket, User LEDs, Push Buttons and DIP Switches for controlling the SoM.
Refer to http://trenz.org/teb0707-info for the current online version of this manual and other available documentation.
Key Features
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Note: 'description: Important components and connector or other Features of the module → please sort and indicate assembly options Key Features' must be split into 6 main groups for modules and mainboards: - SoC/FPGA
- Package: SFVC784
- Device: ZU2...ZU5*
- Engine: CG, EG, EV*
- Speed: -1LI, -2LE,*, **
- Temperature: I, E,*, **
- RAM/Storage
- Low Power DDR4 on PS
- Data width: 32bit
- Size: def. 2GB*
- Speed:***
- eMMC
- Data width: 8Bit
- size: def. 8GB *
- QSPI boot Flash in dual parallel mode (size depends on assembly version)
- Data width: 8bit
- size: def. 128MB *
- HyperRAM/Flash (optional, default not assembled)
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
- On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
- Interface
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, Sata, PCIe, DP)
- MIO for UART
- MIO for SD
- MIO for PJTAG
- JTAG
- Ctrl
- Power
- 3.3V-5V Main Input
- 3.3V Controller Input
- Variable Bank IO Power Input
- Dimension
- Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
Key Features' must be split into 6 main groups for carrier: - Modules
- TE0808, TE807, TE0803,...
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
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- Modules
- 4x5 Trenz Electronic modules
- RAM/Storage
- EEPROM (FTDI Configuration)
- On Board
- Intel Max 10 FPGA
- FTDI FT2223
- 6x User LEDs (3x green, 3x red)
- 2x Status LED
- DIP Switch
- Push Buttons
- Interface
- Gigabit RJ45 LAN socket
- SD Card socket
- Micro USB2.0 Socket
- USB A Socket
- 3x High Speed CRUVI B2B Connectors
- 1x Low Speed CRUVI B2B Connector
- 4x Jumpers
- Power
- Dimension
- Notes
Block Diagram
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title | TEB0707 block diagram |
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Main Components
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Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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title | TEB0707 main components |
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diagramName | TEB0707_OV_MC |
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- Barrel Jack Power Supply, J1
- Voltage Regulator, U1
- Micro SD Card Socket, J8
- Micro USB2.0 Socket, J15
- FT2232H FTDI, U8
- USB A Socket, J9
- RJ45 LAN Socket, J2
- SDIO Port Expander, U4
- Jumpers, J4...7
- Push Button (Reset), S2
- DIP Switch, S1
- B2B Connector, JB3
- B2B Connector, JB2
- B2B Connector, JB1
- Intel MAX 10 FPGA, U6
- High Speed CRUVI Connector, J10
- High Speed CRUVI Connector, J11
- High Speed CRUVI Connector, J12
- Low Speed CRUVI Connector, J13
- User Push Button, S3
- Pin header, J3
Initial Delivery State
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Notes : Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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anchor | Table_OV_IDS |
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title | Initial delivery state of programmable devices on the module |
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orientation | portrait |
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Storage device name | Content | Notes |
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EEPROM | Programmed | FTDI Configuration |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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anchor | Table_OV_BP |
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title | Boot process. |
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MODE Signal State | Boot Mode |
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MODE | Boot Mode: | PROGMODE | Programming Mode: - select between CPLD (low, closed, on)
- on SoM or FPGA/SoC (high, open, off )
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anchor | Table_OV_RST |
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title | Reset process. |
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Signal | Connected to | I/O | Note |
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Reset | Push Button, S2 | Out | Module Reset signal |
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Signals, Interfaces and Pins
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Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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Board to Board (B2B)
Interfaces and Number of I/O signals connected to the B2B connectors for Trenz 4x5 modules:
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anchor | Table_SIP_B2B |
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title | General PL I/O to B2B connectors information |
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orientation | portrait |
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B2B Connector | Interface | I/O Signal Count | Connected to | Notes |
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JB1
| Ethernet LAN | 4x Diff pairs | RJ45 Socket, J2 |
| SD Card | 6 x Single Ended | IO Expander, U4 |
| I/Os | 20x Single Ended | MAX10 FPGA Bank 6, U6 |
| CRUVI | 12x Diff pairs/24x Single ended 4x Single Ended | High Speed CRUVI, J12 | CRUVI C | SoM Control Signals | 5x Single Ended | MAX10 FPGA, U6 |
| I/Os | 8x Single ended | MAX10 FPGA Bank 8, U6 |
| JB2
| CRUVI | 12x Diff pairs/24x Single ended 4x Single Ended | High Speed CRUVI, J10 | CRUVI A | CRUVI | 6x Diff pairs/12x Single ended | High Speed CRUVI, J11 | CRUVI B | JTAG | 4x Single Ended | FPGA Bank 5, U6 |
| JB3 | CRUVI | 6x Diff pairs/12x Single ended 4x Single Ended | High Speed CRUVI, J11 | CRUVI B | USB | 1x Diff pair, 2x Single Ended | USB A, J9 |
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CRUVI B2B Connectors
The TEMB0707 is equipped with a Low Speed Connectors J 13 and three High Speed Connector J10...12. These connectors are provided for CRUVI extension cards. More information is provided in the B2B Connectors section.
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anchor | Table_SIP_CRUVIB2B |
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title | CRUVI B2B connectors information |
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orientation | portrait |
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Speed | Designators | Schematic | Connected to | Notes |
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High
| CRUVI C, J12 | A0...A5 (N/P) | B2B, JB1 |
| B0...B5 (N/P) | B2B, JB1 |
| MODE, REFCLK, SMB_ALERT, SMB_SDA, SMB_SCL, SEL, DO, DI, SCK | MAX10 FPGA Bank 8, U6 | 3.3V User IOs (Max10 Firmware dependent) | HSIO, HI, HO, RESET | B2B, JB1 |
| High
| CRUVI B, J11 | A0...A5 (N/P) | B2B, JB1 |
| B0...B5 (N/P) | B2B, JB1 |
| MODE, REFCLK, SMB_ALERT, SMB_SDA, SMB_SCL, SEL, DO, DI, SCK | MAX10 FPGA Bank 2/3, U6 | 3.3V User IOs (Max10 Firmware dependent) | HSIO, HSI, HSO, RESET | B2B, JB3 |
| High
| CRUVI A, J13
| A0...A5 (N/P) | B2B, JB2 |
| B0...B5 (N/P) | B2B, JB2 |
| MODE, REFCLK, SMB_ALERT, SMB_SDA, SMB_SCL, SEL, DO, DI, SCK | MAX10 FPGA Bank 2/3, U6 | 3.3V User IOs (Max10 Firmware dependent) | HSIO, HSI, HSO, RESET | B2B, JB2 |
| Low | CRUVI | X0...X7 | MAX10 FPGA Bank 1A, U6 |
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JTAG Interface
JTAG signals form FTDI U8 are routed to MAX10 CPLD. Via dip setting JTAG of MAX10 or JTAG of the connected Trenz 4x5 module can be selected. Forwarding signals to SoM is MAX10 Firmware dependent.
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anchor | Table_SIP_MJTG |
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title | JTAG pins connection |
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orientation | portrait |
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JTAG Signal | MAX10 Pin Bank 1B, U6 | Connected to |
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TMS | G1 | FTDI (U8) - ADBUS3 | TDI | F5 | FTDI (U8) - ADBUS1 | TDO | F6 | FTDI (U8) - ADBUS2 | TCK | G2 | FTDI (U8) - ADBUS0 | JTAGEN | E5 | Dip S1-4 |
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JTAG access to the Trenz 4x5 module is through B2B connector JB2.
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anchor | Table_SIP_MJTG |
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title | JTAG pins connection |
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orientation | portrait |
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JTAG Signal | MAX10 Pin Bank5, U6 | B2B Connector |
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M_TMS | L12 | JB2-94 | M_TDI | L13 | JB2-96 | M_TDO | J10 | JB2-100 | M_TCK | H8 | JB2-98 | VCCJTAG | J11, J12 | JB2-92 |
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SD Card socket
The TEB0707 is equipped with an Micro SD Card slot, J8. For levelshifting an IO Expander (U4) is used.
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anchor | Table_SIP_SD Card |
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title | USB2.0 Socket information |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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cellHighlighting | true |
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Pin | Schematic | Connected to | Notes |
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DAT0...3 | ESD_DAT0...3 | B2B, JB1 | Through IO Expander, U4 | CMD | ESD_CMD | B2B, JB1 | Through IO Expander, U4 | VDD | 3.3V_SD | B2B, JB1 | Through IO Expander, U4 | CLK | ESD_CLK | B2B, JB1 | Through IO Expander, U4 | DLT | SD_CD | FPGA Bank 3, U6 | Card detect. |
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Micro USB2.0 Socket
There is a micro USB2.0 Socket, J15 provided in order to communicate with the FTDI, U8.
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anchor | Table_SIP_USB2 |
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title | Micro USB2.0 Socket information |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Pin | Schematic | Connected to | Notes |
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D+ | O2-D_P | B2B, JB3 | Through Line Filter, L4 | D- | O2-D_N | B2B, JB3 | Through Line Filter, L4 | Vbus | VBUS | B2B, JB3 |
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USB A Socket
The SoM USB 2.0 signals are routed to a USB A socket (host).
Scroll Title |
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anchor | Table_SIP_USBA |
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title | USB A Socket information |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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cellHighlighting | true |
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Pin | Schematic | Connected to | Notes |
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Data+ | O2-D_P | B2B, JB3 | Through Line Filter, L1 | Data- | O2-D_N | B2B, JB3 | Through Line Filter, L1 | VCC | USB_VBUS | B2B, JB3 |
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RJ45 LAN Socket
There is a RJ45 Ethernet LAN MagJack, J2 connected to B2B, JB1.
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anchor | Table_SIP_ETH |
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title | RJ45 LAN Socket information |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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cellHighlighting | true |
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Pin | Schematic | Connected to | Notes |
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2 | PHY_MDI0_P | B2B, JB1 |
| 3 | PHY_MDI0_N | B2B, JB1 |
| 4 | PHY_MDI1_P | B2B, JB1 |
| 5 | PHY_MDI1_N | B2B, JB1 |
| 6 | PHY_MDI2_P | B2B, JB1 |
| 7 | PHY_MDI2_N | B2B, JB1 |
| 8 | PHY_MDI3_P | B2B, JB1 |
| 9 | PHY_MDI3_N | B2B, JB1 |
| VCC | ETH-VCC | B2B, JB1 |
| Green LED | ETH1_LED0 | Intel MAX 10, U6 | MAX10 Firmware dependent | Yellow LED | ETH1_LED1 | Intel MAX 10, U6 | MAX10 Firmware dependent |
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Jumpers
There are three Jumpers provided to choose the CRUVI Extension power voltage.
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anchor | Table_SIP_Jumpers |
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title | Jumpers information |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Schematic | Connected to | Notes |
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J14 | VCCIO_CC | B2B, JB2 | CRUVI C | J16 | VCCIO_CB | B2B, JB2 | CRUVI B | J17 | VCCIO_CA | B2B, JB2 | CRUVI A |
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anchor | Table_SIP_SMD |
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title | Jumpers information |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Schematic | Connected to | Notes |
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J3 | VBAT | B2B, JB1 |
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Test Points
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example: Test Point | Signal | B2B | Notes |
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10 | PWR_PL_OK | J2-120 |
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anchor | Table_SIP_TPs |
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title | Test Points Information |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Test Point | Signal | Connected to | Notes |
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TP1 | 3.3V | Regulator, U1 |
| TP2 | VIN | Voltage Protection, U2 |
| TP4 | IOV | Regulator, U3 |
| TP5 | 3.3V | Power Switch, Q1 |
| TP6 | C5VIN | Power Switch, Q2 |
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On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
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anchor | Table_OBP |
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title | On board peripherals |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Intel Max10 CPLD
The TEB0707 is quipped with an Intel Max10 as CPLD used for levelshifting of 3.3V signals on CRUVI connectors, JTAG/UART forward to modules, Module control pis, power sequencing and IO voltage selection along with providing User Push buttons, LEDs and switches. For complete information, please see the TEB0707 MAX10 CPLD.
FTDI FT2232H
The FTDI chip (U8) converts signals from USB2 to variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip which is used in Multi-Protocol Synchronous Serial Engine (MPPSE) mode for JTAG.
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U10.
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anchor | Table_OBP_FT2232H |
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title | FTDI chip interfaces and pins |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Pin | Schematic | Connected to | Notes |
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ADBUS0 | TCK | FPGA Bank 1B, U6 | JTAG interface | ADBUS1 | TDI | FPGA Bank 1B, U6 | ADBUS2 | TDO | FPGA Bank 1B, U6 | ADBUS3 | TMS | FPGA Bank 1B, U6 | BDBUS0 | F_UART_TX | FPGA Bank 1B, U6 | UART Transmitter output | BDBUS1 | F_UART_RX | FPGA Bank 1B, U6 | UART Receiver Input | OSCI | OSCI | Oscillator, U7 | Clock 12 MHz | EECS | EECS | EEPROM, U10 | EEPROM Contains FTDI configuration | EECLK | EECLK | EEPROM, U10 | EEDATA | EEDATA | EEPROM, U10 | DM/DP | FD_N/ FD_P | Micro USB, J15 | USB to UART | nRESET | 3.3V | 3.3V |
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LEDs
The functions of the LEDs are MAX10 Firmware dependent. See TEB0707 MAX10 CPLD LEDs.
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anchor | Table_OBP_LED |
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title | On-board LEDs |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Color | Schematic | Connected to | Active Level | Note |
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D1 | green | LED3 | FPGA Bank 8 | Active High |
| D2 | green | LED5 | FPGA Bank 8 | Active High |
| D3 | green | LED7 | FPGA Bank 8 | Active High |
| D4 | red | LED4 | FPGA Bank 3 | Active High |
| D5 | red | LED6 | FPGA Bank 2 | Active High |
| D6 | red | LED8 | FPGA Bank 8 | Active High |
| D7 | red | LED2 | FPGA Bank 3 | Active High |
| D8 | green | LED1 | FPGA Bank 3 | Active High |
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EEPROM
The EEPROM IC, U8 contains the FTDI configuration and is prprogrammed with Xilinx JTAG licence.
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anchor | Table_OBP_EEP |
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title | I2C EEPROM interface MIOs and pins |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Pin | Schematic | Connected to | Notes |
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CS | EECS | FTDI, U8 |
| CLK | EECLK | FTDI, U8 |
| DIN | EEDATA | FTDI, U8 |
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DIP Switch
There is a DIP Switch provided for user controlling of settings. Dip1..3 are connected to MAX10 CPLD and therefore function is Firmware dependent, see TEB0707 MAX10 Dips.
Scroll Title |
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anchor | Table_OBP_DIP |
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title | DIP Switch connections |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Pin | Schematic | Function (in standard Firmware) | Notes |
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DIP1 | DIP1 | Forwarded to IO so SoM | MAX10 firmware dependent. | DIP2 | DIP2 | IO Voltage selection | 1.8V ('high', open, OFF), 2.5V ('low', closed, ON) | DIP3 | DIP3 (PROGMODE) | Programming mode (JTAG selection on Trenz 4x5 module) | Select between FPGA/SoC (high, open, OFF ) or CPLD (low, closed, ON), MAX10 firmware dependent.
| DIP4 | JTAGEN | JTAG Selection | JTAG mode between CPLD (high, closed, ON) or SoM (low, open, OFF) |
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Push Buttons
Buttons are connected MAX10 CPLD and therefore function is Firmware dependent, see TEB0707 MAX10 CPLD Buttons
Scroll Title |
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anchor | Table_OBP_BTN |
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title | Push Buttons informations |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Schematic | Function (in standard Firmware) | Notes |
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S2 | RESET | SoM Reset | Hardware debounced. | S3 | BUTTON1 | User Button | debounced in Max10 FPGA |
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Clock Sources
MEMS U7 Oscillator is nedded for FTDI. It is additionally connectd to MAX 10 FPGA Bank 2 Pin H4 and can be used in custom Firmware.
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anchor | Table_OBP_CLK |
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title | Osillators |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Description | Frequency | Note |
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U7 | MEMS Oscillator | 12 MHz |
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Power and Power-On Sequence
Page properties |
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - |Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
Power supply with minimum current capability of 3 A for system startup is recommended.
Power Consumption
Scroll Title |
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anchor | Table_PWR_PC |
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title | Power Consumption |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Input Pin | Typical Current |
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VIN | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
Scroll Title |
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anchor | Figure_PWR_PD |
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title | Power Distribution |
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draw.io Diagram |
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border | false |
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| |
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diagramName | TEB0707_PWR_DP |
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simpleViewer | false |
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width | 639 |
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links | auto |
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tbstyle | hidden |
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diagramDisplayName | |
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lbox | true |
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diagramWidth | 641 |
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revision | 5 |
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Scroll Only |
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Image Added |
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Power-On Sequence
Scroll Title |
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anchor | Figure_PWR_PS |
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title | Power Sequency |
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Scroll Ignore |
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draw.io Diagram |
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border | false |
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| |
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diagramName | TEB0707_PWR_PS |
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simpleViewer | false |
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width | 639 |
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links | auto |
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tbstyle | hidden |
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diagramDisplayName | |
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lbox | true |
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diagramWidth | 641 |
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revision | 4 |
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Scroll Only |
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Image Added |
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Power Rails
Scroll Title |
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anchor | Table_PWR_PR |
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title | Module power rails. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Rail Name | B2B Connector JB1 Pin | B2B Connector JB2 Pin | B2B Connector JB3 Pin | Direction | Notes |
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VCCIO_CA | - | 8, 10 | - | Output |
| VCCIO_CB | - | 2, 4, 6 | - | Output |
| VCCIO_CC | 10, 12 | - | - | Output |
| 3.3V | 14, 16 | - | - | Output |
| M1.8VOUT | 40 | - | - | Input |
| M3.3VOUT | - | 9, 11 | - | Input |
| ETH-VCC | 13 | - | - | Input |
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Bank Voltages
Below MAX10 CPLD Bankvoltages are summarized.
Scroll Title |
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anchor | Table_PWR_BV |
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title | Zynq SoC bank voltages. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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| Schematic Name | | Notes |
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Bank 1A | 3.3V | 3.3V |
| Bank 1B | 3.3V | 3.3V |
| Bank 2 | 3.3V | 3.3V |
| Bank 3 | 3.3V | 3.3V |
| Bank 5 | VCCJTAG |
| from SoM | Bank 6 | VCCIO_CC |
| Variable | Bank 8 | 3.3V | 3.3V |
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Board to Board Connectors
Page properties |
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- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
Include Page |
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| 6 x 6 SoM LSHM B2B Connectors |
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| 6 x 6 SoM LSHM B2B Connectors |
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Include Page |
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| 4 x 5 SoM LSHM B2B Connectors |
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| 4 x 5 SoM LSHM B2B Connectors |
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CRUVI Connectors
Include Page |
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| CRUVI B2B Connectors |
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| CRUVI B2B Connectors |
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Technical Specifications
Absolute Maximum Ratings
Scroll Title |
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anchor | Table_TS_AMR |
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title | PS absolute maximum ratings |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Symbols | Description | Min | Max | Unit |
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5VIN | Input supply Voltage | -40 | 60 | V | T_STG | Storage Temperature | -40 | 85 | °C |
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Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Scroll Title |
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anchor | Table_TS_ROC |
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title | Recommended operating conditions. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Parameter | Min | Max | Units | Reference Document |
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Input supply Voltage | 4.06 | 5.58 | V | See the OV/UV in the carrier datasheets. | T_OPT | 0 | 70 | °C | See Push Button datasheet. |
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Physical Dimensions
Module size: 135 mm × 68 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 4 mm.
PCB thickness: 1.7 mm.
Page properties |
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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM. For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below: https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF
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Scroll Title |
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anchor | Figure_TS_PD |
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title | Physical Dimension |
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Scroll Ignore |
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draw.io Diagram |
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border | false |
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diagramName | TEB0707_TS_PD |
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simpleViewer | false |
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width | 639 |
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links | auto |
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tbstyle | hidden |
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diagramDisplayName | |
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lbox | true |
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diagramWidth | 591 |
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revision | 7 |
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Scroll Only |
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scroll-pdf | true |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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| Image Added |
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Currently Offered Variants
Page properties |
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Set correct link to the shop page overview table of the product on English and German. Example for TE0706: ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706 DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706 |
Scroll Title |
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anchor | Table_VCP_SO |
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title | Trenz Electronic Shop Overview |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Revision History
Hardware Revision History
Scroll Title |
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anchor | Table_RH_HRH |
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title | Hardware Revision History |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Date | Revision | Changes | Documentation Link |
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2020-11-20 | REV02 | first production release | REV02 | 2020-04-01 | REV01 | Prototypes | - |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Scroll Title |
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anchor | Figure_RV_HRN |
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title | Board hardware revision number. |
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Scroll Ignore |
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draw.io Diagram |
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border | false |
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| |
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diagramName | TEB0707_RV_HRN |
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simpleViewer | false |
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width | 200 |
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links | auto |
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tbstyle | hidden |
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diagramDisplayName | |
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lbox | true |
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diagramWidth | 122 |
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revision | 7 |
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Scroll Only |
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Image Added |
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Document Change History
Page properties |
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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Scroll Title |
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anchor | Table_RH_DCH |
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title | Document change history. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Date | Revision | Contributor | Description |
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Page info |
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infoType | Modified date |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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| Page info |
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infoType | Current version |
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prefix | v. |
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type | Flat |
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showVersions | false |
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| Page info |
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infoType | Modified by |
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type | Flat |
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showVersions | false |
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| | -- | all | Page info |
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infoType | Modified users |
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type | Flat |
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showVersions | false |
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Disclaimer
Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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