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Overview

The Trenz Electronic TEM0707 is an industrial-grade module TEB0707 is a carrier for 4 x 5 Trenz Electronic modules. It provides three high speed and one low speed CRUVI extension connectors. For more information, please refer to the CRUVI B2B Connectors. The TEB0707 is integrated with an Intel MAX10 FPGA as system controller and it is equipped with a Micro USB2.0 Socket with FTDI to JTAG/UART solution, RJ45 LAN Socket, Micro USB A Socket, Micro SD Card Socket, Low and High Speed Board to Board Connectors, User LEDs, FTDI,  Push Buttons and DIP Switch Switches for controlling the SoM. Furtheremore, the TEB0707 provides CRUVI Extension connectors. For more information, Please refer to the CRUVI B2B Connectors.

Refer to http://trenz.org/teb0707-info for the current online version of this manual and other available documentation.

...

  • Modules
    • 4x5 Trenz Electronic modules
  • RAM/Storage
    • EEPROM (FTDI Configuration)
  • On Board
    • Intel Max 10 FPGA
    • FTDI FT2223
    • 8x Green 6x User LEDs (3x green, 3x red)
    • 2x Status LED
    • DIP Switch
    • Push Buttons
  • Interface
    • Gigabit RJ45 LAN socket
    • SD Card socket
    • Micro USB2.0 Socket
    • USB A Socket
    • 3x High Speed CRUVI B2B Connectors
    • 1x Low Speed CRUVI B2B Connector
    • 4x Jumpers
  • Power
    • 5V Input Power Supply 
  • Dimension
    • 135 x 68 mm
  • Notes

...

Scroll Title
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titleTEB0707 block diagram


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Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


Note

For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .

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titleTEB0707 main components


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  1. Barrel Jack Power Supply, J1
  2. Voltage Regulator, U1
  3. Micro SD Card Socket, J8
  4. Micro USB2.0 Socket, J15
  5. FT2232H FTDI, U8
  6. USB A Socket, J9
  7. RJ45 LAN Socket, J2
  8. SDIO Port Expander, U4
  9. Jumpers, J4...7
  10. Push Button (Reset), S2
  11. DIP Switch, S1
  12. B2B Connector, JB3
  13. B2B Connector, JB2
  14. B2B Connector, JB1
  15. Intel MAX 10 FPGA, U6
  16. High speed Speed CRUVI Connector, J10
  17. High speed Speed CRUVI Connector, J11
  18. High speed Speed CRUVI Connector, J12
  19. Low Speed CRUVI Connector, J13
  20. User Push Button, S3
  21. JumperPin header, J3

Initial Delivery State

...

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titleBoot process.

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MODE Signal State

Boot Mode

MODESoM Mode control pin (depnds on SoM

Boot Mode:

  • SD Card (Low)
  • QSPI (High)
PROGMODE

Programming Mode:

  • select between CPLD (low, closed, on)
  • on SoM or FPGA/SoC (high, open, off )


...

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titleReset process.

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Signal

B2B		Connected toI/ONote

Reset

Push Button, S2

RESIN

JB2- 17OutSoM Module Reset signal


Signals, Interfaces and Pins

...

Interfaces and Number of I/O signals connected to the B2B connectors for Trenz 4x5 modules:

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B2B ConnectorInterfaceI/O Signal CountConnected toNotes
JB1


Ethernet LAN8x Single ended, 4x Diff pairsRJ45 Socket, J2
SD  Card6 x Single EndedIO Expander, U4
I/Os20x Single EndedMAX10 FPGA BAnk Bank 6, U6
CRUVI

20x 12x Diff pairs/24x Single ended, 10x Diff pairs

4x Single Ended

High Speed CRUVI, J12CRUVI C
SoM Control Signals5x Single EndedMAX10 FPGA, U6
I/Os8x Single endedMAX10 FPGA Bank 8, U6VBAT1x Single Ended
Pin Header, J3JB2

CRUVI

8x 12x Diff pairs/24x Single ended, 4x Diff pairs

4x Single Ended

High Speed CRUVI, J10CRUVI A
CRUVI6x Diff pairs/12x Single ended, 6x Diff pairsHigh Speed CRUVI, J11CRUVI B
JTAG4x Single EndedFPGA Bank 5, U6
JB3CRUVI

6x Diff pairs/12x Single ended, 6x Diff pairs

4x Single Ended

High Speed CRUVI, J11CRUVI B
USB 

1x Diff pair,

4x

2x Single Ended

USB A, J9


CRUVI B2B Connectors

...

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FPGA Bank 8 U6B2B JB1FPGA Bank 3 U6B2B JB3FPGA Bank 2 U6B2B JB2
SpeedDesignatorsSchematicConnected toNotes
High



CRUVI C, J12A0...A5 (N/P)B2B, JB1
B0...B5 (N/P)B2B, JB1
MODE, REFCLK, SMB_ALERT, SMB_SDA, SMB_SCLFPGA Bank 8, U6DI, SEL, DO, DI, SCK,SELMAX10 FPGA Bank 8, U63.3V User IOs (Max10 Firmware dependent)
HSIO, HI, HO, RESET B2B, JB1
High


CRUVI B, J11A0...A5 (N/P)B2B, JB1
B0...B5 (N/P)B2B, JB1
MODE, REFCLK, SMB_ALERT, SMB_SDA, SMB_SCLFPGA Bank 2, U6DI, SEL, DO, DI, SCK,SELMAX10 FPGA Bank 2/3, U63.3V User IOs (Max10 Firmware dependent)
HSIO, HIHSI, HOHSO, RESET B2B, JB3
High



CRUVI A, J13



A0...A5 (N/P)B2B, JB2
B0...B5 (N/P)B2B, JB2

MODE, REFCLK

,

SMB_ALERT, SMB_SDA, SMB_SCL

FPGA Bank 3, U6DI

, SEL, DO, DI, SCK

,SEL

MAX10 FPGA Bank 2/3, U63.3V User IOs (Max10 Firmware dependent)
HSIO, HIHSI, HOHSO, RESET B2B, JB2
LowCRUVIX0...X7MAX10 FPGA Bank 1A, U6



JTAG Interface

JTAG

...

signals form FTDI U8  are routed to MAX10 CPLD. Via dip setting JTAG of MAX10 or JTAG of the connected Trenz 4x5 module can be selected. Forwarding signals to SoM is MAX10 Firmware dependent.

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JTAG Signal

B2B Connector

M_TMSJB2-94
M_TDIJB2-96
M_TDOJB2-100
M_TCK

JB2-98

VCCJTAGJB2-92

...

MAX10 Pin Bank 1B, U6

Connected to

TMSG1FTDI (U8) - ADBUS3
TDIF5FTDI (U8) - ADBUS1
TDOF6FTDI (U8) - ADBUS2
TCKG2

FTDI (U8) - ADBUS0

JTAGENE5Dip S1-4


JTAG access to the Trenz 4x5 module is through B2B connector JB2.

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JTAG Signal

Connected to

MAX10 Pin Bank5, U6

B2B Connector

M_TMS
FTDI (U8) - ADBUS3
L12JB2-94
M_TDI
FTDI (U8) - ADBUS1
L13JB2-96
M_TDO
FTDI (U8) - ADBUS2
J10JB2-100
M_TCK
FTDI (U8) - ADBUS0
H8

JB2-98

VCCJTAGJ11, J12JB2-92


SD Card

...

socket

The TEB0707 is equipped with an Micro SD Card readerslot, J8. Data for USBs are expanded through For levelshifting an IO Expander (U4) is used.

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Pin SchematicConnected toNotes
DAT0...3ESD_DAT0...3B2B, JB1Through IO Expander, U4
CMDESD_CMDB2B, JB1Through IO Expander, U4
VDD3.3V_SDB2B, JB1Through IO Expander, U4
CLKESD_CLKB2B, JB1Through IO Expander, U4
DLTSD_CDFPGA Bank 3, U6Card detect.


Micro USB2.0 Socket

There is a micro USB2.0 Socket, J15 provided in order to communicate with the FTDI, U8. Data signals from USB2.0 are passed through a Line Filter L4 and a Diode U9 in order to be protected against inverse polarity connection.

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Pin SchematicConnected toNotes
D+O2-DVbusVBUSB2B, JB3D+O2-D_PB2B, JB3Through Line Filter, L4
D-O2-D_NB2B, JB3Through Line Filter, L4
VbusVBUSB2B, JB3


 USB A Socket

The SoM USB 2.0 signals are routed to a USB A socket (host).

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VCC
Pin SchematicConnected toNotes
USB_VBUSB2B, JB3Data+O2-D_PB2B, JB3Through Line Filter, L1
Data-O2-D_NB2B, JB3Through Line Filter, L1
VCCUSB_VBUSB2B, JB3


RJ45 LAN Socket

There is a RJ45 Ethernet LAN SocketMagJack, J2 connected to B2B, JB1 via 4x channels data receive and transmit.

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titleRJ45 LAN Socket information

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Pin SchematicConnected toNotes
2PHY_MDI0_PB2B, JB1
3PHY_MDI0_NB2B, JB1
4PHY_MDI1_PB2B, JB1
5PHY_MDI1_NB2B, JB1
6PHY_MDI2_PB2B, JB1
7PHY_MDI2_NB2B, JB1
8PHY_MDI3_PB2B, JB1
9PHY_MDI3_NB2B, JB1
VCCETH-VCCB2B, JB1
Green LEDETH1_LED0Intel MAX 10, U6Link/Activity indicatorMAX10 Firmware dependent
Yellow LEDETH1_LED1Intel MAX 10, U6Speed indicatorMAX10 Firmware dependent


Jumpers

There are three Jumpers provided to choose the CRUVI Extension power voltage.

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DesignatorSchematicConnected toNotes
J14VCCIO_CCB2B, JB2CRUVI C
J16VCCIO_CBB2B, JB2CRUVI B
J17VCCIO_CAB2B, JB2CRUVI A


Pin Header

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DesignatorSchematicConnected toNotes
J3VBATB2B, JB1


Test Points

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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

Test PointSignalB2BNotes
10PWR_PL_OKJ2-120


...

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titleOn board peripherals

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Chip/InterfaceDesignatorNotes
Intel MAX 10U6
FTDIU8SDIO Expander
105698015U4U10FTDI, programmed with Xilinx licenceEEPROMU10
OscillatorU7
LEDs105698015D1...8

LEDs


DIP SwitchS1
Push ButtonsS2, S3


Intel Max10 CPLD

The TEB0707 is quipped with an Intel Max10 as CPLD used for levelshifting of 3.3V signals on CRUVI connectors, JTAG/UART forward to modules, Module control pis, power sequencing and IO voltage selection along with providing User Push buttons, LEDs and switches. For complete information, please see the TEB0707 MAX10 CPLD.

FTDI FT2232H

The FTDI chip (U8) converts signals from USB2 to variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip which is used in  Multi-Protocol Synchronous Serial Engine (MPPSE) mode for JTAG. 

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U10.

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titleFTDI chip interfaces and pins

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PinSchematicConnected toNotes
ADBUS0TCKFPGA Bank 1B, U6JTAG interface
ADBUS1TDIFPGA Bank 1B, U6
ADBUS2TDOFPGA Bank 1B, U6
ADBUS3TMS

FPGA Bank 1B, U6

BDBUS0F_UART_TXFPGA Bank 1B, U6UART Transmitter output
BDBUS1F_UART_RXFPGA Bank 1B, U6UART Receiver Input
OSCIOSCIOscillator, U7Clock 12 MHz
EECSEECSEEPROM, U10EEPROM Contains FTDI configuration
EECLKEECLKEEPROM, U10
EEDATAEEDATAEEPROM, U10
DM/DPFD_N/ FD_PMicro USB, J15USB to UART
nRESET3.3V3.3V


LEDs

The functions of the LEDs are MAX10 Firmware dependent. See TEB0707 MAX10 CPLD LEDs.

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DesignatorColorSchematicConnected toActive LevelNote
D1greenLED3FPGA Bank 8Active High
D2greenLED5FPGA Bank 8Active High
D3greenLED7FPGA Bank 8Active High
D4redLED4FPGA Bank 3Active High
D5redLED6FPGA Bank 2Active High
D6redLED8FPGA Bank 8Active High
D7redLED2FPGA Bank 3Active High
D8greenLED1FPGA Bank 3Active High


EEPROM

The EEPROM IC, U8 contains the FTDI configuration and is prprogrammed with Xilinx JTAG licence.

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titleI2C EEPROM interface MIOs and pins

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PinSchematicConnected toNotes
CSEECSFTDI, U8
CLKEECLKFTDI, U8
DINEEDATAFTDI, U8


DIP Switch

There is a DIP Switch provided for user controlling of settings. Dip1..3 are connected to MAX10 CPLD and therefore function is Firmware dependent, see TEB0707 MAX10 Dips.

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titleDIP Switch connections

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PinSchematicFunction (in standard Firmware)Notes
DIP1DIP1Forwarded to IO so SoM

MAX10 firmware dependent.

DIP2DIP2IO Voltage selection1.8V ('high', open, OFF), 2.5V ('low', closed, ON)
DIP3DIP3 (PROGMODE)Programming mode (JTAG selection on Trenz 4x5 module)Select between FPGA/SoC (high, open, OFF ) or CPLD (low, closed, ON), MAX10 firmware dependent.
DIP4JTAGENJTAG SelectionJTAG mode between CPLD (high, closed, ON) or SoM (low, open, OFF)


Push Buttons

Buttons are connected MAX10 CPLD and therefore function is Firmware dependent, see TEB0707 MAX10 CPLD Buttons

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titlePush Buttons informations
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titleOn-board LEDs

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Designator
ColorSchematicConnected toActive LevelNoteD2GreenLED3FPGA Bank 3Active HighD3GreenLED5FPGA Bank 3Active HighD4GreenLED7FPGA Bank 3Active HighD5GreenLED4FPGA Bank 8Active HighD6GreenLED6FPGA Bank 2Active HighD7GreenLED8FPGA Bank 8Active HighD8GreenLED2FPGA Bank 8Active HighD9GreenLED1FPGA Bank 8Active High

EEPROM

SchematicFunction (in standard Firmware)Notes
S2RESETSoM ResetHardware debounced.
S3BUTTON1User Buttondebounced in Max10 FPGA


Clock Sources

MEMS U7 Oscillator is nedded for FTDI. It is  additionally connectd to MAX 10 FPGA Bank 2 Pin H4 and can be used in custom Firmware.

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titleOsillators

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DesignatorDescriptionFrequencyNote
U7MEMS Oscillator12 MHz


Power and Power-On Sequence

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • |Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power supply with minimum current capability of 3 A for system startup is recommended.

Power Consumption

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titleI2C EEPROM interface MIOs and pinsPower Consumption

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Power Input Pin
Schematic
Typical Current
Connected to
VIN
NotesCSEECSFTDI, U8CLKEECLKFTDI, U8DINEEDATAFTDI, U8
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I2C AddressDesignatorNotes
A0U10

Clock Sources

...

anchorTable_OBP_CLK
titleOsillators

...

Power and Power-On Sequence

...

hiddentrue
idComments

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • |Power on-sequence
  • Power distribution
  • Voltage monitoring circuit
Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

TBD*


* TBD - To Be Determined

Power Distribution Dependencies

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titlePower Distribution


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Power-On Sequence

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Power Rails

Power Supply

Power supply with minimum current capability of xx A for system startup is recommended.

...

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Power
Input Pin
Typical Current
VINTBD*

* TBD - To Be Determined

Power Distribution Dependencies

...

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titlePower Distribution

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Power-On Sequence

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titlePower Sequency

...

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Voltage Monitor Circuit

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Rail Name

B2B Connector

JB1 Pin

B2B Connector

JB2 Pin

B2B Connector

JB3 Pin

DirectionNotes
VCCIO_CA-8, 10-Output
VCCIO_CB-2, 4, 6-Output
VCCIO_CC10, 12--Output

3.3V 

14, 16--Output
M1.8VOUT40--Input
M3.3VOUT-9, 11-Input
ETH-VCC13--Input


Bank Voltages

Below MAX10 CPLD Bankvoltages are summarized.

Power Rails

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titleModule power railsZynq SoC bank voltages.

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Bank          

Schematic
Power Rail
Name

B2B Connector

JM1 Pin

B2B Connector

JM2 Pin

B2B Connector

JM3 Pin

Direction

Voltage

Notes
Bank

...

1A3.3V3.3V
Bank 1B

3.3V

3.3V
Bank 23.3V3.3V
Bank 33.3V3.3V
Bank 5VCCJTAG
from SoM
Bank 6VCCIO_CC

Variable

Bank 83.3V3.3V
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Notes

Bank          

Schematic Name

Voltage




Board to Board Connectors

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  • This section is optional and only for modules.

  • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors

    Include Page
    PD:6 x 6 SoM LSHM B2B ConnectorsPD:
    6 x 6 SoM LSHM B2B Connectors

Include Page
PD:4 x 5 SoM LSHM B2B ConnectorsPD:
4 x 5 SoM LSHM LSHM B2B Connectors

CRUVI Connectors

Include Page
CRUVI B2B Connectors
CRUVI B2B Connectors

Technical Specifications

...

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SymbolsDescriptionMinMaxUnit
5VINInput supply Voltage-4060V
T_STGStorage Temperature-4085°C


Recommended Operating Conditions

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ParameterMinMaxUnitsReference Document
Input supply Voltage4.065.58VSee ???? the OV/UV in the carrier datasheets.
T_OPT070°CSee  Push Button °CSee Xilinx ???? datasheet.


Physical Dimensions

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titlePhysical Dimension


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Documentation Link
DateRevisionChangesDocumentation Link
2020-11-20REV02first production releaseREV02DateRevisionChanges
2020-04-01REV01PrototypesInitial Release-


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

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Disclaimer

Include Page
IN:Legal Notices
IN:Legal Notices
Include Page
IN:Legal NoticesIN:Legal Notices
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