Versions Compared

Old Version 4

changes.mady.by.user Pedram Babakhani

Saved on

compared with

New Version Current

changes.mady.by.user Martin Rohrmüller

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

Overview

The Trenz Electronic TE0xxx-xx ... is an industrial-grade ... module ... based on Xilinx ...TEB0707 is a carrier for 4 x 5 Trenz Electronic modules. It provides three high speed and one low speed CRUVI extension connectors. For more information, please refer to the CRUVI B2B Connectors. The TEB0707 is integrated with an Intel MAX10 FPGA as system controller and is equipped with a Micro USB2.0 Socket with FTDI to JTAG/UART solution, RJ45 LAN Socket, USB A Socket, Micro SD Card Socket, User LEDs, Push Buttons and DIP Switches for controlling the SoM.

Refer to http://trenz.org/teb0707Refer to http://trenz.org/tec0850-info for the current online version of this manual and other available documentation.

...

Page properties
hiddentrue
idComments

Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features'  must be split into 6 main groups for modules and mainboards:

  • SoC/FPGA
    • Package: SFVC784
    • Device: ZU2...ZU5*
    • Engine: CG, EG, EV*
    • Speed: -1LI, -2LE,*, **
    • Temperature: I, E,*, **
  • RAM/Storage
    • Low Power DDR4 on PS
      • Data width: 32bit
      • Size: def. 2GB*
      • Speed:***
    • eMMC
      • Data width: 8Bit
      • size: def. 8GB *
    • QSPI boot Flash in dual parallel mode (size depends on assembly version)
      • Data width: 8bit
      • size: def. 128MB *
    • HyperRAM/Flash (optional, default not assembled)
      • size:*
    • MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
  • On Board
    • Lattice LCMXO2
    • PLL SI5338
    • Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
    • Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
  • Interface
    • 132 x HP PL I/Os (3 banks)
    • ETH
    • USB
    • 4 GTR (for USB3, Sata, PCIe, DP)
    • MIO for UART
    • MIO for SD
    • MIO for PJTAG
    • JTAG
    • Ctrl
  • Power
    • 3.3V-5V Main Input
    • 3.3V Controller Input
    • Variable Bank IO Power Input
  • Dimension
    • 4 cm x 5 cm
  • Notes
    • * depends on assembly version
    • ** also non low power assembly options possible
    • *** depends on used U+ Zynq and DDR4 combination


Key Features'  must be split into 6 main groups for carrier:

  • Modules
    • TE0808, TE807, TE0803,...
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension


  • <Replace for module use "SoC/FPGA" for Carrier "Modules">
    • 4x5 Trenz Electronic modules
    • ...
  • RAM/Storage
    • ...EEPROM (FTDI Configuration)
  • On Board
      • ...
    • Interface
      • ...
    • Power
      • ...
    • Dimension
      • ...
      • Intel Max 10 FPGA
      • FTDI FT2223
      • 6x User LEDs (3x green, 3x red)
      • 2x Status LED
      • DIP Switch
      • Push Buttons
    • Interface
      • Gigabit RJ45 LAN socket
      • SD Card socket
      • Micro USB2.0 Socket
      • USB A Socket
      • 3x High Speed CRUVI B2B Connectors
      • 1x Low Speed CRUVI B2B Connector
      • 4x Jumpers
    • Power
      • 5V Input Power Supply 
    • Dimension
      • 135 x 68 mm
    • NotesNotes...


    Block Diagram

    Page properties
    hiddentrue
    idComments

    add drawIO object here.

    Note

    For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


    ...

    Scroll Title
    anchorFigure_OV_BD
    titleTEB0707 block diagram


    Scroll Ignore

    draw.io Diagram
    borderfalse
    diagramNameTEB0707_OV_BD
    simpleViewerfalse
    width639
    linksauto
    tbstylehidden
    diagramDisplayName
    lboxtrue
    diagramWidth641
    revision

    1

    23



    Scroll Only

    |


    Main Components

    Page properties
    hiddentrue
    idComments

    Notes :

    • Picture of the PCB (top and bottom side) with labels of important components
    • Add List below


    Note

    For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .

    draw.io Diagram
    borderfalse
    diagramNameTEB0707_OV_BD
    simpleViewerfalse
    width639
    linksauto
    tbstylehidden
    diagramDisplayName
    lboxtrue
    diagramWidth641
    revision23



    scrollscroll-title
    anchorFigure_OV_MC
    titleTEB0707 main components


    Scroll Ignore
    draw.io Diagram
    borderfalse
    diagramNameTEB0707_OV_MC
    simpleViewerfalse
    width639
    linksauto
    tbstylehidden
    diagramDisplayName
    lboxtrue
    diagramWidth641
    revision16


    Scroll Only

    1. ...
    2. ...
    3. ...

    Initial Delivery State

    Page properties
    hiddentrue
    idComments

    Notes :

    Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

    If there is no components which might have initial data ( possible on carrier) you must keep the table empty

    ...

    anchorTable_OV_IDS
    titleInitial delivery state of programmable devices on the module


    1. Barrel Jack Power Supply, J1
    2. Voltage Regulator, U1
    3. Micro SD Card Socket, J8
    4. Micro USB2.0 Socket, J15
    5. FT2232H FTDI, U8
    6. USB A Socket, J9
    7. RJ45 LAN Socket, J2
    8. SDIO Port Expander, U4
    9. Jumpers, J4...7
    10. Push Button (Reset), S2
    11. DIP Switch, S1
    12. B2B Connector, JB3
    13. B2B Connector, JB2
    14. B2B Connector, JB1
    15. Intel MAX 10 FPGA, U6
    16. High Speed CRUVI Connector, J10
    17. High Speed CRUVI Connector, J11
    18. High Speed CRUVI Connector, J12
    19. Low Speed CRUVI Connector, J13
    20. User Push Button, S3
    21. Pin header, J3

    Initial Delivery State

    Page properties
    hiddentrue
    idComments

    Notes :

    Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

    If there is no components which might have initial data ( possible on carrier) you must keep the table empty

    ...

    Storage device name

    ...

    Content

    ...

    Notes

    ...

    Quad SPI Flash

    ...

    Configuration Signals

    Page properties
    hiddentrue
    idComments
    Overview of Boot Mode, Reset, Enables.


    Scroll Title
    anchorTable_OV_BPIDS
    titleBoot process.Initial delivery state of programmable devices on the module

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Storage device name

    Content

    Notes

    EEPROMProgrammed

    FTDI Configuration


    Configuration Signals

    Boot Mode
    Page properties
    hiddentrue
    idComments
    • Overview of Boot Mode, Reset, Enables.

    MODE Signal State


    Scroll Title
    anchorTable_OV_RSTBP
    titleReset Boot process.

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    MODE Signal State

    		B2BI/ONote

    Signals, Interfaces and Pins

    Page properties
    hiddentrue
    idComments

    Notes :

    • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
      • SD
      • USB
      • ETH
      • FMC
      • ...
    • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
      • JTAG
      • UART
      • I2C
      • MGT
      • ...

    Board to Board (B2B) I/Os

    FPGA bank number and number of I/O signals connected to the B2B connector:

    ...

    anchorTable_SIP_B2B
    titleGeneral PL I/O to B2B connectors information

    ...

    Boot Mode

    MODE

    Boot Mode:

    • SD Card (Low)
    • QSPI (High)
    PROGMODE

    Programming Mode:

    • select between CPLD (low, closed, on)
    • on SoM or FPGA/SoC (high, open, off )



    Scroll Title
    anchorTable_OV_RST
    titleReset process.

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Signal

    		Connected toI/ONote

    Reset

    		Push Button, S2OutModule Reset signal


    Signals, Interfaces and Pins

    Page properties
    hiddentrue
    idComments

    Notes :

    • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
      • SD
      • USB
      • ETH
      • FMC
      • ...
    • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
      • JTAG
      • UART
      • I2C
      • MGT
      • ...

    Board to Board (B2B)

    Interfaces and Number of I/O signals connected to the B2B connectors for Trenz 4x5 modules:

    ...

    JTAG access to the TExxxx SoM through B2B connector JMX.

    Scroll Title
    anchorTable_SIP_JTGB2B
    titleJTAG pins connectionGeneral PL I/O to B2B connectors information

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    JTAG Signal

    B2B Connector
    TMSTDITDOTCKJTAG_EN

MIO Pins

...

hiddentrue
idComments

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

InterfaceI/O Signal CountConnected toNotes
JB1


Ethernet LAN4x Diff pairsRJ45 Socket, J2
SD  Card6 x Single EndedIO Expander, U4
I/Os20x Single EndedMAX10 FPGA Bank 6, U6
CRUVI

12x Diff pairs/24x Single ended

4x Single Ended

High Speed CRUVI, J12CRUVI C
SoM Control Signals5x Single EndedMAX10 FPGA, U6
I/Os8x Single endedMAX10 FPGA Bank 8, U6
JB2

CRUVI

12x Diff pairs/24x Single ended

4x Single Ended

High Speed CRUVI, J10CRUVI A
CRUVI6x Diff pairs/12x Single endedHigh Speed CRUVI, J11CRUVI B
JTAG4x Single EndedFPGA Bank 5, U6
JB3CRUVI

6x Diff pairs/12x Single ended

4x Single Ended

High Speed CRUVI, J11CRUVI B
USB 

1x Diff pair,

2x Single Ended

USB A, J9


CRUVI B2B Connectors

The TEMB0707 is equipped with a Low Speed Connectors J 13 and three High Speed Connector J10...12. These connectors are provided for CRUVI extension cards. More information is provided in the  B2B Connectors section.

...

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

...

anchorTable_SIP_MIOs
titleMIOs pins

...

Test Points

...

hiddentrue
idComments

you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

...

Scroll Title
anchorTable_SIP_TPsCRUVIB2B
titleTest Points InformationCRUVI B2B connectors information

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Speed
Test Point
Designators
Signal
SchematicConnected toNotes

On-board Peripherals

Page properties
hiddentrue
idComments

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs
Page properties
hiddentrue
idComments

Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

...

anchorTable_OBP
titleOn board peripherals
High



CRUVI C, J12A0...A5 (N/P)B2B, JB1
B0...B5 (N/P)B2B, JB1
MODE, REFCLK, SMB_ALERT, SMB_SDA, SMB_SCL, SEL, DO, DI, SCKMAX10 FPGA Bank 8, U63.3V User IOs (Max10 Firmware dependent)
HSIO, HI, HO, RESET B2B, JB1
High


CRUVI B, J11A0...A5 (N/P)B2B, JB1
B0...B5 (N/P)B2B, JB1
MODE, REFCLK, SMB_ALERT, SMB_SDA, SMB_SCL, SEL, DO, DI, SCKMAX10 FPGA Bank 2/3, U63.3V User IOs (Max10 Firmware dependent)
HSIO, HSI, HSO, RESET B2B, JB3
High



CRUVI A, J13



A0...A5 (N/P)B2B, JB2
B0...B5 (N/P)B2B, JB2

MODE, REFCLK, SMB_ALERT, SMB_SDA, SMB_SCL, SEL, DO, DI, SCK

MAX10 FPGA Bank 2/3, U63.3V User IOs (Max10 Firmware dependent)
HSIO, HSI, HSO, RESET B2B, JB2
LowCRUVIX0...X7MAX10 FPGA Bank 1A, U6



JTAG Interface

JTAG signals form FTDI U8  are routed to MAX10 CPLD. Via dip setting JTAG of MAX10 or JTAG of the connected Trenz 4x5 module can be selected. Forwarding signals to SoM is MAX10 Firmware dependent.

scroll

...

Quad SPI Flash Memory

Page properties
hiddentrue
idComments

Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

scroll-title
anchorTable_OBPSIP_SPIMJTG
titleQuad SPI interface MIOs and JTAG pins connection

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

JTAG Signal

MIO
MAX10 Pin
SchematicU?? PinNotes

...

Bank 1B, U6

Connected to

TMSG1FTDI (U8) - ADBUS3
TDIF5FTDI (U8) - ADBUS1
TDOF6FTDI (U8) - ADBUS2
TCKG2

FTDI (U8) - ADBUS0

JTAGENE5Dip S1-4


JTAG access to the Trenz 4x5 module is through B2B connector JB2.

Scroll Title
anchorTable_OBPSIP_RTCMJTG
titleI2C interface MIOs and JTAG pins connection

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

MIO PinSchematicU? PinNotes
Scroll Title
anchorTable_OBP_I2C_RTC
titleI2C Address for RTC
Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
stylewidths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue
MIO PinI2C AddressDesignatorNotes

...

JTAG Signal

MAX10 Pin Bank5, U6

B2B Connector

M_TMSL12JB2-94
M_TDIL13JB2-96
M_TDOJ10JB2-100
M_TCKH8

JB2-98

VCCJTAGJ11, J12JB2-92


SD Card socket

The TEB0707 is equipped with an Micro SD Card slot, J8. For levelshifting an IO Expander (U4) is used.

Scroll Title
anchorTable_OBPSIP_EEPSD Card
titleI2C EEPROM interface MIOs and pinsUSB2.0 Socket information

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

MIO Pin
Pin Schematic
U?? Pin
Connected toNotes
Scroll Title
anchorTable_OBP_I2C_EEPROM
titleI2C address for EEPROM
Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
stylewidths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue
MIO PinI2C AddressDesignatorNotes

...

DAT0...3ESD_DAT0...3B2B, JB1Through IO Expander, U4
CMDESD_CMDB2B, JB1Through IO Expander, U4
VDD3.3V_SDB2B, JB1Through IO Expander, U4
CLKESD_CLKB2B, JB1Through IO Expander, U4
DLTSD_CDFPGA Bank 3, U6Card detect.


Micro USB2.0 Socket

There is a micro USB2.0 Socket, J15 provided in order to communicate with the FTDI, U8.

Scroll Title
anchorTable_OBPSIP_LEDUSB2
titleOn-board LEDsMicro USB2.0 Socket information

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Designator
Pin 
Color
SchematicConnected to
Active Level
Notes
Note

DDR3 SDRAM

Page properties
hiddentrue
idComments

Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

  • Part number: 
  • Supply voltage:
  • Speed: 
  • NOR Flash
  • Temperature: 

Ethernet

D+O2-D_PB2B, JB3Through Line Filter, L4
D-O2-D_NB2B, JB3Through Line Filter, L4
VbusVBUSB2B, JB3


 USB A Socket

The SoM USB 2.0 signals are routed to a USB A socket (host).

Scroll Title
anchorTable_SIP_USBA
titleUSB A Socket information

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Pin SchematicConnected toNotes
Data+O2-D_PB2B, JB3Through Line Filter, L1
Data-O2-D_NB2B, JB3Through Line Filter, L1
VCCUSB_VBUSB2B, JB3


RJ45 LAN Socket

There is a RJ45 Ethernet LAN MagJack, J2 connected to B2B, JB1.

Scroll Title
anchorTable_SIP_ETH
titleRJ45 LAN Socket information

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Pin SchematicConnected toNotes
2PHY_MDI0_PB2B, JB1
3PHY_MDI0_NB2B, JB1
4PHY_MDI1_PB2B, JB1
5PHY_MDI1_NB2B, JB1
6PHY_MDI2_PB2B, JB1
7PHY_MDI2_NB2B, JB1
8PHY_MDI3_PB2B, JB1
9PHY_MDI3_NB2B, JB1
VCCETH-VCCB2B, JB1
Green LEDETH1_LED0Intel MAX 10, U6MAX10 Firmware dependent
Yellow LEDETH1_LED1Intel MAX 10, U6MAX10 Firmware dependent


Jumpers

There are three Jumpers provided to choose the CRUVI Extension power voltage.

Scroll Title
anchorTable_SIP_Jumpers
titleJumpers information

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DesignatorSchematicConnected toNotes
J14VCCIO_CCB2B, JB2CRUVI C
J16VCCIO_CBB2B, JB2CRUVI B
J17VCCIO_CAB2B, JB2CRUVI A


Pin Header

Scroll Title
anchorTable_SIP_SMD
titleJumpers information

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DesignatorSchematicConnected toNotes
J3VBATB2B, JB1


Test Points

Page properties
hiddentrue
idComments

you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

Test PointSignalB2BNotes
10PWR_PL_OKJ2-120



Scroll Title
anchorTable_SIP_TPs
titleTest Points Information

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Test PointSignalConnected toNotes
TP13.3VRegulator, U1
TP2VINVoltage Protection, U2
TP4IOVRegulator, U3
TP53.3VPower Switch, Q1
TP6C5VINPower Switch, Q2


On-board Peripherals

Page properties
hiddentrue
idComments

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


Page properties
hiddentrue
idComments

Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


Scroll Title
anchorTable_OBP
titleOn board peripherals

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Chip/InterfaceDesignatorNotes
Intel MAX 10U6
FTDIU8
105698015U10FTDI, programmed with Xilinx licence
OscillatorU7
105698015D1...8
DIP SwitchS1
Push ButtonsS2, S3


Intel Max10 CPLD

The TEB0707 is quipped with an Intel Max10 as CPLD used for levelshifting of 3.3V signals on CRUVI connectors, JTAG/UART forward to modules, Module control pis, power sequencing and IO voltage selection along with providing User Push buttons, LEDs and switches. For complete information, please see the TEB0707 MAX10 CPLD.

FTDI FT2232H

The FTDI chip (U8) converts signals from USB2 to variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip which is used in  Multi-Protocol Synchronous Serial Engine (MPPSE) mode for JTAG. 

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U10.

Scroll Title
anchorTable_OBP_FT2232H
titleFTDI chip interfaces and pins

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

PinSchematicConnected toNotes
ADBUS0TCKFPGA Bank 1B, U6JTAG interface
ADBUS1TDIFPGA Bank 1B, U6
ADBUS2TDOFPGA Bank 1B, U6
ADBUS3TMS

FPGA Bank 1B, U6

BDBUS0F_UART_TXFPGA Bank 1B, U6UART Transmitter output
BDBUS1F_UART_RXFPGA Bank 1B, U6UART Receiver Input
OSCIOSCIOscillator, U7Clock 12 MHz
EECSEECSEEPROM, U10EEPROM Contains FTDI configuration
EECLKEECLKEEPROM, U10
EEDATAEEDATAEEPROM, U10
DM/DPFD_N/ FD_PMicro USB, J15USB to UART
nRESET3.3V3.3V


LEDs

The functions of the LEDs are MAX10 Firmware dependent. See TEB0707 MAX10 CPLD LEDs.

Scroll Title
anchorTable_OBP_LED
titleOn-board LEDs

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DesignatorColorSchematicConnected toActive LevelNote
D1greenLED3FPGA Bank 8Active High
D2greenLED5FPGA Bank 8Active High
D3greenLED7FPGA Bank 8Active High
D4redLED4FPGA Bank 3Active High
D5redLED6FPGA Bank 2Active High
D6redLED8FPGA Bank 8Active High
D7redLED2FPGA Bank 3Active High
D8greenLED1FPGA Bank 3Active High


EEPROM

The EEPROM IC, U8 contains the FTDI configuration and is prprogrammed with Xilinx JTAG licence.

Scroll Title
anchorTable_OBP_EEP
titleI2C EEPROM interface MIOs and pins

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

PinSchematicConnected toNotes
CSEECSFTDI, U8
CLKEECLKFTDI, U8
DINEEDATAFTDI, U8


DIP Switch

There is a DIP Switch provided for user controlling of settings. Dip1..3 are connected to MAX10 CPLD and therefore function is Firmware dependent, see TEB0707 MAX10 Dips.

Scroll Title
anchorTable_OBP_ETHDIP
titleEthernet PHY to Zynq SoC DIP Switch connections

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

U?? Pin Signal NameConnected toSignal DescriptionNote

CAN Transceiver

...

anchorTable_OBP_CAN
titleCAN Tranciever interface MIOs

...

PinSchematicFunction (in standard Firmware)Notes
DIP1DIP1Forwarded to IO so SoM

MAX10 firmware dependent.

DIP2DIP2IO Voltage selection1.8V ('high', open, OFF), 2.5V ('low', closed, ON)
DIP3DIP3 (PROGMODE)Programming mode (JTAG selection on Trenz 4x5 module)Select between FPGA/SoC (high, open, OFF ) or CPLD (low, closed, ON), MAX10 firmware dependent.
DIP4JTAGENJTAG SelectionJTAG mode between CPLD (high, closed, ON) or SoM (low, open, OFF)


Push Buttons

Buttons are connected MAX10 CPLD and therefore function is Firmware dependent, see TEB0707 MAX10 CPLD Buttons

...

Scroll Title
anchorTable_OBP_CLKBTN
titleOsillatorsPush Buttons informations

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Designator
DescriptionFrequencyNoteMHzMHzKHz

Programmable Clock Generator

SchematicFunction (in standard Firmware)Notes
S2RESETSoM ResetHardware debounced.
S3BUTTON1User Buttondebounced in Max10 FPGA


Clock Sources

MEMS U7 Oscillator is nedded for FTDI. It is  additionally connectd to MAX 10 FPGA Bank 2 Pin H4 and can be used in custom FirmwareThere is a programmable clock generator on-board (U??) provided in order to generate variable clocks for the module. Programming can be done using I2C via PIN header J??.  The I2C Address is 0x??.

OUT8/OUT9
Scroll Title
anchorTable_OBP_PCLKCLK
titleProgrammable Clock Generator Inputs and OutputsOsillators

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DesignatorDescriptionFrequencyNote
U7MEMS Oscillator12 MHz
U?? Pin
SignalConnected toDirectionNote

IN0

IN1IN2IN3

XAXB

SCLKSDAOUT0OUT1OUT2OUT3OUT4OUT5OUT6OUT7


Power and Power-On Sequence

Page properties
hiddentrue
idComments

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • |Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


...

Power supply with minimum current capability of xx 3 A for system startup is recommended.

...

* TBD - To Be Determined

Power Distribution DependenciesDependencies

Scroll Title
anchorFigure_PWR_PD
titlePower Distribution


draw.io Diagram
borderfalse
diagramNameTEB0707_PWR_DP
simpleViewerfalse
width639
linksauto
tbstylehidden
diagramDisplayName
lboxtrue
diagramWidth641
revision5


Scroll Only

Image Added


Power-On Sequence

Scroll Title
anchorFigure_PWR_PDPS
titlePower DistributionSequency


Scroll Ignore
draw.io Diagram
borderfalse
diagramNameTEB0707_PWR_PDPS
simpleViewerfalse
width639
linksauto
tbstylehidden
diagramDisplayName
lboxtrue
diagramWidth641
revision24


Scroll Only

Image RemovedImage Added


Power

...

Rails

Scroll Title
anchorFigureTable_PWR_PSPR
titlePower SequencyModule power rails.

scroll-

ignore

tablelayout

drawio

orientation

border

portrait

false

sortDirection

diagramNameTEB0707_PWR_PS
simpleViewerfalse
width
linksauto
tbstylehidden
diagramDisplayName
lboxtrue
diagramWidth641
revision1
Scroll Only

Image Removed

Voltage Monitor Circuit

...

anchorFigure_PWR_VMC
titleVoltage Monitor Circuit
Scroll Ignore

Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only

image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

ASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue


Power Rail Name

B2B Connector

JB1 Pin

B2B Connector

JB2 Pin

B2B Connector

JB3 Pin

DirectionNotes
VCCIO_CA-8, 10-Output
VCCIO_CB-2, 4, 6-Output
VCCIO_CC10, 12--Output

3.3V 

14, 16--Output
M1.8VOUT40--Input
M3.3VOUT-9, 11-Input
ETH-VCC13--Input


Bank Voltages

Below MAX10 CPLD Bankvoltages are summarized.

Power Rails

...

anchorTable_PWR_PR
titleModule power rails.

...

B2B Connector

JM1 Pin

...

B2B Connector

JM2 Pin

...

B2B Connector

JM3 Pin

...

Bank Voltages

Scroll Title
anchorTable_PWR_BV
titleZynq SoC bank voltages.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue
1
sortEnabledfalse
cellHighlightingtrue

Notes

Bank          

Schematic Name

Voltage

Notes
Bank 1A3.3V3.3V
Bank 1B

3.3V

3.3V
Bank 23.3V3.3V
Bank 33.3V3.3V
Bank 5VCCJTAG
from SoM
Bank 6VCCIO_CC

Variable

Bank 83.3V3.3V

Bank          

Schematic Name

Voltage




Board to Board Connectors

Page properties
hiddentrue
idComments
  • This section is optional and only for modules.

  • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors

    Include Page
    PD:6 x 6 SoM LSHM B2B ConnectorsPD:
    6 x 6 SoM LSHM B2B Connectors

? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.

3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)

Include Page
4 x 5 SoM LSHM B2B Connectors
4 x 5 SoM LSHM B2B Connectors

CRUVI Connectors

Include Page
CRUVI B2B Connectors
CRUVI B2B Connectors

...

Technical Specifications

Absolute Maximum Ratings

V
Scroll Title
anchorTable_TS_AMR
titlePS absolute maximum ratings

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

SymbolsDescriptionMinMaxUnit
5VINInput supply Voltage-4060
V
V
V
T_STGStorage Temperature-4085°C
VVVV