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changes.mady.by.user Pedram Babakhani

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Overview

The Trenz Electronic TE0xxx-xx ... is an industrial-grade ... module ... based on Xilinx ...TEMB0005 is a carrier for the module TEM00005. The carrier is equipped with a LAN socket, a FTDI JTAG/UART to USB2.0 solution, three low speed and one high speed CRUVI B2B Connectors, a PMod Connector.

Refer to http://trenz.org/temb0005-info for the current online version of this manual and other available documentation.

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Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features'  must be split into 6 main groups for modules and mainboards:

  • SoC/FPGA
    • Package: SFVC784
    • Device: ZU2...ZU5*
    • Engine: CG, EG, EV*
    • Speed: -1LI, -2LE,*, **
    • Temperature: I, E,*, **
  • RAM/Storage
    • Low Power DDR4 on PS
      • Data width: 32bit
      • Size: def. 2GB*
      • Speed:***
    • eMMC
      • Data width: 8Bit
      • size: def. 8GB *
    • QSPI boot Flash in dual parallel mode (size depends on assembly version)
      • Data width: 8bit
      • size: def. 128MB *
    • HyperRAM/Flash (optional, default not assembled)
      • size:*
    • MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
  • On Board
    • Lattice LCMXO2
    • PLL SI5338
    • Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
    • Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
  • Interface
    • 132 x HP PL I/Os (3 banks)
    • ETH
    • USB
    • 4 GTR (for USB3, Sata, PCIe, DP)
    • MIO for UART
    • MIO for SD
    • MIO for PJTAG
    • JTAG
    • Ctrl
  • Power
    • 3.3V-5V Main Input
    • 3.3V Controller Input
    • Variable Bank IO Power Input
  • Dimension
    • 4 cm x 5 cm
  • Notes
    • * depends on assembly version
    • ** also non low power assembly options possible
    • *** depends on used U+ Zynq and DDR4 combination


Key Features'  must be split into 6 main groups for carrier:

  • Modules
    • TE0808, TE807, TE0803,...
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension


  • <Replace for module use "SoC/FPGA" for Carrier "Modules">
    • ...TEM0005
  • RAM/Storage
    • ...2KB EEPROM
  • On Board
    • ...
  • Interface
    • ...
  • Power
    • ...
  • Dimension
    • ...
  • Notes
    • ...

Block Diagram

    • FT2232H FTDI
    • 4x User LEDs
    • 2x Push Buttons
    • 2x MEMS Oscillators
  • Interface
    • 1x Samtec Razor Beam (SS5) B2B Connector
    • 1x Samtec Razor Beam (SS4) High Speed CRUVI Connector
    • 3x Samtec Low Speed CRUVI Connectors
    • 1x PMod SMD (2x6) Connector
    • 1x SMD Header (1x6)
    • 1x RJ45 LAN Socket
    • 1x Micro USB2.0 Connector
  • Power
    • 5V Input Power Supply 
  • Dimension
    • 115 x 70 mm
  • Notes


Block Diagram

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add drawIO object here.

Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


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titleTEMB0005 block diagram


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Main Components

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titleTEMB0005 main components


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  1. SMD Header 6x1, J3
  2. RJ45 LAN Socket, J1
  3. B2B Connector, J11
  4. Barrel Jack, J4
  5. Green LEDs, D1
  6. ...
  7. ...
  8. ...

Initial Delivery State

  1. 4
  2. User Push Button, S2
  3. PMod 2x6 SMD Host Socket, J9
  4. FT2232H FTDI, U1
  5. Reset Push Button, S1
  6. Micro USB2.0 Socket, J2
  7. Red LED (PG_DCDC), D8
  8. Green LED (5VIN), D5
  9. High Speed CRUVI Connectors, J5
  10. Low Speed CRUVI Connectors, J8
  11. Low Speed CRUVI Connectors, J7
  12. Low Speed CRUVI Connectors, J6

Initial Delivery State

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Notes :

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

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titleInitial delivery state of programmable devices on the module

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System Controller CPLD

Storage device name

Content

Notes

EEPROM

Quad SPI Flash

ProgrammedFTDI ConfirgurationEEPROM


Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.

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titleBoot Reset process.

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MODE

Signal

State

Boot Mode
Scroll Title
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titleReset process.
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Signal

B2BI/ONote
B2BConnected toNote
M_RESETJ11- 11Push Button, S1Module Reset
EN_VADJJ11-110DCDC, U6pull-down, input from module
SEL_VADJJ11-108DCDC, U6

pull-up, input from module.
'low' → 1.8V,
'high'→ 2.5V


Signals, Interfaces and Pins

...

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:The carrier TEMB0005 is equipped with a Samtec (SS4) B2B Connector. More information in the following table.

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titleGeneral PL I/O to B2B B2B connectors information

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FPGA Bank
Designators
B2B Connector
InterfaceI/O Signal Count
Voltage Level
Connected toNotes

...

J11






JTAG

...

4x Single EndedFTDI, U1
MSIOD24x Single Ended, 12x Differential PairsCRUVI B2B, J5A0...5, B0...5 (N/P)
MSIO/GPIO8x Single EndedCRUVI B2B, J6A_X0...7
MSIO8x Single EndedCRUVI B2B, J7B_X0...7
MSIO/GPIO8x Single EndedCRUVI B2B, J8C_X0...7
LEDs (2x MSIO, 2x MSIO/GPIO)4x Single EndedD1...4LED1...4
MSIO8x Single EndedPmod Header, J9
Push Button1x Single EndedPush Button, S1M_RESET
Push Button1x Single EndedPush Button, S2pull-up, User Button
MSIO/GPIO/I2C2x Single EndedCRUVI B2B J6I2C
ETH

2x Differential Pairs

2x Single Ended

RJ45 Socket, J1

RJ45 LEDs, J1


Yellow and Green LEDs

UART2x Single EndedFTDI, U1UART RX/TX
FTDI I/O2x Single EndedFTDI, U1BDBUS2-BDBUS3
CLK

1x Single Ended

Oscillator, U8

30 MHz

MSIOD

4x Single Ended

CRUVI B2B, J5

RESET, HSIO, HSO, HSI

IO (3x MSIO, 4x MSIO/GPIO, 2x MSIO GPIO/I2C)9x Single EndedCRUVI B2B, J5
Power Signal1x Single Ended

RED LED, D8


PG_DCDC
SC_SPI4x Single Endedpin header, J3SC_CLK, SC_SDO, SC_SDI, SC_SS
GOLDEN1x Single EndedTestpoint, TP1GOLDEN
JTAGSEL1x Single EndedTestpoint, TP2JTAGSEL


CRUVI B2B Connectors

The TEMB0005 is equipped with three Low Speed Connectors J6...8 and a High Speed Connector J5. These connectors are provided for CRUVI extension cards. More information is provided in the  B2B Connectors section.

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titleJTAG pins connection

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JTAG Signal

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B2B Connector

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MIO Pins

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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

...

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

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titleMIOs pins

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Test Points

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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

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Signal
Scroll Title
anchorTable_SIP_TPsCRUVIB2B
titleTest Points InformationCRUVI B2B connectors information

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SpeedDesignatorsSchematic
Test Point
Connected toNotes

On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs
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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

LowJ6A_X0...1B2B, J11alternative GPIO

A_X2...5B2B, J11alternative SPI

A_X6...7B2B, J11alternative I2C0 SDA/SCL
J7B_X0...7|B2B, J11
J8C_X0...7B2B, J11alternative GPIO
HighJ5A0...A5 (N/P)B2B, J11HS I/O
B0...B5 (N/P)B2B, J11HS I/O
HSIO, HI, HO, RESETB2B, J11HS I/O single ended

SMB_ALERT, SMB_SDA, SMB_SCL, MODE, REFCLK

B2B, J11
DI,DO,SCK,SELB2B, J11alternative GPIO


USB2.0 Socket

There is a USB2.0 Socket, J2 provided in order to use JTAG/UART via FTDI, U1.

Designator
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titleUSB2.0 Socket information

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titleOn board peripherals

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Pin 
Chip/Interface
SchematicConnected toNotes

Quad SPI Flash Memory

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Notes :

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IDN.CN.C
D+DL_PFTDI, U1Through Line Filter, L1
D-DL_NFTDI, U1Through Line Filter, L1
VbusVBUSDiode, U2


RJ45 LAN Socket

There is a RJ45 Ethernet LAN Socket, J1 connected to B2B, J11 via 2x channels data receive and transmit.

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titleQuad SPI interface MIOs and pinsRJ45 LAN Socket information

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MIO Pin
Pin Schematic
U?? Pin
Connected toNotes

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anchorTable_OBP_RTC
titleI2C interface MIOs and pins
TD+ETH1_TX_PB2B, J11
TD-ETH1_TX_NB2B, J11
RD+ETH1_RX_PB2B, J11
RD-ETH1_RX_NB2B, J11
Green LEDETH1_LED0B2B, J11Link/Activity indicator
Yellow LEDETH1_LED1B2B, J11Speed indicator


PMod Header

There is a PMod Header, J9 connected to the B2B, J11 and all signals are protected from invers polarity by two diodes D6, D7.

...

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titleI2C Address for RTCPMod Header information

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MIO PinI2C AddressDesignatorNotes

...

SchematicConnected toNotes
PM0...3 (N/P)B2B, J11


Pin Header

There is a Pin Header 6x1, J3 provided for SPI signals. 

scroll-scroll-title
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titleI2C EEPROM interface MIOs and pinsPin Header connections

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MIO Pin
Pin Schematic
U?? Pin
Connected toNotes
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titleI2C address for EEPROM
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MIO PinI2C AddressDesignatorNotes

LEDs

13.3VB2B, J11
2GNDB2B, J11
3SC_SDOB2B, J11
4SC_SDIB2B, J11
5SC_SSB2B, J11
6SC_CLKB2B, J11


UART 

There is an UART channel provided in order to communicate with the module and signals are accessible via B2B, J11 through the FTDI, U1.

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titleOn-board LEDsUART connection

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Designator
U1 Pin
Color
SchematicConnected toNotes
Active LevelNote

DDR3 SDRAM

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Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

  • Part number: 
  • Supply voltage:
  • Speed: 
  • NOR Flash
  • Temperature: 

Ethernet

BDBUS1UART1_TXDB2B, J11FTDI receiver input
BDBUS0UART1_RXDB2B, J11FTDI transmitter output



JTAG Interface

JTAG access is provided through B2B connector J11 connected to the FTDI. For more information please refer to the FTDI section.

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titleJTAG pins connection

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JTAG Signal

B2B Connector

TMSJ11-14
TDIJ11-8
TDOJ11-10
TCK

J11-12

JTAGSELJ11-9


Test Points

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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

Test PointSignalB2BNotes
10PWR_PL_OKJ2-120



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titleTest Points Information

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Test PointSignalConnected toNotes
TP1GOLDENB2B, J11
TP2JTAGSELB2B, J11
TP3PG_DCDCB2B, J11Red LED, D8
TP4VADJRegulator, U6
TP5PROBE_BB2B, J11
TP6PROBE_AB2B, J11


On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


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titleOn board peripherals

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Chip/InterfaceDesignatorNotes
FTDIU1
105698017D1...D6
Push ButtonsS1-S2
105698017U3
Oscillator
U4, U8


FTDI FT2232H

The FTDI chip (U8) converts signals from USB2 to variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip which is used in  Multi-Protocol Synchronous Serial Engine (MPPSE) mode for JTAG. 

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U10.

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titleFTDI chip interfaces and pins

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PinSchematicConnected toNotes
ADBUS0TCKFPGA Bank 1B, U6JTAG interface
ADBUS1TDIFPGA Bank 1B, U6
ADBUS2TDOFPGA Bank 1B, U6
ADBUS3TMS

FPGA Bank 1B, U6

BDBUS0F_UART_TXFPGA Bank 1B, U6UART transmitter output
BDBUS1F_UART_RXFPGA Bank 1B, U6UART receiver input
BDBUS2BDBUS2B2B,J11I/O
BDBUS3BDBUS3B2B,J11I/O
OSCIOSCIOscillator, U4Clock 12 MHz
EECSEECSEEPROM, U3EEPROM Contains FTDI configuration
EECLKEECLKEEPROM, U3
EEDATAEEDATAEEPROM, U3
DM/DPD_N/ D_PMicro USB, J2USB to UART
nRESET3.3V3.3V


EEPROM

There is an EEPROM IC, U3 provided for storing the FTDI (U1) configuration. 

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PinSchematicNotes
DI/DOEEDATAData
CLKEECLKClock
CSEECSSelect


The I2C address is as the following.

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titleI2C address for EEPROM

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I2C AddressDesignatorNotes
0x70U3


Push Buttons

There are two Push Buttons provided on the TEMB0005 designated as S1, S2. The Push Button S2 is considered to be as user buttons and S1 is provided to reset the module on the carrier.

Signal Name
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titleEthernet PHY to Zynq SoC connectionsOn-board Push Buttons

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DesignatorSchematic
U?? Pin 
Connected to
Signal DescriptionNote